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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbf2ed900sm10386544f8f.53.2025.02.09.14.07.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 14:07:04 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Catalin Marinas , Will Deacon , Lee Jones Subject: [PATCH 01/10] arm64: Add SOPHGO SOC family Kconfig support Date: Sun, 9 Feb 2025 23:06:26 +0100 Message-ID: <20250209220646.1090868-2-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 First user will be Aarch64 core within SG2000 SoC. Signed-off-by: Alexander Sverdlin --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 02f9248f7c84..f45f3f05edf8 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -307,6 +307,18 @@ config ARCH_INTEL_SOCFPGA Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, Agilex and eASIC N5X. +config ARCH_SOPHGO + bool "Sophgo SoCs" + select CLK_SOPHGO_CV1800 + select MFD_SYSCON + select RESET_CONTROLLER + help + This enables support for Sophgo SoC platform hardware, such as + SG2000. + + Enable this option if you are going to boot your dual-ARCH SoC in + ARM64 mode. + config ARCH_STM32 bool "STMicroelectronics STM32 SoC Family" select GPIOLIB From patchwork Sun Feb 9 22:06:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Sverdlin X-Patchwork-Id: 13967119 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88B281FC10F for ; Sun, 9 Feb 2025 22:07:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739138830; cv=none; b=XId4NqrHKS0E/AjVxjdD3QFUOzKPYHNDdgcyc4FZWPwGIELsSW/yZbt+fx6pM1JroEo32Vx8f/fSBx7OwLJRkQlNKg1NJPWl2o3x03eWW90jkwlg6b8bilsbGK0jb11JtfX8gSLvIIi+nJa3b3sCIPTzgHPemPiGI1M32o6LluM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739138830; c=relaxed/simple; bh=Ef0EZwU1cUNDad9CKFLPDAxxX2z794AZA0ph/eyeCp0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nNkvpOgkZzVhFH7LxBIZd+1asH4WlbXpiQPmcWHw7xOWmlUEWi9QxACccB/Eo097fo94HTBBsHWxw1r5RQrGSle+IJcEKq2NfKB9e4pOk8pnMflhDsM9T4jrcWnZITzt3rygvo4WRyEZmh1so3DTB4AIxKahWSvNpjNFB936Umc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lFIVNT6T; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lFIVNT6T" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-38dcae0d6dcso1296588f8f.1 for ; Sun, 09 Feb 2025 14:07:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1739138827; x=1739743627; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BeQJSAdDhXmUj7Mhcp/EXCis2MZWrjN6L07LIferSPw=; b=lFIVNT6TUfQ+l+7/1fUH0o605ZCBWKzycBUl99qbzvKVwgqxevTEO0W+/XPm85Ufpd OroWhDjISSzxneaaPfyc8zstGoP8zI909ENVTRcrXWe5V2u5XJLHSjiPXMLE0FQjCuyv e80iHJ/6UEzyfn7YrKgFt283nCxGrEtmNA2M1Z5pAKq45pcPxXazGhOogL+FwVyubiMV 2IeC8LsuExbk74WCWm7HAKlSD0tEjgElw3Z0GgyljHCyDCS10KJc42T6tGF7wPYwbHdP MKJp21rAp01mUjF4hcESwXAo2Vl2B0TJ0LdDuLl9NagA/k7+Ba0jGQZDgX+J7apmXgYf YraA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739138827; x=1739743627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BeQJSAdDhXmUj7Mhcp/EXCis2MZWrjN6L07LIferSPw=; b=YxdfK46BhW8PTD1ncbIZG6WqiahxJtvFbm9cgXlRNWN+ivkgJza3bs5keeKHGZzrpk kr+fYPDA17F3/0gzx1HzJYUtv8aiYj5BwVQOsDHDLUvnGD1WkC4jv1+vLKe3JmWeY1Yj NijOitOCYFf+0lt8sM9hgYBcg+9HCCsGG9uCr/w04i+QOe/Ay35pFLAdu7FyhpSG/H/R 18zVsryrH0nPooGqYxoJvzJBNsPflvZTTc/nc6VtUNizsBJG3jQuuZjRCWkiAg/oLGxV lzDUtnoEiuK4HyiD+ODi+z1kVXfcuOOvg1SBOzElw8JiwPS8Gj44TzToqWvjQjudirlb 9w7w== X-Gm-Message-State: AOJu0Yw9OXuTtGahe97zsdxgEKHYLU5arlyqSlM1bDyblqjlCnhps2uL GOvkmmJuR2sfI1dYD1wrQo/RuJxhjl5OlcBCqBa5BmigcatPuVdDLB3fVfDx X-Gm-Gg: ASbGncujLq093HHNqDea/x8BBY6kzFTFwc+P9scMybboiNgCRdFYY9FEAV3DlWVr4pq EQToc9q3lTjyPn/MtVXXqkFBsjmGLyXg9K7Wk5sDWalQcjO1f3vLOqTPDJVM4ufMb8M808P9Zvs NHlIW/3JW83a6ICNcMNlqm7mTPbW9VYPp2OWtH50Yxm0PB8n0092RLKv3FMR1AAT7taiPxSj9qP ranoHkGhUMCUEcuNjF8xWu1W7BDTuNrNr4IfzVwhKgUF91M5Sj93jdDJYi0VLRucSyXrCu+yWHz loMx4x9Wn0xl1I5o4Lg5qvFD3o+q X-Google-Smtp-Source: AGHT+IGIPPTW7s6FMIHinxaydcbU4c1SdYr2UsWlxPFTGc738bi2zQ0yuQr39n6hlVqn6DA50ArXng== X-Received: by 2002:a5d:64cc:0:b0:38d:d701:419c with SMTP id ffacd0b85a97d-38dd701445emr3294852f8f.41.1739138826504; Sun, 09 Feb 2025 14:07:06 -0800 (PST) Received: from giga-mm.. ([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbf2ed900sm10386544f8f.53.2025.02.09.14.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 14:07:05 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts Date: Sun, 9 Feb 2025 23:06:27 +0100 Message-ID: <20250209220646.1090868-3-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Make the peripheral device tree re-usable on ARM64 platform by splitting it into CPU-core specific and peripheral parts. Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering into "plic" interrupt-controller numbering. Signed-off-by: Alexander Sverdlin --- arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +- arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 313 ++++++++++++++++++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 305 +---------------- 3 files changed, 317 insertions(+), 303 deletions(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi index 5fd14dd1b14f..bbdb30653e9a 100644 --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi @@ -11,7 +11,7 @@ soc { emmc: mmc@4300000 { compatible = "sophgo,cv1800b-dwcmshc"; reg = <0x4300000 0x1000>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clk CLK_AXI4_EMMC>, <&clk CLK_EMMC>; clock-names = "core", "bus"; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi new file mode 100644 index 000000000000..53834b0658b2 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Inochi Amaoto + */ + +#include +#include +#include + +/ { + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + clk: clock-controller@3002000 { + reg = <0x03002000 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + + gpio0: gpio@3020000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x3020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + gpio1: gpio@3021000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x3021000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + gpio2: gpio@3022000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x3022000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + gpio3: gpio@3023000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x3023000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + saradc: adc@30f0000 { + compatible = "sophgo,cv1800b-saradc"; + reg = <0x030f0000 0x1000>; + clocks = <&clk CLK_SARADC>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + channel@0 { + reg = <0>; + }; + + channel@1 { + reg = <1>; + }; + + channel@2 { + reg = <2>; + }; + }; + + i2c0: i2c@4000000 { + compatible = "snps,designware-i2c"; + reg = <0x04000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; + clock-names = "ref", "pclk"; + interrupts = ; + status = "disabled"; + }; + + i2c1: i2c@4010000 { + compatible = "snps,designware-i2c"; + reg = <0x04010000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; + clock-names = "ref", "pclk"; + interrupts = ; + status = "disabled"; + }; + + i2c2: i2c@4020000 { + compatible = "snps,designware-i2c"; + reg = <0x04020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; + clock-names = "ref", "pclk"; + interrupts = ; + status = "disabled"; + }; + + i2c3: i2c@4030000 { + compatible = "snps,designware-i2c"; + reg = <0x04030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; + clock-names = "ref", "pclk"; + interrupts = ; + status = "disabled"; + }; + + i2c4: i2c@4040000 { + compatible = "snps,designware-i2c"; + reg = <0x04040000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; + clock-names = "ref", "pclk"; + interrupts = ; + status = "disabled"; + }; + + uart0: serial@4140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = ; + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@4150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = ; + clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@4160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = ; + clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@4170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = ; + clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi0: spi@4180000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x04180000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; + clock-names = "ssi_clk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + spi1: spi@4190000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x04190000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; + clock-names = "ssi_clk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + spi2: spi@41a0000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x041a0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; + clock-names = "ssi_clk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + spi3: spi@41b0000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x041b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; + clock-names = "ssi_clk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + uart4: serial@41c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = ; + clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + sdhci0: mmc@4310000 { + compatible = "sophgo,cv1800b-dwcmshc"; + reg = <0x4310000 0x1000>; + interrupts = ; + clocks = <&clk CLK_AXI4_SD0>, + <&clk CLK_SD0>; + clock-names = "core", "bus"; + status = "disabled"; + }; + + sdhci1: mmc@4320000 { + compatible = "sophgo,cv1800b-dwcmshc"; + reg = <0x4320000 0x1000>; + interrupts = ; + clocks = <&clk CLK_AXI4_SD1>, + <&clk CLK_SD1>; + clock-names = "core", "bus"; + status = "disabled"; + }; + + dmac: dma-controller@4330000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x04330000 0x1000>; + interrupts = ; + clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <8>; + snps,block-size = <1024 1024 1024 1024 + 1024 1024 1024 1024>; + snps,priority = <0 1 2 3 4 5 6 7>; + snps,dma-masters = <2>; + snps,data-width = <4>; + status = "disabled"; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index c18822ec849f..57a01b71aa67 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -4,9 +4,9 @@ * Copyright (C) 2023 Inochi Amaoto */ -#include -#include -#include +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + +#include "cv18xx-periph.dtsi" / { #address-cells = <1>; @@ -41,310 +41,11 @@ cpu0_intc: interrupt-controller { }; }; - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_25m"; - #clock-cells = <0>; - }; - soc { - compatible = "simple-bus"; interrupt-parent = <&plic>; - #address-cells = <1>; - #size-cells = <1>; dma-noncoherent; ranges; - clk: clock-controller@3002000 { - reg = <0x03002000 0x1000>; - clocks = <&osc>; - #clock-cells = <1>; - }; - - gpio0: gpio@3020000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3020000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@3021000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3021000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio2: gpio@3022000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3022000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio3: gpio@3023000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3023000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - saradc: adc@30f0000 { - compatible = "sophgo,cv1800b-saradc"; - reg = <0x030f0000 0x1000>; - clocks = <&clk CLK_SARADC>; - interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - channel@0 { - reg = <0>; - }; - - channel@1 { - reg = <1>; - }; - - channel@2 { - reg = <2>; - }; - }; - - i2c0: i2c@4000000 { - compatible = "snps,designware-i2c"; - reg = <0x04000000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; - clock-names = "ref", "pclk"; - interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c1: i2c@4010000 { - compatible = "snps,designware-i2c"; - reg = <0x04010000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; - clock-names = "ref", "pclk"; - interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c2: i2c@4020000 { - compatible = "snps,designware-i2c"; - reg = <0x04020000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; - clock-names = "ref", "pclk"; - interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c3: i2c@4030000 { - compatible = "snps,designware-i2c"; - reg = <0x04030000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; - clock-names = "ref", "pclk"; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c4: i2c@4040000 { - compatible = "snps,designware-i2c"; - reg = <0x04040000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; - clock-names = "ref", "pclk"; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart0: serial@4140000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04140000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@4150000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04150000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@4160000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04160000 0x100>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@4170000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04170000 0x100>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - spi0: spi@4180000 { - compatible = "snps,dw-apb-ssi"; - reg = <0x04180000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; - clock-names = "ssi_clk", "pclk"; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - spi1: spi@4190000 { - compatible = "snps,dw-apb-ssi"; - reg = <0x04190000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; - clock-names = "ssi_clk", "pclk"; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - spi2: spi@41a0000 { - compatible = "snps,dw-apb-ssi"; - reg = <0x041a0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; - clock-names = "ssi_clk", "pclk"; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - spi3: spi@41b0000 { - compatible = "snps,dw-apb-ssi"; - reg = <0x041b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; - clock-names = "ssi_clk", "pclk"; - interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart4: serial@41c0000 { - compatible = "snps,dw-apb-uart"; - reg = <0x041c0000 0x100>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - sdhci0: mmc@4310000 { - compatible = "sophgo,cv1800b-dwcmshc"; - reg = <0x4310000 0x1000>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_AXI4_SD0>, - <&clk CLK_SD0>; - clock-names = "core", "bus"; - status = "disabled"; - }; - - sdhci1: mmc@4320000 { - compatible = "sophgo,cv1800b-dwcmshc"; - reg = <0x4320000 0x1000>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_AXI4_SD1>, - <&clk CLK_SD1>; - clock-names = "core", "bus"; - status = "disabled"; - }; - - dmac: dma-controller@4330000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x04330000 0x1000>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <8>; - snps,block-size = <1024 1024 1024 1024 - 1024 1024 1024 1024>; - snps,priority = <0 1 2 3 4 5 6 7>; - snps,dma-masters = <2>; - snps,data-width = <4>; - status = "disabled"; - }; - plic: interrupt-controller@70000000 { reg = <0x70000000 0x4000000>; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbf2ed900sm10386544f8f.53.2025.02.09.14.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 14:07:06 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree Date: Sun, 9 Feb 2025 23:06:28 +0100 Message-ID: <20250209220646.1090868-4-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). Signed-off-by: Alexander Sverdlin --- arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi new file mode 100644 index 000000000000..4e520486cbe5 --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sophgo,sg2000"; + interrupt-parent = <&gic>; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512MiB */ + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + i-cache-size = <32768>; + d-cache-size = <32768>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-level= <2>; + cache-size = <0x20000>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + always-on; + clock-frequency = <25000000>; + }; + + gic: interrupt-controller@1f01000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f01000 0x1000>, + <0x01f02000 0x2000>; + }; + + soc { + ranges; + + pinctrl: pinctrl@3001000 { + compatible = "sophgo,sg2000-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + }; +}; + + +&clk { + compatible = "sophgo,sg2000-clk"; +}; From patchwork Sun Feb 9 22:06:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Sverdlin X-Patchwork-Id: 13967120 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 267AE22256F for ; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbf2ed900sm10386544f8f.53.2025.02.09.14.07.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 14:07:07 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 04/10] arm64: dts: sophgo: Add Duo Module 01 Date: Sun, 9 Feb 2025 23:06:29 +0100 Message-ID: <20250209220646.1090868-5-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Duo Module 01 is a compact module with integrated SG2000, WI-FI6/BTDM5.4, and eMMC. Add only support for UART and SDHCI. Signed-off-by: Alexander Sverdlin --- .../sophgo/sg2000_milkv_duo_module_01.dtsi | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi diff --git a/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi new file mode 100644 index 000000000000..7edcc4d03cc4 --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include +#include "sg2000.dtsi" + +/ { + model = "Milk-V Duo Module 01"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&emmc { + /delete-property/ status; + bus-width = <4>; + no-1-8-v; + cap-mmc-hw-reset; + no-sd; + no-sdio; + non-removable; +}; + +/* Wi-Fi */ +&sdhci1 { + bus-width = <4>; + cap-sdio-irq; + no-mmc; + no-sd; + non-removable; +}; + +&pinctrl { + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; + + sdhci0_cfg: sdhci0-cfg { + sdhci0-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <16100>; + power-source = <3300>; + }; + + sdhci0-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; +}; From patchwork Sun Feb 9 22:06:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Sverdlin X-Patchwork-Id: 13967121 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0421D220693 for ; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbf2ed900sm10386544f8f.53.2025.02.09.14.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 14:07:08 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 05/10] arm64: dts: sophgo: Add Duo Module 01 Evaluation Board Date: Sun, 9 Feb 2025 23:06:30 +0100 Message-ID: <20250209220646.1090868-6-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Duo Module 01 Evaluation Board contains Sophgo Duo Module 01 SMD SoM, Ethernet+USB switch, microSD slot, etc... Add only support for UART0 (console) and microSD slot. Signed-off-by: Alexander Sverdlin --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/sophgo/Makefile | 2 ++ .../sophgo/sg2000_milkv_duo_module_01_evb.dts | 30 +++++++++++++++++++ 3 files changed, 33 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/Makefile create mode 100644 arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..3a32b157ac8c 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -28,6 +28,7 @@ subdir-y += realtek subdir-y += renesas subdir-y += rockchip subdir-y += socionext +subdir-y += sophgo subdir-y += sprd subdir-y += st subdir-y += synaptics diff --git a/arch/arm64/boot/dts/sophgo/Makefile b/arch/arm64/boot/dts/sophgo/Makefile new file mode 100644 index 000000000000..fcabaf0babf4 --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) += sg2000_milkv_duo_module_01_evb.dtb diff --git a/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts new file mode 100644 index 000000000000..f3533892453d --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000_milkv_duo_module_01_evb.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "sg2000_milkv_duo_module_01.dtsi" + +/ { + model = "Milk-V Duo Module 01 Evaluation Board"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdhci0 { + /delete-property/ status; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; + disable-wp; + pinctrl-0 = <&sdhci0_cfg>; + pinctrl-names = "default"; +}; + +&uart0 { + /delete-property/ status; + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; +}; From patchwork Sun Feb 9 22:06:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Sverdlin X-Patchwork-Id: 13967122 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC5171E231A for ; Sun, 9 Feb 2025 22:07:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbf2ed900sm10386544f8f.53.2025.02.09.14.07.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 14:07:09 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Chen Wang , Inochi Amaoto , linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Sebastian Reichel , Arnd Bergmann , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones Subject: [PATCH 06/10] dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl compatible Date: Sun, 9 Feb 2025 23:06:31 +0100 Message-ID: <20250209220646.1090868-7-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 These syscon blocks will be used for CV18xx reset driver. Signed-off-by: Alexander Sverdlin --- Documentation/devicetree/bindings/mfd/syscon.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 4d67ff26d445..5a0b102d1bd9 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -108,6 +108,8 @@ select: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,cv1800-rtcsys-core + - sophgo,cv1800-rtcsys-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain @@ -207,6 +209,8 @@ properties: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,cv1800-rtcsys-core + - sophgo,cv1800-rtcsys-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain From patchwork Sun Feb 9 22:06:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Sverdlin X-Patchwork-Id: 13967123 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 106F122F17D for ; Sun, 9 Feb 2025 22:07:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739138834; cv=none; b=HQ37FHruolMdfkR3qV8JHpO9w2Kjl8o9UAwzieUC7W6zJZ2K5hsh7r/Zk0DUKQtK5cYQsUxRrdmPApFsF5kORXi4brVp0nEwGMWPeGHOoFWNhvlNKjq7P66JtRsXURPwUeXTIm4mC8ZeNRVe9VvvyHXcIebD8N23kwSqe5KumXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739138834; c=relaxed/simple; bh=7ZAGvUrrjx83yvWVf8ubIKKZh58Hvm4b115PNTRbOXQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=edLgR/Nhl16cYXcR1e8RXpokCKQSL7KB9EPDNdyJ+5oYceCE316cBQgZl2mSfFsHV8giycIlk72sk/lFb5T3Hi5uI6hOiT1aQnIBgQCjFtU2fyLAvwjC6p4y1qNpgC0N4Htm3Ka7MvpRH8DWpzDZuPteA0eE2NE8wi+En9bpBVQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MQzZdpJ9; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MQzZdpJ9" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-439307d83f0so7329335e9.3 for ; Sun, 09 Feb 2025 14:07:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1739138831; x=1739743631; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dVSwUzYyCuH/0EmC09Tuh6m4O6FbPIf1eRFL1KmeQ8U=; b=MQzZdpJ9ty9q7WzI+RKB5mMuNlBJVCDLK5xoUNJ4HD41tPvMqLNmsKRISIE7O6J0y1 bIBVmlNGBB0EHvKwi9y0PAr0pqFDRJV5jQmGoILXAjsQ8VOBTL/Gy+7RXF4jbScTYcVh +oz1dFjgsvnZythMUy8kwW0OXmNZnxvl4iBl5snI/5Y+6Dj2dwZQjnjeVeuE+c/g9G2y 2Z4JbDbGUHtPALK//ZeMricLpbjQdkUbdPjvHcHimVHTFjdEr2vOG7lfQ7c4nHGndJEV xngTqjsGAk+IrmVtPULTqzUdKMAq/KdlWURzyne9i67BXmzd/jo9Fet2u4ZYNcvmy3ig evhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739138831; x=1739743631; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dVSwUzYyCuH/0EmC09Tuh6m4O6FbPIf1eRFL1KmeQ8U=; b=g3E5PkKJ7SZkIoCojXOmWfeMo/QP2Tgi0Nvqz6kNDLxO8Fy6NOOQ58gnCSLOhjaA1Q oZQP0c+P7DA60FlEzsmCNYnNn2gWdU0ckfdGvRpu6RAwTVF5pw2z3IyA3nHvJgcVXMQ7 hLnwZVwWh6yIghgLg44DFxPq3VUkounsLuPRZ1koGVJ2cz7c/8ocC5b6VsckazKYx/7d WKYvVHl2IYcYIADrGUZNKgp9Y7kvjjPdEYYky8trjgIr6wLO/2PTWMLfC9WqA3EzZD7B G9vE70NSKBLvyVMTctAAXEIMwl4AOow+O5U+KxmHqad/FzKHIaXKOjy+vc7ZHwKWkDag gnCA== X-Gm-Message-State: AOJu0Yx5IEupni1/LfVOe5C913c7BmZxFT6/qy8V/+lLTUJIqflf6mEY vbi+dPjtIuQKAF7bxQSe0oV7PY09ey2QihutOxkFzSA4uRO9QtEoFvEekSWM X-Gm-Gg: ASbGnctFRfBcqDL++ULmadkibd5VJEKdLAAITl5b6519YDj0vruh2Myy64LkqMO+cvx xyqgxLZJl5R+HBxeIAB0PFImS/eDiWdcdFEUk/GvDAiGpzRdCt7xJbfCtbCYA0vIf9/QiqkuFVK 2QIEg1yrDI8hevYrFsN+YNqWnpmwYYxNNN9wpX9PohK6cGnK0v0/j7jO8giZgl38s9Wdw2AtYtI ucv5a7dOKGdYR7OFG1whyXJ7i3+yZwH+WLqryBxhZKjohvkXMigdTpt8UzWqhJFycSGB4lSdpdp cZr8BNIgyRdfD1u/U3Ep7gTwKhmK X-Google-Smtp-Source: AGHT+IH5vVna5qsuNt4fQZwckiVpOEaiuCCrF2lXcmMmNlYOm+Z+9AtnNGM3IMnM6VxBlfyTkVsF/Q== X-Received: by 2002:a05:600c:8705:b0:439:41dd:c061 with SMTP id 5b1f17b1804b1-43941ddc2a4mr22063795e9.31.1739138831167; Sun, 09 Feb 2025 14:07:11 -0800 (PST) Received: from giga-mm.. ([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbf2ed900sm10386544f8f.53.2025.02.09.14.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 14:07:10 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Chen Wang , Inochi Amaoto , linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Sebastian Reichel , Arnd Bergmann , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones Subject: [PATCH 07/10] dt-bindings: reset: sophgo: Add CV18xx reset controller Date: Sun, 9 Feb 2025 23:06:32 +0100 Message-ID: <20250209220646.1090868-8-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add DT bindings for CV18xx reset controller. The power/reboot driver is going to use only 4 bits from two different MMIO regions which can be potentially used by other subsystems/drivers, therefore the resources are not being claimed directly by the device/driver, but via syscons instead. Link: https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf Signed-off-by: Alexander Sverdlin --- .../bindings/reset/sophgo,cv1800-reset.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml new file mode 100644 index 000000000000..4f058f99df5f --- /dev/null +++ b/Documentation/devicetree/bindings/reset/sophgo,cv1800-reset.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/sophgo,cv1800-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cvitek CV18xx/Sophgo SG2000 Reset Controller + +maintainers: + - Alexander Sverdlin + +properties: + compatible: + const: sophgo,cv1800-reset + + sophgo,rtcsys-ctrl: + description: phandle of the "RTCSYS_CTRL" syscon block + $ref: /schemas/types.yaml#/definitions/phandle + + sophgo,rtcsys-core: + description: phandle of the "RTCSYS_CORE" syscon block + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - sophgo,rtcsys-ctrl + - sophgo,rtcsys-core + +additionalProperties: false + +examples: + - | + soc-reset { + compatible = "sophgo,cv1800-reset"; + sophgo,rtcsys-ctrl = <&rtcsys_ctrl>; + sophgo,rtcsys-core = <&rtcsys_core>; + }; +... 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Signed-off-by: Alexander Sverdlin --- arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi index 53834b0658b2..d793b6db4ed1 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 { snps,data-width = <4>; status = "disabled"; }; + + rtcsys_ctrl: syscon@5025000 { + compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon"; + reg = <0x05025000 0x1000>; + }; + + rtcsys_core: syscon@5026000 { + compatible = "sophgo,cv1800-rtcsys-core", "syscon"; + reg = <0x05026000 0x1000>; + }; + + soc-reset { + compatible = "sophgo,cv1800-reset"; + sophgo,rtcsys-ctrl = <&rtcsys_ctrl>; + sophgo,rtcsys-core = <&rtcsys_core>; + }; }; }; From patchwork Sun Feb 9 22:06:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Sverdlin X-Patchwork-Id: 13967125 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2BF8215046 for ; Sun, 9 Feb 2025 22:07:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739138836; cv=none; b=Jsyn9WvhtvDPpwxBpZcrXOjzJKqyHXEAyxykMUjRG5YUMNcOJ9E4mXoZ2Xfx2ONUwR+iSs+MeNAumQ202s8KSO74ilB+wKDnN91+IgW91X0mvYdGIhnxFErBUktHh+jSrznxAN0gUOGTCUb1eG6QAHvnLUdk/5QBqC9DNs3ZwYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739138836; c=relaxed/simple; bh=uroPKKaN+hm8ZOaXXgQ6wTDHWe3x+0gyAjigUkvchR4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LS7BWsqbuA8vYrOmO1smmFKq7Fcxp5PQOhOk2lt7G0lWEXxM0lzABtZwsRsaylgMkzDyVujRaYhjDaoBi6zJzPqTS6qHu1zoAp5fALuwMgsCTMftg5FnBFF66VPi/QtLeVSmDRcpXGBiHLIafbQHQGVEv5l2l8AuNvxXu59hw68= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RRa9VYnV; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RRa9VYnV" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-38dd14c99c3so851642f8f.3 for ; Sun, 09 Feb 2025 14:07:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1739138833; x=1739743633; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=369dAJGZKeB0JOjSvrMu1FUQdCgqdozrza7riiyrYK0=; b=RRa9VYnVsu+o3mQ1nCEkKNnRs3uxIl7eI9OQK/MKfCW53hpqpL1hYNz1ahne/klQA7 UF8pNPt+6N72aZWqCT5UWMUA+f45PRINZPb/Ye6OBHnTjszrfMMGwxok+VMthvQ9yNPT oWF+kBx0134anSFSshkHndLlFoK7rOdPRhP/4jMVQoscclIc7Wlj6M6IMQvwdjExysqD rscmEPvoDus4hL1N6nx99OUwPacFluDyR6vq7CwHsHc916hDzbWvRn94A3kLRLTzaguo yGxXWFSOxE+3zPf+ddJ7NU80UjLoWf6BXiHv/uoEC9EK6rscFJE8MAIritTnxw6jsQIm FXuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739138833; x=1739743633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=369dAJGZKeB0JOjSvrMu1FUQdCgqdozrza7riiyrYK0=; b=AlKU2ZHG286PTOozUDXfzFdemu39C9JwkcoouNMeRenVcmC+kZsQhc9u6RefX5Cp0h eEdmhFI5oG7l5GErYdac3Am7Tu6poq1tfNg79Nev+2rlNktbW1HYQOt+h+arFPCq5bkF I3v3JYIXEAboxxuR9DqcEvNyG/N637BOJPLOt/08hqFHZW97yPKP03ID+a3Tv7SGlypA TIXGTBz8KdhPR0UKi3ElNZXRU+xUp9M2SEnsbGdaXo+jDWlGB6Jvyy5UVwtjKxwHTxhn 7jnb+44/ezLFxEwHkz6GV4qyKRJYGCpBh0yzvb8cS3xaVhdtNf0EvDF0pxoQy0AqCaYj CwJw== X-Gm-Message-State: AOJu0YwIDjbiIrS2onkkeBp/Kke1cH8pkOlqbJFbD3BYDPhm5ABwmrca RkMakYILNr5dhEZWaeRqL6ACBRILFjDJwKu0vqbK5Z+CzVnBHMe+jX0GtX13 X-Gm-Gg: ASbGncvUCmkjPYjVz3m5oCO6vA28Z1UAJ35XJ3NSWor3GQbJbPgUZ+7l+xPbxQcOY0g b1KdNhTDZjyDtXvbxMR/az8HJCEW9e06FXP4JZI6R9glJWZIR/rU+lv0i95sJD6ShYanvdaFmAR U+sZRcNxKe+dLDaq9f2/gGGHTuBbJseKV4/23/afaNVHQ4XQZ8Zm1j6EbdMMZ3hGt2/fJWxIBHx TdXPgxja1qpvK5gPnWFmHAEtUiqRCilFIyVn86djuBblmS8DuAGlgbN1FhAW8oDU29t03l4EeNc G5WE9wSNjnS9k3+sYy2BPo/n6ocD X-Google-Smtp-Source: AGHT+IGQNeDm9SkXrpQUSzcKpyxZS28meHGL8UbkTV9jZIpjqhrqbWvmN7mXz5mtgw2H/4aI14AXXQ== X-Received: by 2002:a05:6000:4028:b0:38d:d767:364 with SMTP id ffacd0b85a97d-38dd7670e6fmr3783272f8f.13.1739138833224; Sun, 09 Feb 2025 14:07:13 -0800 (PST) Received: from giga-mm.. ([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbf2ed900sm10386544f8f.53.2025.02.09.14.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 14:07:12 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Chen Wang , Inochi Amaoto , linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Sebastian Reichel , Arnd Bergmann , Philipp Zabel , Lee Jones Subject: [PATCH 09/10] power: reset: cv18xx: New driver Date: Sun, 9 Feb 2025 23:06:34 +0100 Message-ID: <20250209220646.1090868-10-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add new driver to support cold and warm reset on Cvitek CV18xx and Sophgo SG2000 SoCs. Link: https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf Signed-off-by: Alexander Sverdlin --- MAINTAINERS | 1 + drivers/power/reset/Kconfig | 12 ++++ drivers/power/reset/Makefile | 1 + drivers/power/reset/cv18xx-reset.c | 89 ++++++++++++++++++++++++++++++ 4 files changed, 103 insertions(+) create mode 100644 drivers/power/reset/cv18xx-reset.c diff --git a/MAINTAINERS b/MAINTAINERS index e4f5d8f68581..b7fec02f7673 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22147,6 +22147,7 @@ M: Chen Wang M: Inochi Amaoto T: git https://github.com/sophgo/linux.git S: Maintained +F: drivers/power/reset/cv18xx-reset.c N: sophgo K: sophgo diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 60bf0ca64cf3..d41ed3c2a30d 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -75,6 +75,18 @@ config POWER_RESET_BRCMSTB Say Y here if you have a Broadcom STB board and you wish to have restart support. +config POWER_RESET_CV18XX + bool "Cvitek CV18XX/Sophgo SG2000 reset driver" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on MFD_SYSCON + default ARCH_SOPHGO + help + This driver provides restart support for Cvitek CV18xx and + Sophgo SG2000 SoCs. + + Say Y here if you have a Cvitek CV18xx or Sophgo SG2000 SoC and + you wish to have restart support. + config POWER_RESET_EP93XX bool "Cirrus EP93XX reset driver" if COMPILE_TEST depends on MFD_SYSCON diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index 10782d32e1da..ce24e74e0477 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_POWER_RESET_ATC260X) += atc260x-poweroff.o obj-$(CONFIG_POWER_RESET_AXXIA) += axxia-reset.o obj-$(CONFIG_POWER_RESET_BRCMKONA) += brcm-kona-reset.o obj-$(CONFIG_POWER_RESET_BRCMSTB) += brcmstb-reboot.o +obj-$(CONFIG_POWER_RESET_CV18XX) += cv18xx-reset.o obj-$(CONFIG_POWER_RESET_EP93XX) += ep93xx-restart.o obj-$(CONFIG_POWER_RESET_GEMINI_POWEROFF) += gemini-poweroff.o obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o diff --git a/drivers/power/reset/cv18xx-reset.c b/drivers/power/reset/cv18xx-reset.c new file mode 100644 index 000000000000..bc1797e7d3f5 --- /dev/null +++ b/drivers/power/reset/cv18xx-reset.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include + +/* RTCSYS_CTRL registers */ +#define RTC_CTRL_UNLOCKKEY 0x04 +#define RTC_CTRL0 0x08 +#define REQ_PWR_CYC BIT(3) +#define REQ_WARM_RST BIT(4) + +/* RTCSYS_CORE registers */ +#define RTC_EN_PWR_CYC_REQ 0xC8 +#define RTC_EN_WARM_RST_REQ 0xCC + +static struct regmap *rtcsys_ctrl_regs; +static struct regmap *rtcsys_core_regs; + +static int cv18xx_restart_handler(struct sys_off_data *data) +{ + u32 reg_en = RTC_EN_WARM_RST_REQ; + u32 request = 0xFFFF0800; + + if (data->mode == REBOOT_COLD) { + reg_en = RTC_EN_PWR_CYC_REQ; + request |= REQ_PWR_CYC; + } else { + request |= REQ_WARM_RST; + } + + /* Enable reset request */ + regmap_write(rtcsys_core_regs, reg_en, 1); + /* Enable CTRL0 register access */ + regmap_write(rtcsys_ctrl_regs, RTC_CTRL_UNLOCKKEY, 0xAB18); + /* Request reset */ + regmap_write(rtcsys_ctrl_regs, RTC_CTRL0, request); + + return NOTIFY_DONE; +} + +static int cv18xx_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + int ret; + + if (!np) + return -ENODEV; + + rtcsys_ctrl_regs = syscon_regmap_lookup_by_phandle(np, "sophgo,rtcsys-ctrl"); + if (IS_ERR(rtcsys_ctrl_regs)) + return dev_err_probe(dev, PTR_ERR(rtcsys_ctrl_regs), + "sophgo,rtcsys-ctrl lookup failed\n"); + + rtcsys_core_regs = syscon_regmap_lookup_by_phandle(np, "sophgo,rtcsys-core"); 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbf2ed900sm10386544f8f.53.2025.02.09.14.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 14:07:13 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Catalin Marinas , Will Deacon Subject: [PATCH 10/10] arm64: defconfig: Enable rudimentary Sophgo SG2000 support Date: Sun, 9 Feb 2025 23:06:35 +0100 Message-ID: <20250209220646.1090868-11-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable ARCH_SOPHGO, pinctrl (built-in, required to boot), ADC as module. This defconfig is able to boot from SD card on Milk-V Duo Module 01 EVB. Signed-off-by: Alexander Sverdlin --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index cb7da4415599..56e2c833f745 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -66,6 +66,7 @@ CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_INTEL_SOCFPGA=y +CONFIG_ARCH_SOPHGO=y CONFIG_ARCH_STM32=y CONFIG_ARCH_SYNQUACER=y CONFIG_ARCH_TEGRA=y @@ -650,6 +651,7 @@ CONFIG_PINCTRL_SM8450_LPASS_LPI=m CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m CONFIG_PINCTRL_SM8550_LPASS_LPI=m CONFIG_PINCTRL_SM8650_LPASS_LPI=m +CONFIG_PINCTRL_SOPHGO_SG2000=y CONFIG_GPIO_ALTERA=m CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y @@ -1517,6 +1519,7 @@ CONFIG_QCOM_SPMI_VADC=m CONFIG_QCOM_SPMI_ADC5=m CONFIG_ROCKCHIP_SARADC=m CONFIG_RZG2L_ADC=m +CONFIG_SOPHGO_CV1800B_ADC=m CONFIG_TI_ADS1015=m CONFIG_TI_AM335X_ADC=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m