From patchwork Tue Feb 11 02:52:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunny Shen X-Patchwork-Id: 13969830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C44EC0219E for ; Tue, 11 Feb 2025 07:56:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0602810E42F; Tue, 11 Feb 2025 07:56:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="scj4I0q8"; dkim-atps=neutral Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id EDAD510E1FF for ; Tue, 11 Feb 2025 02:53:30 +0000 (UTC) X-UUID: 5ddedaf0e82311efb8f9918b5fc74e19-20250211 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=uIyrTTeXw+C4BCHVXGUIGZGr+s1+Cv96AxvzOxDoOWg=; b=scj4I0q8ajkCM7GKjoRHQ9Rs8dsZ9LaLxwOtorLzzev38j5rb7Cy1/yaclSd+mUWpW8KIrfP8avf8EGy6zKtIWMPfdE1KPTmdLNI8gSVx7ykNocHywePp+QwaGS+JMoCK0fqosiRuy0jlGjP5wcnSJu0glYjBCesVXZLCGLhkzg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46, REQID:b457304c-cdf0-475d-8d30-df13efc26819, IP:0, U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:60aa074, CLOUDID:ffc9627f-427a-4311-9df4-bfaeeacd8532, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 ,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 5ddedaf0e82311efb8f9918b5fc74e19-20250211 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 963153032; Tue, 11 Feb 2025 10:53:26 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 11 Feb 2025 10:53:25 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 11 Feb 2025 10:53:25 +0800 From: Sunny Shen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Matthias Brugger , Philipp Zabel , Fei Shao , Pin-yen Lin , "Jason-JH . Lin" , Nancy Lin , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196 Date: Tue, 11 Feb 2025 10:52:50 +0800 Message-ID: <20250211025317.399534-2-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250211025317.399534-1-sunny.shen@mediatek.com> References: <20250211025317.399534-1-sunny.shen@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 11 Feb 2025 07:56:48 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add MDP-RSZ hardware description for MediaTek MT8196 SoC Signed-off-by: Sunny Shen --- .../display/mediatek/mediatek,mdp-rsz.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml new file mode 100644 index 000000000000..6642b9aa651a --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rsz.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display multimedia data path resizer + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: | + MediaTek display multimedia data path resizer, namely MDP-RSZ, + can do scaling up/down to the picture. + +properties: + compatible: + const: mediatek,mt8196-disp-mdp-rsz + + reg: + maxItems: 1 + + clocks: + items: + - description: MDP-RSZ Clock + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + disp_mdp_rsz0: disp-mdp-rsz0@321a0000 { + compatible = "mediatek,mt8196-disp-mdp-rsz"; + reg = <0 0x321a0000 0 0x1000>; + clocks = <&dispsys_config_clk 101>; + }; + }; From patchwork Tue Feb 11 02:52:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunny Shen X-Patchwork-Id: 13969832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 059D3C021A2 for ; Tue, 11 Feb 2025 07:56:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 83FAA10E425; Tue, 11 Feb 2025 07:56:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; 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Tue, 11 Feb 2025 10:53:31 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 11 Feb 2025 10:53:30 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 11 Feb 2025 10:53:29 +0800 From: Sunny Shen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Matthias Brugger , Philipp Zabel , Fei Shao , Pin-yen Lin , "Jason-JH . Lin" , Nancy Lin , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH 2/5] dt-bindings: display: mediatek: postmask: Modify rules for MT8196 Date: Tue, 11 Feb 2025 10:52:51 +0800 Message-ID: <20250211025317.399534-3-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250211025317.399534-1-sunny.shen@mediatek.com> References: <20250211025317.399534-1-sunny.shen@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 11 Feb 2025 07:56:48 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a compatible string for MediaTek MT8196 SoC Signed-off-by: Sunny Shen --- .../devicetree/bindings/display/mediatek/mediatek,postmask.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml index fb6fe4742624..29624ac191e1 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml @@ -27,6 +27,7 @@ properties: - enum: - mediatek,mt8186-disp-postmask - mediatek,mt8188-disp-postmask + - mediatek,mt8196-disp-postmask - const: mediatek,mt8192-disp-postmask reg: From patchwork Tue Feb 11 02:52:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunny Shen X-Patchwork-Id: 13969836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5357EC021A5 for ; Tue, 11 Feb 2025 07:56:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0BC9E10E431; Tue, 11 Feb 2025 07:56:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="gN6vjS8c"; dkim-atps=neutral Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 020EF10E1FF for ; Tue, 11 Feb 2025 02:53:37 +0000 (UTC) X-UUID: 614af8d6e82311efb8f9918b5fc74e19-20250211 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=huymk/dQpvaH56qoB1f+DVpPSCDfCCnhC4pMTyNd65I=; b=gN6vjS8c4gjC3ucBxjsLjokloCGdTedyECr8uzu/q7ZsuQ3fDPwQVrq2Fa2AVyOFeLVRCFIEPcD4/T39IfId4rTnTawu4iC4Brry43Yy7Yrnw5SvqF2N5Z555mdW9fyzr42StsUElUDHhMBQ++xlPT09tLq0ht0V0Nhb2I3/Taw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46, REQID:a42345fe-7830-4ded-bbe0-24f4f14b685d, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:60aa074, CLOUDID:62ca627f-427a-4311-9df4-bfaeeacd8532, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 614af8d6e82311efb8f9918b5fc74e19-20250211 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 441736300; Tue, 11 Feb 2025 10:53:32 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 11 Feb 2025 10:53:31 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 11 Feb 2025 10:53:31 +0800 From: Sunny Shen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Matthias Brugger , Philipp Zabel , Fei Shao , Pin-yen Lin , "Jason-JH . Lin" , Nancy Lin , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH 3/5] soc: mediatek: Add components to support PQ in display path for MT8196 Date: Tue, 11 Feb 2025 10:52:52 +0800 Message-ID: <20250211025317.399534-4-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250211025317.399534-1-sunny.shen@mediatek.com> References: <20250211025317.399534-1-sunny.shen@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 11 Feb 2025 07:56:48 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Due to the path mux design of the MT8196, the following components need to be configured into mutex and mmsys to support Picture Quality (PQ) in the display path:CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0. Signed-off-by: Sunny Shen --- drivers/soc/mediatek/mt8196-mmsys.h | 70 +++++++++++++++++++++++++- drivers/soc/mediatek/mtk-mutex.c | 17 +++++++ include/linux/soc/mediatek/mtk-mmsys.h | 5 ++ 3 files changed, 90 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mt8196-mmsys.h b/drivers/soc/mediatek/mt8196-mmsys.h index 03d1210d2b80..b686d5029219 100644 --- a/drivers/soc/mediatek/mt8196-mmsys.h +++ b/drivers/soc/mediatek/mt8196-mmsys.h @@ -68,6 +68,22 @@ #define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY7 BIT(2) /* DISPSYS0 */ +#define MT8196_DISP_CCORR0_SEL 0xd28 +#define MT8196_DISP_CCORR0_FROM_TDSHP0 BIT(1) +#define MT8196_DISP_CCORR0_SOUT 0xd2c +#define MT8196_DISP_CCORR0_TO_CCORR1 BIT(0) +#define MT8196_DISP_CCORR1_SEL 0xd30 +#define MT8196_DISP_CCORR1_FROM_CCORR0 BIT(0) +#define MT8196_DISP_CCORR1_SOUT 0xd34 +#define MT8196_DISP_CCORR1_TO_GAMMA0 BIT(0) +#define MT8196_DISP_GAMMA0_SEL 0xd58 +#define MT8196_DISP_GAMMA0_FROM_CCORR1 BIT(0) +#define MT8196_DISP_POSTMASK0_SOUT 0xd68 +#define MT8196_DISP_POSTMASK0_TO_DITHER0 0x0 +#define MT8196_DISP_TDSHP0_SOUT 0xd70 +#define MT8196_DISP_TDSHP0_TO_CCORR0 BIT(1) +#define MT8196_MDP_RSZ0_MOUT_EN 0xd78 +#define MT8196_MDP_RSZ0_TO_TDSHP0 BIT(0) #define MT8196_PANEL_COMP_OUT_CB1_MOUT_EN 0xd84 #define MT8196_DISP_TO_DLO_RELAY1 BIT(1) #define MT8196_PANEL_COMP_OUT_CB2_MOUT_EN 0xd88 @@ -75,12 +91,14 @@ #define MT8196_PANEL_COMP_OUT_CB3_MOUT_EN 0xd8c #define MT8196_DISP_TO_DLO_RELAY3 BIT(3) #define MT8196_PQ_IN_CB0_MOUT_EN 0xdd0 +#define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0 BIT(0) #define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6 BIT(2) - #define MT8196_PQ_IN_CB1_MOUT_EN 0xdd4 #define MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7 BIT(3) #define MT8196_PQ_IN_CB8_MOUT_EN 0xdf0 #define MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8 BIT(4) +#define MT8196_PQ_OUT_CB0_MOUT_EN 0xe3c +#define MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1 BIT(1) #define MT8196_PQ_OUT_CB6_MOUT_EN 0xe54 #define MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1 BIT(1) #define MT8196_PQ_OUT_CB7_MOUT_EN 0xe58 @@ -314,11 +332,13 @@ static const struct mtk_mmsys_routes mmsys_mt8196_ovl1_routing_table[] = { }; /* - * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ_OUT_CB6 -> PANEL_COMP_OUT_CB1 -> DLO_ASYNC1 + * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ (MDP_RSZ0/TDSHP0/CCORR0/CCORR1/GAMMA0/POSTMASK0/DITHER0) + * -> PQ_OUT_CB0 -> PANEL_COMP_OUT_CB1 -> DLO_ASYNC1 * ext: DLI_ASYNC1-> PQ_IN_CB1 -> PQ_OUT_CB7 -> PANEL_COMP_OUT_CB2 -> DLO_ASYNC2 */ static const struct mtk_mmsys_routes mmsys_mt8196_disp0_routing_table[] = { { + /* main: PQ bypass */ DDP_COMPONENT_DLI_ASYNC0, DDP_COMPONENT_DLO_ASYNC1, MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6 @@ -331,6 +351,52 @@ static const struct mtk_mmsys_routes mmsys_mt8196_disp0_routing_table[] = { MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1, MT8196_DISP_TO_DLO_RELAY1 }, { + /* main: PQ path */ + DDP_COMPONENT_DLI_ASYNC0, DDP_COMPONENT_MDP_RSZ0, + MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0, + MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0 + }, { + DDP_COMPONENT_MDP_RSZ0, DDP_COMPONENT_TDSHP0, + MT8196_MDP_RSZ0_MOUT_EN, MT8196_MDP_RSZ0_TO_TDSHP0, + MT8196_MDP_RSZ0_TO_TDSHP0 + }, { + DDP_COMPONENT_TDSHP0, DDP_COMPONENT_CCORR0, + MT8196_DISP_TDSHP0_SOUT, MT8196_DISP_TDSHP0_TO_CCORR0, + MT8196_DISP_TDSHP0_TO_CCORR0 + }, { + DDP_COMPONENT_TDSHP0, DDP_COMPONENT_CCORR0, + MT8196_DISP_CCORR0_SEL, MT8196_DISP_CCORR0_FROM_TDSHP0, + MT8196_DISP_CCORR0_FROM_TDSHP0 + }, { + DDP_COMPONENT_CCORR0, DDP_COMPONENT_CCORR1, + MT8196_DISP_CCORR0_SOUT, MT8196_DISP_CCORR0_TO_CCORR1, + MT8196_DISP_CCORR0_TO_CCORR1 + }, { + DDP_COMPONENT_CCORR0, DDP_COMPONENT_CCORR1, + MT8196_DISP_CCORR1_SEL, MT8196_DISP_CCORR1_FROM_CCORR0, + MT8196_DISP_CCORR1_FROM_CCORR0 + }, { + DDP_COMPONENT_CCORR1, DDP_COMPONENT_GAMMA0, + MT8196_DISP_CCORR1_SOUT, MT8196_DISP_CCORR1_TO_GAMMA0, + MT8196_DISP_CCORR1_TO_GAMMA0 + }, { + DDP_COMPONENT_CCORR1, DDP_COMPONENT_GAMMA0, + MT8196_DISP_GAMMA0_SEL, MT8196_DISP_GAMMA0_FROM_CCORR1, + MT8196_DISP_GAMMA0_FROM_CCORR1 + }, { + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_DITHER0, + MT8196_DISP_POSTMASK0_SOUT, MT8196_DISP_POSTMASK0_TO_DITHER0, + MT8196_DISP_POSTMASK0_TO_DITHER0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1, + MT8196_PQ_OUT_CB0_MOUT_EN, MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1, + MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1, + MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1, + MT8196_DISP_TO_DLO_RELAY1 + }, { + /* ext */ DDP_COMPONENT_DLI_ASYNC1, DDP_COMPONENT_DLO_ASYNC2, MT8196_PQ_IN_CB1_MOUT_EN, MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7, MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7 diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 51db6f2a05ae..9c895566dfb2 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -262,6 +262,11 @@ #define MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6 (32 + 17) /* DISP0 */ + +#define MT8196_MUTEX_MOD0_DISP_CCORR0 6 +#define MT8196_MUTEX_MOD0_DISP_CCORR1 7 +#define MT8196_MUTEX_MOD0_DISP_DITHER0 14 + #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC0 16 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC1 17 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC8 24 @@ -269,6 +274,11 @@ #define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC2 (32 + 2) #define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC3 (32 + 3) +#define MT8196_MUTEX_MOD1_DISP_GAMMA0 (32 + 9) +#define MT8196_MUTEX_MOD1_DISP_POSTMASK0 (32 + 14) +#define MT8196_MUTEX_MOD1_DISP_MDP_RSZ0 (32 + 18) +#define MT8196_MUTEX_MOD1_DISP_TDSHP0 (32 + 21) + /* DISP1 */ #define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC21 1 #define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC22 2 @@ -678,6 +688,13 @@ static const u8 mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { }; static const u8 mt8196_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_CCORR0] = MT8196_MUTEX_MOD0_DISP_CCORR0, + [DDP_COMPONENT_CCORR1] = MT8196_MUTEX_MOD0_DISP_CCORR1, + [DDP_COMPONENT_DITHER0] = MT8196_MUTEX_MOD0_DISP_DITHER0, + [DDP_COMPONENT_GAMMA0] = MT8196_MUTEX_MOD1_DISP_GAMMA0, + [DDP_COMPONENT_MDP_RSZ0] = MT8196_MUTEX_MOD1_DISP_MDP_RSZ0, + [DDP_COMPONENT_POSTMASK0] = MT8196_MUTEX_MOD1_DISP_POSTMASK0, + [DDP_COMPONENT_TDSHP0] = MT8196_MUTEX_MOD1_DISP_TDSHP0, [DDP_COMPONENT_OVL0_EXDMA2] = MT8196_MUTEX_MOD0_OVL_EXDMA2, [DDP_COMPONENT_OVL0_EXDMA3] = MT8196_MUTEX_MOD0_OVL_EXDMA3, [DDP_COMPONENT_OVL0_EXDMA4] = MT8196_MUTEX_MOD0_OVL_EXDMA4, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4a0b10567581..250054ca5523 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -25,6 +25,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_AAL1, DDP_COMPONENT_BLS, DDP_COMPONENT_CCORR, + DDP_COMPONENT_CCORR0 = DDP_COMPONENT_CCORR, + DDP_COMPONENT_CCORR1, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER0, @@ -51,6 +53,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DVO0, DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_GAMMA, + DDP_COMPONENT_GAMMA0 = DDP_COMPONENT_GAMMA, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MDP_RDMA2, @@ -59,6 +62,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_MDP_RDMA5, DDP_COMPONENT_MDP_RDMA6, DDP_COMPONENT_MDP_RDMA7, + DDP_COMPONENT_MDP_RSZ0, DDP_COMPONENT_MERGE0, DDP_COMPONENT_MERGE1, DDP_COMPONENT_MERGE2, @@ -130,6 +134,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, DDP_COMPONENT_RDMA4, + DDP_COMPONENT_TDSHP0, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, From patchwork Tue Feb 11 02:52:53 2025 Content-Type: text/plain; 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Tue, 11 Feb 2025 10:53:36 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 11 Feb 2025 10:53:34 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 11 Feb 2025 10:53:34 +0800 From: Sunny Shen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Matthias Brugger , Philipp Zabel , Fei Shao , Pin-yen Lin , "Jason-JH . Lin" , "Nancy Lin" , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH 4/5] drm/mediatek: Add MDP-RSZ component support for MT8196 Date: Tue, 11 Feb 2025 10:52:53 +0800 Message-ID: <20250211025317.399534-5-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250211025317.399534-1-sunny.shen@mediatek.com> References: <20250211025317.399534-1-sunny.shen@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 11 Feb 2025 07:56:48 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add MDP-RSZ component support for MT8196. Signed-off-by: Sunny Shen --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index 7f09a8977965..65878d3fe8a9 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -46,6 +46,10 @@ #define DSC_BYPASS BIT(4) #define DSC_UFOE_SEL BIT(16) +#define DISP_REG_MDP_RSZ_EN 0x0000 +#define DISP_REG_MDP_RSZ_INPUT_SIZE 0x0010 +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE 0x0014 + #define DISP_REG_OD_EN 0x0000 #define DISP_REG_OD_CFG 0x0020 #define OD_RELAYMODE BIT(0) @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev) writel(1, priv->regs + DISP_REG_OD_EN); } +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MDP_RSZ_INPUT_SIZE); + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MDP_RSZ_OUTPUT_SIZE); +} + static void mtk_postmask_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs ddp_ovlsys_adaptor = { .get_num_formats = mtk_ovlsys_adaptor_get_num_formats, }; +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_mdp_rsz_config, +}; + static const struct mtk_ddp_comp_funcs ddp_postmask = { .clk_enable = mtk_ddp_clk_enable, .clk_disable = mtk_ddp_clk_disable, @@ -454,6 +476,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_DITHER] = "dither", [MTK_DISP_DSC] = "dsc", [MTK_DISP_GAMMA] = "gamma", + [MTK_DISP_MDP_RSZ] = "mdp-rsz", [MTK_DISP_MERGE] = "merge", [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, + [DDP_COMPONENT_MDP_RSZ0] = { MTK_DISP_MDP_RSZ, 0, &ddp_mdp_rsz}, [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge }, [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge }, [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge }, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h index badb42bd4f7c..87f573fcc903 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type { MTK_DISP_OVLSYS_ADAPTOR, MTK_DISP_OVL_2L, MTK_DISP_OVL_ADAPTOR, + MTK_DISP_MDP_RSZ, MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_RDMA, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 50f5f81a7da1..b810a197f58b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -885,6 +885,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8195-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8196-disp-mdp-rsz", + .data = (void *)MTK_DISP_MDP_RSZ }, { .compatible = "mediatek,mt8195-disp-merge", .data = (void *)MTK_DISP_MERGE }, { .compatible = "mediatek,mt2701-disp-mutex", From patchwork Tue Feb 11 02:52:54 2025 Content-Type: text/plain; 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Tue, 11 Feb 2025 10:53:37 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 11 Feb 2025 10:53:36 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 11 Feb 2025 10:53:36 +0800 From: Sunny Shen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Matthias Brugger , Philipp Zabel , Fei Shao , Pin-yen Lin , "Jason-JH . Lin" , Nancy Lin , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH 5/5] drm/mediatek: Change main display path to support PQ for MT8196 Date: Tue, 11 Feb 2025 10:52:54 +0800 Message-ID: <20250211025317.399534-6-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250211025317.399534-1-sunny.shen@mediatek.com> References: <20250211025317.399534-1-sunny.shen@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 11 Feb 2025 07:56:48 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Due to the path mux design of the MT8196, the following components need to be added to support Picture Quality (PQ) in the main display path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0. Signed-off-by: Sunny Shen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b810a197f58b..1c97dc46ae70 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = { static const unsigned int mt8196_mtk_ddp_disp0_main[] = { DDP_COMPONENT_DLI_ASYNC0, + DDP_COMPONENT_MDP_RSZ0, + DDP_COMPONENT_TDSHP0, + DDP_COMPONENT_CCORR0, + DDP_COMPONENT_CCORR1, + DDP_COMPONENT_GAMMA0, + DDP_COMPONENT_POSTMASK0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1, };