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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:25:03.4618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1c5fcbf-597e-449d-a43b-08dd4ad1c8ee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5933 CXL.io is implemented on top of PCIe Protocol Errors. But, CXL.io and PCIe have different handling requirements for uncorrectable errors (UCE). The PCIe AER service driver may attempt recovering PCIe devices with UCE while recovery is not used for CXL.io. Recovery is not used in the CXL.io case because of potential corruption on what can be system memory. Create pci_driver::cxl_err_handlers structure similar to pci_driver::error_handler. Create handlers for correctable and uncorrectable CXL.io error handling. The CXL error handlers will be used in future patches adding CXL PCIe Port Protocol Error handling. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Acked-by: Bjorn Helgaas Reviewed-by: Dan Williams --- include/linux/pci.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa..1d62e785ae1f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -884,6 +884,14 @@ struct pci_error_handlers { void (*cor_error_detected)(struct pci_dev *dev); }; +/* Compute Express Link (CXL) bus error event callbacks */ +struct cxl_error_handlers { + /* CXL bus error detected on this device */ + pci_ers_result_t (*error_detected)(struct pci_dev *dev); + + /* Allow device driver to record more details of a correctable error */ + void (*cor_error_detected)(struct pci_dev *dev); +}; struct module; @@ -929,6 +937,7 @@ struct module; * @sriov_get_vf_total_msix: PF driver callback to get the total number of * MSI-X vectors available for distribution to the VFs. * @err_handler: See Documentation/PCI/pci-error-recovery.rst + * @cxl_err_handler: Compute Express Link specific error handlers. * @groups: Sysfs attribute groups. * @dev_groups: Attributes attached to the device that will be * created once it is bound to the driver. @@ -954,6 +963,7 @@ struct pci_driver { int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:25:12.9505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28ea35a8-9423-4edd-2f78-08dd4ad1ce88 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6592 The AER service driver already includes support for Restricted CXL host (RCH) Downstream Port Protocol Error handling. The current implementation is based on CXL1.1 using a Root Complex Event Collector. Rename function interfaces and parameters where necessary to include virtual hierarchy (VH) mode CXL PCIe Port error handling alongside the RCH handling.[1] The CXL PCIe Port Protocol Error handling support will be added in a future patch. Limit changes to renaming variable and function names. No functional changes are added. [1] CXL 3.1 Spec, 9.12.2 CXL Virtual Hierarchy Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Acked-by: Bjorn Helgaas Reviewed-by: Dan Williams --- drivers/pci/pcie/aer.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 508474e17183..6e8de77d0fc4 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1024,7 +1024,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) return 0; } -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) +static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { /* * Internal errors of an RCEC indicate an AER error in an @@ -1047,30 +1047,30 @@ static int handles_cxl_error_iter(struct pci_dev *dev, void *data) return *handles_cxl; } -static bool handles_cxl_errors(struct pci_dev *rcec) +static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl = false; - if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(dev)) + pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); return handles_cxl; } -static void cxl_rch_enable_rcec(struct pci_dev *rcec) +static void cxl_enable_internal_errors(struct pci_dev *dev) { - if (!handles_cxl_errors(rcec)) + if (!handles_cxl_errors(dev)) return; - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); + pci_aer_unmask_internal_errors(dev); + pci_info(dev, "CXL: Internal errors unmasked"); } #else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } +static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } +static inline void cxl_handle_error(struct pci_dev *dev, + struct aer_err_info *info) { } #endif /** @@ -1108,7 +1108,7 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) { - cxl_rch_handle_error(dev, info); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:25:25.4890 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b15b9ae8-f625-4e7f-1836-08dd4ad1d612 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7331 CXL and AER drivers need the ability to identify CXL devices and CXL port devices. First, add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The CXL Flexbus DVSEC presence is used because it is required for all the CXL PCIe devices.[1] Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL Flexbus presence. Add pcie_is_cxl() as a macro to return 'struct pci_dev::is_cxl'. Add pcie_is_cxl_port() to check if a device is a CXL Root Port, CXL Upstream Switch Port, or CXL Downstream Switch Port. Also, verify the CXL Extensions DVSEC for Ports is present.[1] [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment, Table 8-2 Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Acked-by: Bjorn Helgaas Reviewed-by: Dan Williams --- drivers/pci/pci.c | 13 +++++++++++++ drivers/pci/probe.c | 10 ++++++++++ include/linux/pci.h | 5 +++++ include/uapi/linux/pci_regs.h | 3 ++- 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 869d204a70a3..a2d8b41dd043 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5032,6 +5032,19 @@ static u16 cxl_port_dvsec(struct pci_dev *dev) PCI_DVSEC_CXL_PORT); } +inline bool pcie_is_cxl(struct pci_dev *pci_dev) +{ + return pci_dev->is_cxl; +} + +bool pcie_is_cxl_port(struct pci_dev *dev) +{ + if (!pcie_is_cxl(dev)) + return false; + + return (cxl_port_dvsec(dev) > 0); +} + static bool cxl_sbr_masked(struct pci_dev *dev) { u16 dvsec, reg; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index b6536ed599c3..7737b9ce7a83 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1676,6 +1676,14 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) dev->is_thunderbolt = 1; } +static void set_pcie_cxl(struct pci_dev *dev) +{ + u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS); + if (dvsec) + dev->is_cxl = 1; +} + static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent = pci_upstream_bridge(dev); @@ -2006,6 +2014,8 @@ int pci_setup_device(struct pci_dev *dev) /* Need to have dev->cfg_size ready */ set_pcie_thunderbolt(dev); + set_pcie_cxl(dev); + set_pcie_untrusted(dev); if (pci_is_pcie(dev)) diff --git a/include/linux/pci.h b/include/linux/pci.h index 1d62e785ae1f..82a0401c58d3 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -452,6 +452,7 @@ struct pci_dev { unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ + unsigned int is_cxl:1; /* Compute Express Link (CXL) */ /* * Devices marked being untrusted are the ones that can potentially * execute DMA attacks and similar. They are typically connected @@ -741,6 +742,10 @@ static inline bool pci_is_vga(struct pci_dev *pdev) return false; } +bool pcie_is_cxl(struct pci_dev *pci_dev); + +bool pcie_is_cxl_port(struct pci_dev *dev); + #define for_each_pci_bridge(dev, bus) \ list_for_each_entry(dev, &bus->devices, bus_list) \ if (!pci_is_bridge(dev)) {} else diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3445c4970e4d..dbc0f23d8c82 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1208,9 +1208,10 @@ #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ +/* Compute Express Link (CXL r3.1, sec 8.1) */ #define PCI_DVSEC_CXL_PORT 3 #define PCI_DVSEC_CXL_PORT_CTL 0x0c #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 +#define PCI_DVSEC_CXL_FLEXBUS 7 #endif /* LINUX_PCI_REGS_H */ From patchwork Tue Feb 11 19:24:31 2025 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:25:35.7081 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 596efb5e-186a-4a50-081c-08dd4ad1dc27 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6306 The AER driver and aer_event tracing currently log 'PCIe Bus Type' for all errors. Update the driver and aer_event tracing to log 'CXL Bus Type' for CXL device errors. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Acked-by: Bjorn Helgaas Reviewed-by: Dan Williams --- drivers/pci/pcie/aer.c | 14 ++++++++------ include/ras/ras_event.h | 9 ++++++--- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 6e8de77d0fc4..f99a1c6fb274 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -694,13 +694,14 @@ static void __aer_print_error(struct pci_dev *dev, void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) { + const char *bus_type = pcie_is_cxl(dev) ? "CXL" : "PCIe"; int layer, agent; int id = pci_dev_id(dev); const char *level; if (!info->status) { - pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", - aer_error_severity_string[info->severity]); + pci_err(dev, "%s Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", + bus_type, aer_error_severity_string[info->severity]); goto out; } @@ -709,8 +710,8 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR; - pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n", - aer_error_severity_string[info->severity], + pci_printk(level, dev, "%s Bus Error: severity=%s, type=%s, (%s)\n", + bus_type, aer_error_severity_string[info->severity], aer_error_layer[layer], aer_agent_string[agent]); pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", @@ -725,7 +726,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) if (info->id && info->error_dev_num > 1 && info->id == id) pci_err(dev, " Error of this Agent is reported first\n"); - trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), + trace_aer_event(dev_name(&dev->dev), bus_type, (info->status & ~info->mask), info->severity, info->tlp_header_valid, &info->tlp); } @@ -759,6 +760,7 @@ EXPORT_SYMBOL_GPL(cper_severity_to_aer); void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer) { + const char *bus_type = pcie_is_cxl(dev) ? "CXL" : "PCIe"; int layer, agent, tlp_header_valid = 0; u32 status, mask; struct aer_err_info info; @@ -793,7 +795,7 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, if (tlp_header_valid) pcie_print_tlp_log(dev, &aer->header_log, dev_fmt(" ")); - trace_aer_event(dev_name(&dev->dev), (status & ~mask), + trace_aer_event(dev_name(&dev->dev), bus_type, (status & ~mask), aer_severity, tlp_header_valid, &aer->header_log); } EXPORT_SYMBOL_NS_GPL(pci_print_aer, "CXL"); diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index e5f7ee0864e7..1bf8e7050ba8 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -297,15 +297,17 @@ TRACE_EVENT(non_standard_event, TRACE_EVENT(aer_event, TP_PROTO(const char *dev_name, + const char *bus_type, const u32 status, const u8 severity, const u8 tlp_header_valid, struct pcie_tlp_log *tlp), - TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp), + TP_ARGS(dev_name, bus_type, status, severity, tlp_header_valid, tlp), TP_STRUCT__entry( __string( dev_name, dev_name ) + __string( bus_type, bus_type ) __field( u32, status ) __field( u8, severity ) __field( u8, tlp_header_valid) @@ -314,6 +316,7 @@ TRACE_EVENT(aer_event, TP_fast_assign( __assign_str(dev_name); + __assign_str(bus_type); __entry->status = status; __entry->severity = severity; __entry->tlp_header_valid = tlp_header_valid; @@ -325,8 +328,8 @@ TRACE_EVENT(aer_event, } ), - TP_printk("%s PCIe Bus Error: severity=%s, %s, TLP Header=%s\n", - __get_str(dev_name), + TP_printk("%s %s Bus Error: severity=%s, %s, TLP Header=%s\n", + __get_str(dev_name), __get_str(bus_type), __entry->severity == AER_CORRECTABLE ? "Corrected" : __entry->severity == AER_FATAL ? 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:25:46.8078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 043a93d3-b081-4e2b-a178-08dd4ad1e2d0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8841 The AER service driver supports handling Downstream Port Protocol Errors in Restricted CXL host (RCH) mode also known as CXL1.1. It needs the same functionality for CXL PCIe Ports operating in Virtual Hierarchy (VH) mode.[1] CXL and PCIe Protocol Error handling have different requirements that necessitate a separate handling path. The AER service driver may try to recover PCIe uncorrectable non-fatal errors (UCE). The same recovery is not suitable for CXL PCIe Port devices because of potential for system memory corruption. Instead, CXL Protocol Error handling must use a kernel panic in the case of a fatal or non-fatal UCE. The AER driver's PCIe Protocol Error handling does not panic the kernel in response to a UCE. Introduce a separate path for CXL Protocol Error handling in the AER service driver. This will allow CXL Protocol Errors to use CXL specific handling instead of PCIe handling. Add the CXL specific changes without affecting or adding functionality in the PCIe handling. Make this update alongside the existing Downstream Port RCH error handling logic, extending support to CXL PCIe Ports in VH mode. Remove is_internal_error(). is_internal_error() was used to determine if an AER error was a CXL error. Instead, now rely on pcie_is_cxl_port() to indicate the error is a CXL error. The uncorrectable error (UCE) handling will be added in a future patch. [1] CXL 3.1 Spec, 12.2.2 CXL Root Ports, Downstream Switch Ports, and Upstream Switch Ports Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Ira Weiny Acked-by: Bjorn Helgaas --- drivers/pci/pcie/aer.c | 47 ++++++++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index f99a1c6fb274..34ec0958afff 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -989,14 +989,6 @@ static bool cxl_error_is_native(struct pci_dev *dev) return (pcie_ports_native || host->native_aer); } -static bool is_internal_error(struct aer_err_info *info) -{ - if (info->severity == AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} - static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) { struct aer_err_info *info = (struct aer_err_info *)data; @@ -1033,9 +1025,23 @@ static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) * RCH's downstream port. Check and handle them in the CXL.mem * device driver. */ - if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) + return pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); + + if (info->severity == AER_CORRECTABLE) { + struct pci_driver *pdrv = dev->driver; + int aer = dev->aer_cap; + + if (aer) + pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, + info->status); + + if (pdrv && pdrv->cxl_err_handler && + pdrv->cxl_err_handler->cor_error_detected) + pdrv->cxl_err_handler->cor_error_detected(dev); + + pcie_clear_device_status(dev); + } } static int handles_cxl_error_iter(struct pci_dev *dev, void *data) @@ -1053,9 +1059,13 @@ static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl = false; - if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(dev)) + if (!pcie_aer_is_native(dev)) + return false; + + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); + else + handles_cxl = pcie_is_cxl_port(dev); return handles_cxl; } @@ -1073,6 +1083,10 @@ static void cxl_enable_internal_errors(struct pci_dev *dev) static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } static inline void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { } +static bool handles_cxl_errors(struct pci_dev *dev) +{ + return false; +} #endif /** @@ -1110,8 +1124,11 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) { - cxl_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (handles_cxl_errors(dev)) + cxl_handle_error(dev, info); + else + pci_aer_handle_error(dev, info); + pci_dev_put(dev); } From patchwork Tue Feb 11 19:24:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13970548 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2051.outbound.protection.outlook.com [40.107.244.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1BCC263893; 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Tue, 11 Feb 2025 13:25:56 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 06/17] PCI/AER: Add CXL PCIe Port uncorrectable error recovery in AER service driver Date: Tue, 11 Feb 2025 13:24:33 -0600 Message-ID: <20250211192444.2292833-7-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EE:EE_|SN7PR12MB7021:EE_ X-MS-Office365-Filtering-Correlation-Id: cedd33ca-1b43-40f6-d3f1-08dd4ad1e95a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:25:57.8580 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cedd33ca-1b43-40f6-d3f1-08dd4ad1e95a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7021 Existing recovery procedure for PCIe uncorrectable errors (UCE) does not apply to CXL devices. Recovery can not be used for CXL devices because of potential corruption on what can be system memory. Also, current PCIe UCE recovery, in the case of a Root Port (RP) or Downstream Switch Port (DSP), does not begin at the RP/DSP but begins at the first downstream device. This will miss handling CXL Protocol Errors in a CXL RP or DSP. A separate CXL recovery is needed because of the different handling requirements Add a new function, cxl_do_recovery() using the following. Add cxl_walk_bridge() to iterate the detected error's sub-topology. cxl_walk_bridge() is similar to pci_walk_bridge() but the CXL flavor will begin iteration at the RP or DSP rather than beginning at the first downstream device. pci_walk_bridge() is candidate to possibly reuse cxl_walk_bridge() but needs further investigation. This will be left for future improvement to make the CXL and PCI handling paths more common. Add cxl_report_error_detected() as an analog to report_error_detected(). It will call pci_driver::cxl_err_handlers for each iterated downstream device. The pci_driver::cxl_err_handler's UCE handler returns a boolean indicating if there was a UCE error detected during handling. cxl_do_recovery() uses the status from cxl_report_error_detected() to determine how to proceed. Non-fatal CXL UCE errors will be treated as fatal. If a UCE was present during handling then cxl_do_recovery() will kernel panic. Signed-off-by: Terry Bowman Acked-by: Bjorn Helgaas Reviewed-by: Dave Jiang Reviewed-by: Gregory Price Reviewed-by: Dan Williams Reviewed-by: Jonathan Cameron Reviewed-by: Fan Ni --- drivers/pci/pci.h | 3 +++ drivers/pci/pcie/aer.c | 4 +++ drivers/pci/pcie/err.c | 58 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 3 +++ 4 files changed, 68 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 01e51db8d285..deb193b387af 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -722,6 +722,9 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, pci_channel_state_t state, pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); +/* CXL error reporting and handling */ +void cxl_do_recovery(struct pci_dev *dev); + bool pcie_wait_for_link(struct pci_dev *pdev, bool active); int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 34ec0958afff..ee38db08d005 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1012,6 +1012,8 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) err_handler->error_detected(dev, pci_channel_io_normal); else if (info->severity == AER_FATAL) err_handler->error_detected(dev, pci_channel_io_frozen); + + cxl_do_recovery(dev); } out: device_unlock(&dev->dev); @@ -1041,6 +1043,8 @@ static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) pdrv->cxl_err_handler->cor_error_detected(dev); pcie_clear_device_status(dev); + } else { + cxl_do_recovery(dev); } } diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index 31090770fffc..05f2d1ef4c36 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -24,6 +24,9 @@ static pci_ers_result_t merge_result(enum pci_ers_result orig, enum pci_ers_result new) { + if (new == PCI_ERS_RESULT_PANIC) + return PCI_ERS_RESULT_PANIC; + if (new == PCI_ERS_RESULT_NO_AER_DRIVER) return PCI_ERS_RESULT_NO_AER_DRIVER; @@ -276,3 +279,58 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, return status; } + +static void cxl_walk_bridge(struct pci_dev *bridge, + int (*cb)(struct pci_dev *, void *), + void *userdata) +{ + if (cb(bridge, userdata)) + return; + + if (bridge->subordinate) + pci_walk_bus(bridge->subordinate, cb, userdata); +} + +static int cxl_report_error_detected(struct pci_dev *dev, void *data) +{ + const struct cxl_error_handlers *cxl_err_handler; + pci_ers_result_t vote, *result = data; + struct pci_driver *pdrv; + + device_lock(&dev->dev); + pdrv = dev->driver; + if (!pdrv || !pdrv->cxl_err_handler || + !pdrv->cxl_err_handler->error_detected) + goto out; + + cxl_err_handler = pdrv->cxl_err_handler; + vote = cxl_err_handler->error_detected(dev); + *result = merge_result(*result, vote); +out: + device_unlock(&dev->dev); + return 0; +} + +void cxl_do_recovery(struct pci_dev *dev) +{ + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); + pci_ers_result_t status = PCI_ERS_RESULT_CAN_RECOVER; + + cxl_walk_bridge(dev, cxl_report_error_detected, &status); + if (status == PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + /* + * If we have native control of AER, clear error status in the device + * that detected the error. If the platform retained control of AER, + * it is responsible for clearing this status. In that case, the + * signaling device may not even be visible to the OS. + */ + if (host->native_aer || pcie_ports_native) { + pcie_clear_device_status(dev); + pci_aer_clear_nonfatal_status(dev); + pci_aer_clear_fatal_status(dev); + } + + pci_info(dev, "CXL uncorrectable error.\n"); +} diff --git a/include/linux/pci.h b/include/linux/pci.h index 82a0401c58d3..5b539b5bf0d1 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -864,6 +864,9 @@ enum pci_ers_result { /* No AER capabilities registered for the driver */ PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, + + /* System is unstable, panic */ + PCI_ERS_RESULT_PANIC = (__force pci_ers_result_t) 7, }; /* PCI bus error event callbacks */ From patchwork Tue Feb 11 19:24:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13970549 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2086.outbound.protection.outlook.com [40.107.237.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BAC1263893; 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Tue, 11 Feb 2025 13:26:07 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 07/17] cxl/pci: Map CXL PCIe Root Port and Downstream Switch Port RAS registers Date: Tue, 11 Feb 2025 13:24:34 -0600 Message-ID: <20250211192444.2292833-8-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EC:EE_|LV2PR12MB5824:EE_ X-MS-Office365-Filtering-Correlation-Id: 062654a7-f03d-4634-b194-08dd4ad1efee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:26:08.8933 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 062654a7-f03d-4634-b194-08dd4ad1efee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5824 The CXL mem driver (cxl_mem) currently maps and caches a pointer to RAS registers for the endpoint's Root Port. The same needs to be done for each of the CXL Downstream Switch Ports and CXL Root Ports found between the endpoint and CXL Host Bridge. Introduce cxl_init_ep_ports_aer() to be called for each CXL Port in the sub-topology between the endpoint and the CXL Host Bridge. This function will determine if there are CXL Downstream Switch Ports or CXL Root Ports associated with this Port. The same check will be added in the future for upstream switch ports. Move the RAS register map logic from cxl_dport_map_ras() into cxl_dport_init_ras_reporting(). This eliminates the need for the helper function, cxl_dport_map_ras(). cxl_init_ep_ports_aer() calls cxl_dport_init_ras_reporting() to map the RAS registers for CXL Downstream Switch Ports and CXL Root Ports. cxl_dport_init_ras_reporting() must check for previously mapped registers before mapping. This is required because multiple Endpoints under a CXL switch may share an upstream CXL Root Port, CXL Downstream Switch Port, or CXL Downstream Switch Port. Ensure the RAS registers are only mapped once. Introduce a mutex for synchronizing accesses to the cached RAS mapping. Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Jonathan Cameron Reviewed-by: Gregory Price Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 42 ++++++++++++++++++++---------------------- drivers/cxl/cxl.h | 6 ++---- drivers/cxl/mem.c | 31 +++++++++++++++++++++++++++++-- 3 files changed, 51 insertions(+), 28 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a5c65f79db18..143c853a52c4 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -24,6 +24,8 @@ static unsigned short media_ready_timeout = 60; module_param(media_ready_timeout, ushort, 0644); MODULE_PARM_DESC(media_ready_timeout, "seconds to wait for media ready"); +static DEFINE_MUTEX(ras_init_mutex); + struct cxl_walk_context { struct pci_bus *bus; struct cxl_port *port; @@ -749,18 +751,6 @@ static void cxl_dport_map_rch_aer(struct cxl_dport *dport) } } -static void cxl_dport_map_ras(struct cxl_dport *dport) -{ - struct cxl_register_map *map = &dport->reg_map; - struct device *dev = dport->dport_dev; - - if (!map->component_map.ras.valid) - dev_dbg(dev, "RAS registers not found\n"); - else if (cxl_map_component_regs(map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) - dev_dbg(dev, "Failed to map RAS capability.\n"); -} - static void cxl_disable_rch_root_ints(struct cxl_dport *dport) { void __iomem *aer_base = dport->regs.dport_aer; @@ -788,22 +778,30 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport) /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized - * @host: host device for devm operations */ -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host) +void cxl_dport_init_ras_reporting(struct cxl_dport *dport) { - dport->reg_map.host = host; - cxl_dport_map_ras(dport); - - if (dport->rch) { - struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport->dport_dev); - - if (!host_bridge->native_aer) - return; + struct device *dport_dev = dport->dport_dev; + struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev); + dport->reg_map.host = dport_dev; + if (dport->rch && host_bridge->native_aer) { cxl_dport_map_rch_aer(dport); cxl_disable_rch_root_ints(dport); } + + /* dport may have more than 1 downstream EP. Check if already mapped. */ + mutex_lock(&ras_init_mutex); + if (dport->regs.ras) { + mutex_unlock(&ras_init_mutex); + return; + } + + if (cxl_map_component_regs(&dport->reg_map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_err(dport_dev, "Failed to map RAS capability\n"); + mutex_unlock(&ras_init_mutex); + } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 6baec4ba9141..82d0a8555a11 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -754,11 +754,9 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, resource_size_t rcrb); #ifdef CONFIG_PCIEAER_CXL -void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host); +void cxl_dport_init_ras_reporting(struct cxl_dport *dport); #else -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, - struct device *host) { } +static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport) { } #endif struct cxl_decoder *to_cxl_decoder(struct device *dev); diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 9675243bd05b..8c1144bbc058 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -45,6 +45,31 @@ static int cxl_mem_dpa_show(struct seq_file *file, void *data) return 0; } +static bool dev_is_cxl_pci(struct device *dev, u32 pcie_type) +{ + struct pci_dev *pdev; + + if (!dev || !dev_is_pci(dev)) + return false; + + pdev = to_pci_dev(dev); + + return (pci_pcie_type(pdev) == pcie_type); +} + +static void cxl_init_ep_ports_aer(struct cxl_ep *ep) +{ + struct cxl_dport *dport = ep->dport; + + if (dport) { + struct device *dport_dev = dport->dport_dev; + + if (dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_DOWNSTREAM) || + dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_ROOT_PORT)) + cxl_dport_init_ras_reporting(dport); + } +} + static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, struct cxl_dport *parent_dport) { @@ -52,6 +77,9 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, struct cxl_port *endpoint, *iter, *down; int rc; + if (parent_dport->rch) + cxl_dport_init_ras_reporting(parent_dport); + /* * Now that the path to the root is established record all the * intervening ports in the chain. @@ -62,6 +90,7 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, ep = cxl_ep_load(iter, cxlmd); ep->next = down; + cxl_init_ep_ports_aer(ep); } /* Note: endpoint port component registers are derived from @cxlds */ @@ -166,8 +195,6 @@ static int cxl_mem_probe(struct device *dev) else endpoint_parent = &parent_port->dev; - cxl_dport_init_ras_reporting(dport, dev); - scoped_guard(device, endpoint_parent) { if (!endpoint_parent->driver) { dev_err(dev, "CXL port topology %s not enabled\n", From patchwork Tue Feb 11 19:24:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13970550 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2078.outbound.protection.outlook.com [40.107.101.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F301263893; 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Tue, 11 Feb 2025 13:26:18 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 08/17] cxl/pci: Map CXL PCIe Upstream Switch Port RAS registers Date: Tue, 11 Feb 2025 13:24:35 -0600 Message-ID: <20250211192444.2292833-9-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001ED:EE_|LV2PR12MB5775:EE_ X-MS-Office365-Filtering-Correlation-Id: f2274020-e6f6-4cc5-6025-08dd4ad1f69d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:26:20.1201 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2274020-e6f6-4cc5-6025-08dd4ad1f69d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5775 Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers. Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a pointer to the CXL Upstream Port's mapped RAS registers. Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS register mapping. This is similar to the existing cxl_dport_init_ras_reporting() but for USP devices. The USP may have multiple downstream endpoints. Before mapping RAS registers check if the registers are already mapped. Introduce a mutex for synchronizing accesses to the cached RAS mapping. Signed-off-by: Terry Bowman Reviewed-by: Gregory Price Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 19 ++++++++++++++++++- drivers/cxl/cxl.h | 4 ++++ drivers/cxl/mem.c | 8 ++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 143c853a52c4..25513b9a8aff 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -775,6 +775,24 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } +void cxl_uport_init_ras_reporting(struct cxl_port *port) +{ + + /* uport may have more than 1 downstream EP. Check if already mapped. */ + mutex_lock(&ras_init_mutex); + if (port->uport_regs.ras) { + mutex_unlock(&ras_init_mutex); + return; + } + + port->reg_map.host = &port->dev; + if (cxl_map_component_regs(&port->reg_map, &port->uport_regs, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_err(&port->dev, "Failed to map RAS capability\n"); + mutex_unlock(&ras_init_mutex); +} +EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); + /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized @@ -801,7 +819,6 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) BIT(CXL_CM_CAP_CAP_ID_RAS))) dev_err(dport_dev, "Failed to map RAS capability\n"); mutex_unlock(&ras_init_mutex); - } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 82d0a8555a11..49f29a3ef68e 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -581,6 +581,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @uport_regs: mapped component registers * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation ordering * @commit_end: cursor to track highest committed decoder for commit ordering @@ -602,6 +603,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + struct cxl_component_regs uport_regs; int nr_dports; int hdm_end; int commit_end; @@ -755,8 +757,10 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, #ifdef CONFIG_PCIEAER_CXL void cxl_dport_init_ras_reporting(struct cxl_dport *dport); +void cxl_uport_init_ras_reporting(struct cxl_port *port); #else static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport) { } +static inline void cxl_uport_init_ras_reporting(struct cxl_port *port) { } #endif struct cxl_decoder *to_cxl_decoder(struct device *dev); diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 8c1144bbc058..541cabca434e 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -60,6 +60,7 @@ static bool dev_is_cxl_pci(struct device *dev, u32 pcie_type) static void cxl_init_ep_ports_aer(struct cxl_ep *ep) { struct cxl_dport *dport = ep->dport; + struct cxl_port *port = ep->next; if (dport) { struct device *dport_dev = dport->dport_dev; @@ -68,6 +69,13 @@ static void cxl_init_ep_ports_aer(struct cxl_ep *ep) dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_ROOT_PORT)) cxl_dport_init_ras_reporting(dport); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:26:31.1861 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e3728a5-9f94-4b5f-4ad0-08dd4ad1fd38 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9510 CXL PCIe Port Protocol Error handling support will be added to the CXL drivers in the future. In preparation, rename the existing interfaces to support handling all CXL PCIe Port Protocol Errors. The driver's RAS support functions currently rely on a 'struct cxl_dev_state' type parameter, which is not available for CXL Port devices. However, since the same CXL RAS capability structure is needed across most CXL components and devices, a common handling approach should be adopted. To accommodate this, update the __cxl_handle_cor_ras() and __cxl_handle_ras() functions to use a `struct device` instead of `struct cxl_dev_state`. No functional changes are introduced. [1] CXL 3.1 Spec, 8.2.4 CXL.cache and CXL.mem Registers Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 25513b9a8aff..69bb030aa8e1 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -652,7 +652,7 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, +static void __cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { void __iomem *addr; @@ -665,13 +665,13 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, status = readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); } } static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) { - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); + return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } /* CXL spec rev3.0 8.2.4.16.1 */ @@ -695,8 +695,7 @@ static void header_log_copy(void __iomem *ras_base, u32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -723,7 +722,7 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, } header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); return true; @@ -731,7 +730,7 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) { - return __cxl_handle_ras(cxlds, cxlds->regs.ras); + return __cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } #ifdef CONFIG_PCIEAER_CXL @@ -825,13 +824,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:26:42.3250 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 044b0880-69b9-41f2-922d-08dd4ad203d9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6483 The CXL RAS handlers do not currently log if the RAS registers are unmapped. This is needed in order to help debug CXL error handling. Update the CXL driver to log a warning message if the RAS register block is unmapped. Also, add type check before processing EP or RCH DP. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 69bb030aa8e1..af809e7cbe3b 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -658,15 +658,19 @@ static void __cxl_handle_cor_ras(struct device *dev, void __iomem *addr; u32 status; - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return; + } addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status = readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) + return; + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + + if (is_cxl_memdev(dev)) trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); - } } static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) @@ -702,8 +706,10 @@ static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) u32 status; u32 fe; - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return false; + } addr = ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status = readl(addr); @@ -722,7 +728,9 @@ static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) } header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + if (is_cxl_memdev(dev)) + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); return true; From patchwork Tue Feb 11 19:24:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13970553 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2081.outbound.protection.outlook.com [40.107.237.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21D5B26D5CB; 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Tue, 11 Feb 2025 13:26:52 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 11/17] cxl/pci: Change find_cxl_port() to non-static Date: Tue, 11 Feb 2025 13:24:38 -0600 Message-ID: <20250211192444.2292833-12-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001ED:EE_|SA3PR12MB7859:EE_ X-MS-Office365-Filtering-Correlation-Id: 385ad1ea-77ea-4838-47d1-08dd4ad20a7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026|921020; X-Microsoft-Antispam-Message-Info: ZTpgbHmBc4d45VCLl938ja4pNq7iGmryf7CMIcH47jVol9HlNEJGYOAfyNwWjnLNdSDRqs/feY0fncOevYjNEyt/01aX6+qfNKnPHwd7j+BOV5Vcljz5nJ+/fULWCCWaAcriOqP0U7ez6xJ/dSjLTRUSJ431hBEINJgBdN4Gfe/ZszehKozJaggiIUtS35c105+9GDPmN23e67GA8xkIgBef/4Ww6uHOSASbP50iSbxP0b5k205gm5IiRBEPaz1tnbd7R0q370af2cvpO7hxZWxXPKQRdbgzPAKj0wGCWVTZUIvgeNtzj68RRkQg9xdR+jFd0EipPsUv4AEuYQKOPw1+wGzXBA2VXEW6n2uRSjlNldY6ikmCf7NPulwQZqDT5hcQSAoYL2kU2ew6EUpL7bsU9DWgmVWvlg3a/QOIMoHLvdQEyR8Gi1WsH/T5qJl2VaL/8TDEzVFGxJPZ2eqbCbnktfMHR7qIsXbYivh+iCZ8htrRrg1E5hAcp41X0MTUkvqEiDnmLOiudAKQUcQyTZEw0FpglujM2cWnxp5jagm+S/Izg9t+byoubVdXgrQ0eZsnE02d4Y31kVjZzot/ENAdsRGw0ZeU0ZP9GpQBDMxSDrGPtR6r24hAU+BLWu98QcmakYonrvYk6V9cA+0Fj6RTpXHEgEsaUOnWhL6pwttjBUW/GMZ6hUNifUNd6AQ8yia6oS+ZvQq/TQmdFZpV0RLQHfm1YGXz0/9E4lWJqTzH4c/jxOgGWbD6HpyI1KKNlwwwuiM8v8kilOEHjHRe/QLFm8sC/KSs+ECsgeRVfZdEdrq5epKGUqHI34D0vmvfOs77YwxNZvdEcHvRh7pjyBted94d8M+NQ82sSn2ocG8G/7LrZvkmzcW+udDyETzl52b+R0ZK6JYH2kMOu7H/BDf3O1AtkNtf6LvSrk8RrWiHSyGw0uKUXlFizDuDga7/s945MoAkHFpzltNg3kPxTKqUdFSNGXVuXv8POJuiA110lT7E004mjUa/NDaBNnk9YyxJfAUGcTHsATXOw/zPs76SAiEmN55100jmXNcyh1UV4ezTl/fjazfgAytbJ9/yZ7dIPFUzwusK40D/JKMUPdf3/Ciji/7ZRB839WsF8SZZXznEhZP9srPedhyry085x8CIlYzHtJVplVlFroDlUywv7G460FglAA4Tuh6xl03y2X+w7oQ6SrBdnFHGsU9TUZnm5q6oS7r5tfKVpbmPZITIe5H9idVs5bfKwQnEoxwU2hsz9wc/D/Jc4nW7EqKM1pUEahELeI5XPZ2l19T0EVSyaHpp9DukA7aatHMUUJ3G+LyxguakWVZ0fVyaqHYeTrpwCPPDDtDHTe2vLx5etvurlpJvQ/BkDgmYrDydbOV1STBNfmYqAqDA5e414jhZJPissKCnjG2uRrWDuek+55TSsEGuQEinmV6sdIMzR/mdCuq5fQvaKV4Ra9oj9wS1DlJ8DgkTCyBWbfgohxBrlf/8eaFgQBeJaroC3hflvsc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026)(921020);DIR:OUT;SFP:1101; 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This requires searching for a CXL PCIe Port device in the CXL topology as provided by find_cxl_port(). But, find_cxl_port() is defined static and as a result is not callable outside of this source file. Update the find_cxl_port() declaration to be non-static. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Reviewed-by: Dave Jiang --- drivers/cxl/core/core.h | 2 ++ drivers/cxl/core/port.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index a20ea2b7d1a4..796334f2ad6c 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -118,5 +118,7 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, struct access_coordinate *c); int cxl_gpf_port_setup(struct device *dport_dev, struct cxl_port *port); +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport); #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index f9501a16b390..ae6471e4ebff 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1352,8 +1352,8 @@ static struct cxl_port *__find_cxl_port(struct cxl_find_port_ctx *ctx) return NULL; } -static struct cxl_port *find_cxl_port(struct device *dport_dev, - struct cxl_dport **dport) +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx = { .dport_dev = dport_dev, From patchwork Tue Feb 11 19:24:39 2025 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:27:04.9632 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64459de9-e4db-4472-a8a3-08dd4ad2115c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6594 Introduce correctable and uncorrectable (UCE) CXL PCIe Port Protocol Error handlers. The handlers will be called with a 'struct pci_dev' parameter indicating the CXL Port device requiring handling. The CXL PCIe Port device's underlying 'struct device' will match the port device in the CXL topology. Use the PCIe Port's device object to find the matching CXL Upstream Switch Port, CXL Downstream Switch Port, or CXL Root Port in the CXL topology. The matching CXL Port device should contain a cached reference to the RAS register block. The cached RAS block will be used in handling the error. Invoke the existing __cxl_handle_ras() or __cxl_handle_cor_ras() using a reference to the RAS registers as a parameter. These functions will use the RAS register reference to indicate an error and clear the device's RAS status. Update __cxl_handle_ras() to return PCI_ERS_RESULT_PANIC in the case an error is present in the RAS status. Otherwise, return PCI_ERS_RESULT_NONE. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 81 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 77 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index af809e7cbe3b..3f13d9dfb610 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -699,7 +699,7 @@ static void header_log_copy(void __iomem *ras_base, u32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) +static pci_ers_result_t __cxl_handle_ras(struct device *dev, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -708,13 +708,13 @@ static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) if (!ras_base) { dev_warn_once(dev, "CXL RAS register block is not mapped"); - return false; + return PCI_ERS_RESULT_NONE; } addr = ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status = readl(addr); if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) - return false; + return PCI_ERS_RESULT_NONE; /* If multiple errors, log header points to first error from ctrl reg */ if (hweight32(status) > 1) { @@ -733,7 +733,7 @@ static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); - return true; + return PCI_ERS_RESULT_PANIC; } static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) @@ -782,6 +782,79 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } +static int match_uport(struct device *dev, const void *data) +{ + const struct device *uport_dev = data; + struct cxl_port *port; + + if (!is_cxl_port(dev)) + return 0; + + port = to_cxl_port(dev); + + return port->uport_dev == uport_dev; +} + +static void __iomem *cxl_pci_port_ras(struct pci_dev *pdev, struct device **dev) +{ + void __iomem *ras_base; + + if (!pdev || !*dev) { + pr_err("Failed, parameter is NULL"); + return NULL; + } + + if ((pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) || + (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)) { + struct cxl_port *port __free(put_cxl_port); + struct cxl_dport *dport = NULL; + + port = find_cxl_port(&pdev->dev, &dport); + if (!port) { + pci_err(pdev, "Failed to find root/dport in CXL topology\n"); + return NULL; + } + + ras_base = dport ? dport->regs.ras : NULL; + *dev = &port->dev; + } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_UPSTREAM) { + struct device *port_dev __free(put_device); + struct cxl_port *port; + + port_dev = bus_find_device(&cxl_bus_type, NULL, &pdev->dev, + match_uport); + if (!port_dev || !is_cxl_port(port_dev)) { + pci_err(pdev, "Failed to find uport in CXL topology\n"); + return NULL; + } + + port = to_cxl_port(port_dev); + ras_base = port ? port->uport_regs.ras : NULL; + *dev = port_dev; + } else { + pci_err(pdev, "Unsupported device type\n"); + ras_base = NULL; + } + + return ras_base; +} + +static void cxl_port_cor_error_detected(struct pci_dev *pdev) +{ + struct device *dev; + void __iomem *ras_base = cxl_pci_port_ras(pdev, &dev); + + __cxl_handle_cor_ras(dev, ras_base); +} + +static pci_ers_result_t cxl_port_error_detected(struct pci_dev *pdev) +{ + struct device *dev; + void __iomem *ras_base = cxl_pci_port_ras(pdev, &dev); + + return __cxl_handle_ras(dev, ras_base); +} + void cxl_uport_init_ras_reporting(struct cxl_port *port) { From patchwork Tue Feb 11 19:24:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13970555 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2047.outbound.protection.outlook.com [40.107.96.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E8C826B2A3; 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Tue, 11 Feb 2025 13:27:14 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 13/17] cxl/pci: Add trace logging for CXL PCIe Port RAS errors Date: Tue, 11 Feb 2025 13:24:40 -0600 Message-ID: <20250211192444.2292833-14-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EC:EE_|DM6PR12MB4252:EE_ X-MS-Office365-Filtering-Correlation-Id: f5311cac-70d8-4ed6-3d26-08dd4ad21842 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:27:16.5653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5311cac-70d8-4ed6-3d26-08dd4ad21842 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4252 The CXL drivers use kernel trace functions for logging Endpoint and Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL Upstream Switch Ports. Introduce trace logging functions for both RAS correctable and uncorrectable errors specific to CXL PCIe Ports. Additionally, update the CXL Port Protocol Error handlers to invoke these new trace functions. Examples of the output from these changes is below. Correctable error: cxl_port_aer_correctable_error: device=port1 parent=root0 status='Received Error From Physical Layer' Uncorrectable error: cxl_port_aer_uncorrectable_error: device=port1 parent=root0 status: 'Memory Byte Enable Parity Error' first_error: 'Memory Byte Enable Parity Erro' Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Jonathan Cameron Reviewed-by: Gregory Price Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 4 ++++ drivers/cxl/core/trace.h | 47 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 3f13d9dfb610..9a3090dae46a 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -671,6 +671,8 @@ static void __cxl_handle_cor_ras(struct device *dev, if (is_cxl_memdev(dev)) trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); + else if (is_cxl_port(dev)) + trace_cxl_port_aer_correctable_error(dev, status); } static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) @@ -730,6 +732,8 @@ static pci_ers_result_t __cxl_handle_ras(struct device *dev, void __iomem *ras_b header_log_copy(ras_base, hl); if (is_cxl_memdev(dev)) trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + else if (is_cxl_port(dev)) + trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index cea706b683b5..b536233ac210 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -48,6 +48,34 @@ { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ ) +TRACE_EVENT(cxl_port_aer_uncorrectable_error, + TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), + TP_ARGS(dev, status, fe, hl), + TP_STRUCT__entry( + __string(devname, dev_name(dev)) + __string(parent, dev_name(dev->parent)) + __field(u32, status) + __field(u32, first_error) + __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) + ), + TP_fast_assign( + __assign_str(devname); + __assign_str(parent); + __entry->status = status; + __entry->first_error = fe; + /* + * Embed the 512B headerlog data for user app retrieval and + * parsing, but no need to print this in the trace buffer. + */ + memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); + ), + TP_printk("device=%s parent=%s status: '%s' first_error: '%s'", + __get_str(devname), __get_str(parent), + show_uc_errs(__entry->status), + show_uc_errs(__entry->first_error) + ) +); + TRACE_EVENT(cxl_aer_uncorrectable_error, TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), TP_ARGS(cxlmd, status, fe, hl), @@ -96,6 +124,25 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ ) +TRACE_EVENT(cxl_port_aer_correctable_error, + TP_PROTO(struct device *dev, u32 status), + TP_ARGS(dev, status), + TP_STRUCT__entry( + __string(devname, dev_name(dev)) + __string(parent, dev_name(dev->parent)) + __field(u32, status) + ), + TP_fast_assign( + __assign_str(devname); + __assign_str(parent); + __entry->status = status; + ), + TP_printk("device=%s parent=%s status='%s'", + __get_str(devname), __get_str(parent), + show_ce_errs(__entry->status) + ) +); + TRACE_EVENT(cxl_aer_correctable_error, TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), TP_ARGS(cxlmd, status), From patchwork Tue Feb 11 19:24:41 2025 Content-Type: text/plain; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001E9.mail.protection.outlook.com (10.167.242.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8445.10 via Frontend Transport; Tue, 11 Feb 2025 19:27:27 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 11 Feb 2025 13:27:25 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 14/17] cxl/pci: Update CXL Port RAS logging to also display PCIe SBDF Date: Tue, 11 Feb 2025 13:24:41 -0600 Message-ID: <20250211192444.2292833-15-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E9:EE_|IA0PR12MB8716:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d2137c1-7e13-4659-a073-08dd4ad21eb0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:27:27.3395 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d2137c1-7e13-4659-a073-08dd4ad21eb0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8716 CXL RAS errors are currently logged using the associated CXL port's name returned from devname(). They are typically named with 'port1', 'port2', etc. to indicate the hierarchial location in the CXL topology. But, this doesn't clearly indicate the CXL card or slot reporting the error. Update the logging to also log the corresponding PCIe devname. This will give a PCIe SBDF or ACPI object name (in case of CXL HB). This will provide details helping users understand which physical slot and card has the error. Below is example output after making these changes. Correctable error example output: cxl_port_aer_correctable_error: device=port1 (0000:0c:00.0) parent=root0 (pci0000:0c) status='Received Error From Physical Layer' Uncorrectable error example output: cxl_port_aer_uncorrectable_error: device=port1 (0000:0c:00.0) parent=root0 (pci0000:0c) status: 'Memory Byte Enable Parity Error' first_error: 'Memory Byte Enable Parity Error' Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 39 +++++++++++++++++++------------------ drivers/cxl/core/trace.h | 42 +++++++++++++++++++++++++--------------- 2 files changed, 46 insertions(+), 35 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 9a3090dae46a..f154dcf6dfda 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -652,14 +652,14 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); -static void __cxl_handle_cor_ras(struct device *dev, +static void __cxl_handle_cor_ras(struct device *cxl_dev, struct device *pcie_dev, void __iomem *ras_base) { void __iomem *addr; u32 status; if (!ras_base) { - dev_warn_once(dev, "CXL RAS register block is not mapped"); + dev_warn_once(cxl_dev, "CXL RAS register block is not mapped"); return; } @@ -669,15 +669,15 @@ static void __cxl_handle_cor_ras(struct device *dev, return; writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - if (is_cxl_memdev(dev)) - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); - else if (is_cxl_port(dev)) - trace_cxl_port_aer_correctable_error(dev, status); + if (is_cxl_memdev(cxl_dev)) + trace_cxl_aer_correctable_error(to_cxl_memdev(cxl_dev), status); + else if (is_cxl_port(cxl_dev)) + trace_cxl_port_aer_correctable_error(cxl_dev, pcie_dev, status); } static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) { - return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, NULL, cxlds->regs.ras); } /* CXL spec rev3.0 8.2.4.16.1 */ @@ -701,7 +701,8 @@ static void header_log_copy(void __iomem *ras_base, u32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static pci_ers_result_t __cxl_handle_ras(struct device *dev, void __iomem *ras_base) +static pci_ers_result_t __cxl_handle_ras(struct device *cxl_dev, struct device *pcie_dev, + void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -709,7 +710,7 @@ static pci_ers_result_t __cxl_handle_ras(struct device *dev, void __iomem *ras_b u32 fe; if (!ras_base) { - dev_warn_once(dev, "CXL RAS register block is not mapped"); + dev_warn_once(cxl_dev, "CXL RAS register block is not mapped"); return PCI_ERS_RESULT_NONE; } @@ -730,10 +731,10 @@ static pci_ers_result_t __cxl_handle_ras(struct device *dev, void __iomem *ras_b } header_log_copy(ras_base, hl); - if (is_cxl_memdev(dev)) - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); - else if (is_cxl_port(dev)) - trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); + if (is_cxl_memdev(cxl_dev)) + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(cxl_dev), status, fe, hl); + else if (is_cxl_port(cxl_dev)) + trace_cxl_port_aer_uncorrectable_error(cxl_dev, pcie_dev, status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); @@ -742,7 +743,7 @@ static pci_ers_result_t __cxl_handle_ras(struct device *dev, void __iomem *ras_b static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) { - return __cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + return __cxl_handle_ras(&cxlds->cxlmd->dev, NULL, cxlds->regs.ras); } #ifdef CONFIG_PCIEAER_CXL @@ -814,7 +815,7 @@ static void __iomem *cxl_pci_port_ras(struct pci_dev *pdev, struct device **dev) struct cxl_dport *dport = NULL; port = find_cxl_port(&pdev->dev, &dport); - if (!port) { + if (!port || !is_cxl_port(&port->dev)) { pci_err(pdev, "Failed to find root/dport in CXL topology\n"); return NULL; } @@ -848,7 +849,7 @@ static void cxl_port_cor_error_detected(struct pci_dev *pdev) struct device *dev; void __iomem *ras_base = cxl_pci_port_ras(pdev, &dev); - __cxl_handle_cor_ras(dev, ras_base); + __cxl_handle_cor_ras(dev, &pdev->dev, ras_base); } static pci_ers_result_t cxl_port_error_detected(struct pci_dev *pdev) @@ -856,7 +857,7 @@ static pci_ers_result_t cxl_port_error_detected(struct pci_dev *pdev) struct device *dev; void __iomem *ras_base = cxl_pci_port_ras(pdev, &dev); - return __cxl_handle_ras(dev, ras_base); + return __cxl_handle_ras(dev, &pdev->dev, ras_base); } void cxl_uport_init_ras_reporting(struct cxl_port *port) @@ -909,13 +910,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras); + return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, NULL, dport->regs.ras); } static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); + return __cxl_handle_ras(&cxlds->cxlmd->dev, NULL, dport->regs.ras); } /* diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index b536233ac210..a74803f4aa22 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -49,18 +49,22 @@ ) TRACE_EVENT(cxl_port_aer_uncorrectable_error, - TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), - TP_ARGS(dev, status, fe, hl), + TP_PROTO(struct device *cxl_dev, struct device *pcie_dev, u32 status, u32 fe, u32 *hl), + TP_ARGS(cxl_dev, pcie_dev, status, fe, hl), TP_STRUCT__entry( - __string(devname, dev_name(dev)) - __string(parent, dev_name(dev->parent)) + __string(cxl_name, dev_name(cxl_dev)) + __string(cxl_parent_name, dev_name(cxl_dev->parent)) + __string(pcie_name, dev_name(pcie_dev)) + __string(pcie_parent_name, dev_name(pcie_dev->parent)) __field(u32, status) __field(u32, first_error) __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) ), TP_fast_assign( - __assign_str(devname); - __assign_str(parent); + __assign_str(cxl_name); + __assign_str(cxl_parent_name); + __assign_str(pcie_name); + __assign_str(pcie_parent_name); __entry->status = status; __entry->first_error = fe; /* @@ -69,8 +73,9 @@ TRACE_EVENT(cxl_port_aer_uncorrectable_error, */ memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); ), - TP_printk("device=%s parent=%s status: '%s' first_error: '%s'", - __get_str(devname), __get_str(parent), + TP_printk("device=%s (%s) parent=%s (%s) status: '%s' first_error: '%s'", + __get_str(cxl_name), __get_str(pcie_name), + __get_str(cxl_parent_name), __get_str(pcie_parent_name), show_uc_errs(__entry->status), show_uc_errs(__entry->first_error) ) @@ -125,20 +130,25 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, ) TRACE_EVENT(cxl_port_aer_correctable_error, - TP_PROTO(struct device *dev, u32 status), - TP_ARGS(dev, status), + TP_PROTO(struct device *cxl_dev, struct device *pcie_dev, u32 status), + TP_ARGS(cxl_dev, pcie_dev, status), TP_STRUCT__entry( - __string(devname, dev_name(dev)) - __string(parent, dev_name(dev->parent)) + __string(cxl_name, dev_name(cxl_dev)) + __string(cxl_parent_name, dev_name(cxl_dev->parent)) + __string(pcie_name, dev_name(pcie_dev)) + __string(pcie_parent_name, dev_name(pcie_dev->parent)) __field(u32, status) ), TP_fast_assign( - __assign_str(devname); - __assign_str(parent); + __assign_str(cxl_name); + __assign_str(cxl_parent_name); + __assign_str(pcie_name); + __assign_str(pcie_parent_name); __entry->status = status; ), - TP_printk("device=%s parent=%s status='%s'", - __get_str(devname), __get_str(parent), + TP_printk("device=%s (%s) parent=%s (%s) status='%s'", + __get_str(cxl_name), __get_str(pcie_name), + __get_str(cxl_parent_name), __get_str(pcie_parent_name), show_ce_errs(__entry->status) ) ); From patchwork Tue Feb 11 19:24:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13970557 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2079.outbound.protection.outlook.com [40.107.236.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3B6326E62D; Tue, 11 Feb 2025 19:27:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 11 Feb 2025 13:27:36 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 15/17] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Date: Tue, 11 Feb 2025 13:24:42 -0600 Message-ID: <20250211192444.2292833-16-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EB:EE_|CH3PR12MB8210:EE_ X-MS-Office365-Filtering-Correlation-Id: 306a9ac8-adf5-4d16-9144-08dd4ad2253c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:27:38.3229 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 306a9ac8-adf5-4d16-9144-08dd4ad2253c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8210 pci_driver::cxl_err_handlers are not currently assigned handler callbacks. The handlers can't be set in the pci_driver static definition because the CXL PCIe Port devices are bound to the portdrv driver which is not CXL driver aware. Add cxl_assign_port_error_handlers() in the cxl_core module. This function will assign the default handlers for a CXL PCIe Port device. When the CXL Port (cxl_port or cxl_dport) is destroyed the device's pci_driver::cxl_err_handlers must be set to NULL indicating they should no longer be used. Create cxl_clear_port_error_handlers() and register it to be called when the CXL Port device (cxl_port or cxl_dport) is destroyed. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 59 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index f154dcf6dfda..03ae21a944e0 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -860,8 +860,39 @@ static pci_ers_result_t cxl_port_error_detected(struct pci_dev *pdev) return __cxl_handle_ras(dev, &pdev->dev, ras_base); } +static const struct cxl_error_handlers cxl_port_error_handlers = { + .error_detected = cxl_port_error_detected, + .cor_error_detected = cxl_port_cor_error_detected, +}; + +static void cxl_assign_port_error_handlers(struct pci_dev *pdev) +{ + struct pci_driver *pdrv; + + if (!pdev || !pdev->driver || !get_device(&pdev->dev)) + return; + + pdrv = pdev->driver; + pdrv->cxl_err_handler = &cxl_port_error_handlers; + put_device(&pdev->dev); +} + +static void cxl_clear_port_error_handlers(void *data) +{ + struct pci_dev *pdev = data; + struct pci_driver *pdrv; + + if (!pdev || !pdev->driver || !get_device(&pdev->dev)) + return; + + pdrv = pdev->driver; + pdrv->cxl_err_handler = NULL; + put_device(&pdev->dev); +} + void cxl_uport_init_ras_reporting(struct cxl_port *port) { + struct pci_dev *pdev = to_pci_dev(port->uport_dev); /* uport may have more than 1 downstream EP. Check if already mapped. */ mutex_lock(&ras_init_mutex); @@ -872,9 +903,15 @@ void cxl_uport_init_ras_reporting(struct cxl_port *port) port->reg_map.host = &port->dev; if (cxl_map_component_regs(&port->reg_map, &port->uport_regs, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_err(&port->dev, "Failed to map RAS capability\n"); + mutex_unlock(&ras_init_mutex); + return; + } mutex_unlock(&ras_init_mutex); + + cxl_assign_port_error_handlers(pdev); + devm_add_action_or_reset(&port->dev, cxl_clear_port_error_handlers, pdev); } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); @@ -886,6 +923,8 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) { struct device *dport_dev = dport->dport_dev; struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev); + struct pci_dev *pdev = to_pci_dev(dport_dev); + struct cxl_port *port; dport->reg_map.host = dport_dev; if (dport->rch && host_bridge->native_aer) { @@ -901,9 +940,25 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) } if (cxl_map_component_regs(&dport->reg_map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_err(dport_dev, "Failed to map RAS capability\n"); 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Tue, 11 Feb 2025 13:27:48 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 16/17] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports Date: Tue, 11 Feb 2025 13:24:43 -0600 Message-ID: <20250211192444.2292833-17-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E8:EE_|SJ2PR12MB8036:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e1f030b-d1d7-4e80-8ae5-08dd4ad22bdd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|36860700013|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:27:49.4442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e1f030b-d1d7-4e80-8ae5-08dd4ad22bdd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8036 The AER service driver enables PCIe Uncorrectable Internal Errors (UIE) and Correctable Internal errors (CIE) for CXL Root Ports. The UIE and CIE are used in reporting CXL Protocol Errors. The same UIE/CIE enablement is needed for CXL Upstream Switch Ports and CXL Downstream Switch Ports inorder to notify the associated Root Port and OS.[1] Export the AER service driver's pci_aer_unmask_internal_errors() function to CXL namespace. Remove the function's dependency on the CONFIG_PCIEAER_CXL kernel config because it is now an exported function. Call pci_aer_unmask_internal_errors() during RAS initialization in: cxl_uport_init_ras_reporting() and cxl_dport_init_ras_reporting(). [1] PCIe Base Spec r6.2-1.0, 6.2.3.2.2 Masking Individual Errors Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Acked-by: Bjorn Helgaas Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 2 ++ drivers/pci/pcie/aer.c | 3 ++- include/linux/aer.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 03ae21a944e0..36e686a31045 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -912,6 +912,7 @@ void cxl_uport_init_ras_reporting(struct cxl_port *port) cxl_assign_port_error_handlers(pdev); devm_add_action_or_reset(&port->dev, cxl_clear_port_error_handlers, pdev); + pci_aer_unmask_internal_errors(pdev); } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); @@ -959,6 +960,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) cxl_assign_port_error_handlers(pdev); devm_add_action_or_reset(&port->dev, cxl_clear_port_error_handlers, pdev); put_device(&port->dev); + pci_aer_unmask_internal_errors(pdev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index ee38db08d005..8e3a60411610 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -948,7 +948,7 @@ static bool find_source_device(struct pci_dev *parent, * Note: AER must be enabled and supported by the device which must be * checked in advance, e.g. with pcie_aer_is_native(). */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +void pci_aer_unmask_internal_errors(struct pci_dev *dev) { int aer = dev->aer_cap; u32 mask; @@ -961,6 +961,7 @@ static void pci_aer_unmask_internal_errors(struct pci_dev *dev) mask &= ~PCI_ERR_COR_INTERNAL; pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); } +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); static bool is_cxl_mem_dev(struct pci_dev *dev) { diff --git a/include/linux/aer.h b/include/linux/aer.h index 947b63091902..a54545796edc 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -61,5 +61,6 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, int cper_severity_to_aer(int cper_severity); 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Tue, 11 Feb 2025 19:28:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001EA.mail.protection.outlook.com (10.167.242.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8445.10 via Frontend Transport; Tue, 11 Feb 2025 19:28:00 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 11 Feb 2025 13:27:59 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 17/17] cxl/pci: Handle CXL Endpoint and RCH Protocol Errors separately from PCIe errors Date: Tue, 11 Feb 2025 13:24:44 -0600 Message-ID: <20250211192444.2292833-18-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EA:EE_|BL3PR12MB6450:EE_ X-MS-Office365-Filtering-Correlation-Id: 6df75a7a-0b7a-4026-6082-08dd4ad23275 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:28:00.4900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6df75a7a-0b7a-4026-6082-08dd4ad23275 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6450 CXL Endpoint and Restricted CXL Host (RCH) Downstream Port Protocol Errors are currently treated as PCIe errors, which does not properly process CXL uncorrectable (UCE) errors. When a CXL device encounters an uncorrectable Protocol Error, the system should panic to prevent potential CXL memory corruption. Treat CXL Endpoint Protocol Errors as CXL errors. This requires updates in the CXL and AER drivers. Update the CXL Endpoint driver with a new declaration for struct cxl_error_handlers named cxl_ep_error_handlers. Move the existing CE and UCE handler assignments from cxl_error_handlers to the new cxl_ep_error_handlers. Remove the 'state' parameter from the UCE handler interface because it is not used in CXL recovery. Update the AER driver to associate CXL Protocol errors with CXL error handling. Change detection in handles_cxl_errors() from using pcie_is_cxl_port() to instead use pcie_is_cxl(). Update AER driver to use CXL handlers for RCH handling. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 26 +++++--------------------- drivers/cxl/cxlpci.h | 3 +-- drivers/cxl/pci.c | 10 +++++++--- drivers/pci/pcie/aer.c | 11 ++++++----- 4 files changed, 19 insertions(+), 31 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 36e686a31045..18d47a14959e 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1075,8 +1075,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +pci_ers_result_t cxl_error_detected(struct pci_dev *pdev) { struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); struct cxl_memdev *cxlmd = cxlds->cxlmd; @@ -1088,7 +1087,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, dev_warn(&pdev->dev, "%s: memdev disabled, abort error handling\n", dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; + return PCI_ERS_RESULT_PANIC; } if (cxlds->rcd) @@ -1102,26 +1101,11 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, ue = cxl_handle_endpoint_ras(cxlds); } - - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); + if (ue) { device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); - return PCI_ERS_RESULT_DISCONNECT; + return PCI_ERS_RESULT_PANIC; } - return PCI_ERS_RESULT_NEED_RESET; + return PCI_ERS_RESULT_CAN_RECOVER; } EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 54e219b0049e..4b8910d934d5 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -133,6 +133,5 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info); void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state); +pci_ers_result_t cxl_error_detected(struct pci_dev *pdev); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index b2c943a4de0a..520570741402 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1104,11 +1104,14 @@ static void cxl_reset_done(struct pci_dev *pdev) } } -static const struct pci_error_handlers cxl_error_handlers = { +static const struct cxl_error_handlers cxl_ep_error_handlers = { .error_detected = cxl_error_detected, + .cor_error_detected = cxl_cor_error_detected, +}; + +static const struct pci_error_handlers pcie_ep_error_handlers = { .slot_reset = cxl_slot_reset, .resume = cxl_error_resume, - .cor_error_detected = cxl_cor_error_detected, .reset_done = cxl_reset_done, }; @@ -1116,7 +1119,8 @@ static struct pci_driver cxl_pci_driver = { .name = KBUILD_MODNAME, .id_table = cxl_mem_pci_tbl, .probe = cxl_pci_probe, - .err_handler = &cxl_error_handlers, + .err_handler = &pcie_ep_error_handlers, + .cxl_err_handler = &cxl_ep_error_handlers, .dev_groups = cxl_rcd_groups, .driver = { .probe_type = PROBE_PREFER_ASYNCHRONOUS, diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 8e3a60411610..07c888fd4c08 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -993,7 +993,7 @@ static bool cxl_error_is_native(struct pci_dev *dev) static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) { struct aer_err_info *info = (struct aer_err_info *)data; - const struct pci_error_handlers *err_handler; + const struct cxl_error_handlers *err_handler; if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) return 0; @@ -1001,7 +1001,8 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) /* protect dev->driver */ device_lock(&dev->dev); - err_handler = dev->driver ? dev->driver->err_handler : NULL; + err_handler = dev->driver ? dev->driver->cxl_err_handler : NULL; + if (!err_handler) goto out; @@ -1010,9 +1011,9 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) err_handler->cor_error_detected(dev); } else if (err_handler->error_detected) { if (info->severity == AER_NONFATAL) - err_handler->error_detected(dev, pci_channel_io_normal); + err_handler->error_detected(dev); else if (info->severity == AER_FATAL) - err_handler->error_detected(dev, pci_channel_io_frozen); + err_handler->error_detected(dev); cxl_do_recovery(dev); } @@ -1070,7 +1071,7 @@ static bool handles_cxl_errors(struct pci_dev *dev) if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); else - handles_cxl = pcie_is_cxl_port(dev); + handles_cxl = pcie_is_cxl(dev); return handles_cxl; }