From patchwork Thu Feb 13 08:00:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziqi Chen X-Patchwork-Id: 13972894 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 253F520C01B; Thu, 13 Feb 2025 08:01:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739433666; cv=none; b=VDQe9hbYzyJpwB2114dXLcaNQhqz3sY5sM9UBlZBM/MkW/GRZWK4UwmDuRgalgirbf+VqGpOtVzqKg7ZHXEAhC/h0A1mPhznXGjV2EBuncQJENCsQj/fg7aYqeQg6Myqc+zzKlZ3zPGnoO5cG7mfN45yhJIVSc8v5qD2pThpH0Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739433666; c=relaxed/simple; bh=vON2EdKdTK85san+UPH/37K4OC7Xko4x35OvCzJ6LJI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iMjGp1Uf1IK6K38XyGDDiTzr3hSzJ+7AOPhNT3lYPZhDVBih6Gdh+QK5haPCqZIz8DKaS6ncyyCRNer4IyCNF1Lf1DcTK3kkipqAgNhu887CzLcCe4hGfFJbCtikp3Jks6/9OQ/A2FKyWjPLJftCvQWu9cOEhBKRbyRXpJvHfss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=aOH/gW2x; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="aOH/gW2x" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51CLAKpW026628; Thu, 13 Feb 2025 08:00:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=kcXMXBydClX JG21enc1D63EjY+VSku5uMG/oiFrstO0=; b=aOH/gW2xtMAfD8z7Pz2GGJosSQo fALCyxWa19bzOia4/hqfrUyU0SY8kO8VehumZ6gVUCpeIC+Qi68a0IxsHZY1AbPA 6sgnZjWxWU5QQpIGiBp7SYiinbTd+/U4AV7myWqFbDOBgqoW7YY0Nz2HXXwQlC9p BCTCKKiejvZlBHOXkKZyYEhgezPARfXKh3qEIjuqJvc4aUcYWOLXdvjCMMyHdLes 0qR68gN6i7chokexAftiZY2FKnyp9C7919t8Z5RbtE/QyJpXS1IiDgz1Rij/bnIq iwqAXKzWgPKcp5UX8Q/8TBIWNy61ug4Y/paxjyMVbGjHkHef/7QX5KbLXLw== Received: from aptaippmta02.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44r5j5ea19-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Feb 2025 08:00:33 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 51D80UWf020811; Thu, 13 Feb 2025 08:00:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 44p0bkxyb4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Feb 2025 08:00:30 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 51D80KWB020786; Thu, 13 Feb 2025 08:00:30 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 51D80T9P020804 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Feb 2025 08:00:30 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 393357) id B957240C04; Thu, 13 Feb 2025 16:00:28 +0800 (CST) From: Ziqi Chen To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com, quic_ziqichen@quicinc.com, quic_nguyenb@quicinc.com, quic_nitirawa@quicinc.com, peter.wang@mediatek.com, quic_rampraka@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, Neil Armstrong , Alim Akhtar , "James E.J. Bottomley" , Stanley Jhu , Manivannan Sadhasivam , Matthias Brugger , AngeloGioacchino Del Regno , Andrew Halaney , Eric Biggers , Minwoo Im , linux-kernel@vger.kernel.org (open list), linux-mediatek@lists.infradead.org (moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support:Keyword:mediatek) Subject: [PATCH v5 1/8] scsi: ufs: core: Pass target_freq to clk_scale_notify() vop Date: Thu, 13 Feb 2025 16:00:01 +0800 Message-Id: <20250213080008.2984807-2-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> References: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: IYpf3aePiYxJI7QI-vCovFBOpBHWOxNb X-Proofpoint-GUID: IYpf3aePiYxJI7QI-vCovFBOpBHWOxNb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_02,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130060 From: Can Guo Instead of only two frequencies, if OPP V2 is used, the UFS devfreq clock scaling may scale the clock among multiple frequencies, so just passing up/down to vop clk_scale_notify() is not enough to cover the intermediate clock freqs between the min and max freqs. Hence pass the target_freq , which will be used in successive commits, to clk_scale_notify() to allow the vop to perform corresponding configurations with regard to the clock freqs. Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Reviewed-by: Bean Huo Reviewed-by: Bart Van Assche Tested-by: Neil Armstrong Reviewed-by: Peter Wang --- v1 -> v2: Modify commit message to make it more clear. v2 -> v3: Change 'vops' to 'vop' in commit message. v4 -> v5: keep the indentation consistent for clk_scale_notify() definition. --- drivers/ufs/core/ufshcd-priv.h | 7 ++++--- drivers/ufs/core/ufshcd.c | 4 ++-- drivers/ufs/host/ufs-mediatek.c | 1 + drivers/ufs/host/ufs-qcom.c | 5 +++-- include/ufs/ufshcd.h | 4 ++-- 5 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index 9ffd94ddf8c7..0549b65f71ed 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -117,11 +117,12 @@ static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba) return ufshcd_readl(hba, REG_UFS_VERSION); } -static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba, - bool up, enum ufs_notify_change_status status) +static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba, bool up, + unsigned long target_freq, + enum ufs_notify_change_status status) { if (hba->vops && hba->vops->clk_scale_notify) - return hba->vops->clk_scale_notify(hba, up, status); + return hba->vops->clk_scale_notify(hba, up, target_freq, status); return 0; } diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index acc3607bbd9c..8d295cc827cc 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -1157,7 +1157,7 @@ static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, int ret = 0; ktime_t start = ktime_get(); - ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); + ret = ufshcd_vops_clk_scale_notify(hba, scale_up, freq, PRE_CHANGE); if (ret) goto out; @@ -1168,7 +1168,7 @@ static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, if (ret) goto out; - ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); + ret = ufshcd_vops_clk_scale_notify(hba, scale_up, freq, POST_CHANGE); if (ret) { if (hba->use_pm_opp) ufshcd_opp_set_rate(hba, diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index 135cd78109e2..977dd0caaef6 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1643,6 +1643,7 @@ static void ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up) } static int ufs_mtk_clk_scale_notify(struct ufs_hba *hba, bool scale_up, + unsigned long target_freq, enum ufs_notify_change_status status) { if (!ufshcd_is_clkscaling_supported(hba)) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 68040b2ab5f8..b6eef975dc46 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1333,8 +1333,9 @@ static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) return ufs_qcom_set_core_clk_ctrl(hba, false); } -static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, - bool scale_up, enum ufs_notify_change_status status) +static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, + unsigned long target_freq, + enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); int err; diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index d7aca9e61684..02802981f07f 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -344,8 +344,8 @@ struct ufs_hba_variant_ops { void (*exit)(struct ufs_hba *); u32 (*get_ufs_hci_version)(struct ufs_hba *); int (*set_dma_mask)(struct ufs_hba *); - int (*clk_scale_notify)(struct ufs_hba *, bool, - enum ufs_notify_change_status); + int (*clk_scale_notify)(struct ufs_hba *, bool, unsigned long, + enum ufs_notify_change_status); int (*setup_clocks)(struct ufs_hba *, bool, enum ufs_notify_change_status); int (*hce_enable_notify)(struct ufs_hba *, From patchwork Thu Feb 13 08:00:02 2025 Content-Type: text/plain; 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Bottomley" , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 2/8] scsi: ufs: qcom: Pass target_freq to clk scale pre and post change Date: Thu, 13 Feb 2025 16:00:02 +0800 Message-Id: <20250213080008.2984807-3-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> References: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: dsxOF_gJseJbsTRIOAIVsdIfbN-B6wxb X-Proofpoint-GUID: dsxOF_gJseJbsTRIOAIVsdIfbN-B6wxb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_02,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 impostorscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130059 From: Can Guo Instead of only two frequencies, if OPP V2 is used, the UFS devfreq clock scaling may scale the clock among multiple frequencies. In the case of scaling up, the devfreq may decide to scale the clock to an intermediate freq based on load, but the clock scale up pre change operation uses settings for the max clock freq unconditionally. Fix it by passing the target_freq to clock scale up pre change so that the correct settings for the target_freq can be used. In the case of scaling down, the clock scale down post change operation is doing fine, because it reads the actual clock rate to tell freq, but to keep symmetry with clock scale up pre change operation, just use the target_freq instead of reading clock rate. Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Reviewed-by: Bean Huo Tested-by: Neil Armstrong Reviewed-by: Peter Wang --- v1 -> v2: 1. Modify commit message to make it more clear. 2. Use common Macro HZ_PER_MHZ in function ufs_qcom_set_core_clk_ctrl(). v2 -> v3: Commit message typo fixed. --- drivers/ufs/host/ufs-qcom.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index b6eef975dc46..a1eb3cab45e4 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -15,6 +15,7 @@ #include #include #include +#include #include @@ -97,7 +98,7 @@ static const struct __ufs_qcom_bw_table { }; static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); -static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up); +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq); static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) { @@ -524,7 +525,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, return -EINVAL; } - err = ufs_qcom_set_core_clk_ctrl(hba, true); + err = ufs_qcom_set_core_clk_ctrl(hba, ULONG_MAX); if (err) dev_err(hba->dev, "cfg core clk ctrl failed\n"); /* @@ -1231,7 +1232,7 @@ static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); } -static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct list_head *head = &hba->clk_list_head; @@ -1245,10 +1246,11 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) !strcmp(clki->name, "core_clk_unipro")) { if (!clki->max_freq) cycles_in_1us = 150; /* default for backwards compatibility */ - else if (is_scale_up) - cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); + else if (freq == ULONG_MAX) + cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); else - cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); + cycles_in_1us = ceil(freq, HZ_PER_MHZ); + break; } } @@ -1285,7 +1287,7 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); } -static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) +static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct ufs_pa_layer_attr *attr = &host->dev_req_params; @@ -1298,7 +1300,7 @@ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) return ret; } /* set unipro core clock attributes and clear clock divider */ - return ufs_qcom_set_core_clk_ctrl(hba, true); + return ufs_qcom_set_core_clk_ctrl(hba, freq); } static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) @@ -1327,10 +1329,10 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) return err; } -static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) +static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq) { /* set unipro core clock attributes and clear clock divider */ - return ufs_qcom_set_core_clk_ctrl(hba, false); + return ufs_qcom_set_core_clk_ctrl(hba, freq); } static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, @@ -1349,7 +1351,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, if (err) return err; if (scale_up) - err = ufs_qcom_clk_scale_up_pre_change(hba); + err = ufs_qcom_clk_scale_up_pre_change(hba, target_freq); else err = ufs_qcom_clk_scale_down_pre_change(hba); @@ -1361,7 +1363,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, if (scale_up) err = ufs_qcom_clk_scale_up_post_change(hba); else - err = ufs_qcom_clk_scale_down_post_change(hba); + err = ufs_qcom_clk_scale_down_post_change(hba, target_freq); if (err) { From patchwork Thu Feb 13 08:00:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziqi Chen X-Patchwork-Id: 13972895 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12C4D20B1F3; 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Bottomley" , Eric Biggers , Minwoo Im , Manivannan Sadhasivam , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 3/8] scsi: ufs: core: Add a vop to map clock frequency to gear speed Date: Thu, 13 Feb 2025 16:00:03 +0800 Message-Id: <20250213080008.2984807-4-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> References: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HRKyK8HIMR_RUdd_RcTB9Ie54v5Uu74m X-Proofpoint-ORIG-GUID: HRKyK8HIMR_RUdd_RcTB9Ie54v5Uu74m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_02,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxscore=0 spamscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130060 From: Can Guo Add a vop to map UFS host controller clock frequencies to the corresponding maximum supported UFS high speed gear speeds. During clock scaling, we can map the target clock frequency, demanded by devfreq, to the maximum supported gear speed, so that devfreq can scale the gear to the highest gear speed supported at the target clock frequency, instead of just scaling up/down the gear between the min and max gear speeds. Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Signed-off-by: Can Guo Reviewed-by: Bean Huo Reviewed-by: Bart Van Assche Tested-by: Neil Armstrong Reviewed-by: Peter Wang --- v2 -> v3: 1. Remove the parameter 'gear' and use it as function return result. 2. Change "vops" into "vop" in commit message. v4 -> v5: 1. keep the indentation consistent for vop freq_to_gear_speed. 2. Change the return value type of vop freq_to_gear_speed from 'int' to 'u32'. --- drivers/ufs/core/ufshcd-priv.h | 8 ++++++++ include/ufs/ufshcd.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index 0549b65f71ed..983b0a8dafb5 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -277,6 +277,14 @@ static inline int ufshcd_mcq_vops_config_esi(struct ufs_hba *hba) return -EOPNOTSUPP; } +static inline u32 ufshcd_vops_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) +{ + if (hba->vops && hba->vops->freq_to_gear_speed) + return hba->vops->freq_to_gear_speed(hba, freq); + + return 0; +} + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; /** diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 02802981f07f..b34301de3cf8 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -336,6 +336,7 @@ struct ufs_pwr_mode_info { * @get_outstanding_cqs: called to get outstanding completion queues * @config_esi: called to config Event Specific Interrupt * @config_scsi_dev: called to configure SCSI device parameters + * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed */ struct ufs_hba_variant_ops { const char *name; @@ -387,6 +388,7 @@ struct ufs_hba_variant_ops { unsigned long *ocqs); int (*config_esi)(struct ufs_hba *hba); void (*config_scsi_dev)(struct scsi_device *sdev); + u32 (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq); }; /* clock gating state */ From patchwork Thu Feb 13 08:00:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziqi Chen X-Patchwork-Id: 13972893 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2545E20C01C; Thu, 13 Feb 2025 08:01:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739433665; cv=none; b=sZpsxXqj9Auu1y20OIJ5hMMa7g/N7dTBsrg4vLqaqu4rlkVVgX6a19TeSMxmD/AKU3lffY8HYKEwf/Nod5JW2ozSZbtTvqpsdSfqpBrkI3oyLR60MMv24uLP5Hr1jKzBT56Z/GXlrC9TgmiihwUWBxYmbuTh1pAdpGIYQbS7Wm4= ARC-Message-Signature: i=1; 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Bottomley" , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 4/8] scsi: ufs: qcom: Implement the freq_to_gear_speed() vop Date: Thu, 13 Feb 2025 16:00:04 +0800 Message-Id: <20250213080008.2984807-5-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> References: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TbvPLulQfvTTBIHtZ5qIMB8DxEK2OpsO X-Proofpoint-GUID: TbvPLulQfvTTBIHtZ5qIMB8DxEK2OpsO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_02,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 malwarescore=0 clxscore=1015 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130060 From: Can Guo Implement the freq_to_gear_speed() vop to map the unipro core clock frequency to the corresponding maximum supported gear speed. Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Reviewed-by: Bean Huo Tested-by: Neil Armstrong Reviewed-by: Peter Wang --- v1 -> v2: Print out freq and gear info as debugging message. v2 -> v3: 1. Change "vops" to "vop" in commit message. 2. Removed variable 'ret' in function ufs_qcom_freq_to_gear_speed(). 3. Removed parameters '*gear' and use gear value as return value for funtion ufs_qcom_freq_to_gear_speed(). v3 -> v4: Change the data type of 'gear' from 'int' to 'u32'. --- drivers/ufs/host/ufs-qcom.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index a1eb3cab45e4..3353acaaa2ae 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1804,6 +1804,36 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba) return ret; } +static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) +{ + u32 gear = 0; + + switch (freq) { + case 403000000: + gear = UFS_HS_G5; + break; + case 300000000: + gear = UFS_HS_G4; + break; + case 201500000: + gear = UFS_HS_G3; + break; + case 150000000: + case 100000000: + gear = UFS_HS_G2; + break; + case 75000000: + case 37500000: + gear = UFS_HS_G1; + break; + default: + dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); + break; + } + + return gear; +} + /* * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations * @@ -1834,6 +1864,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { .op_runtime_config = ufs_qcom_op_runtime_config, .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, .config_esi = ufs_qcom_config_esi, + .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, }; /** From patchwork Thu Feb 13 08:00:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziqi Chen X-Patchwork-Id: 13972896 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A753C20A5E7; Thu, 13 Feb 2025 08:01:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Bottomley" , Manivannan Sadhasivam , Andrew Halaney , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 5/8] scsi: ufs: core: Enable multi-level gear scaling Date: Thu, 13 Feb 2025 16:00:05 +0800 Message-Id: <20250213080008.2984807-6-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> References: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: r7Si0lBAXLtoMoq9bynkoE6lBpgBDzDR X-Proofpoint-ORIG-GUID: r7Si0lBAXLtoMoq9bynkoE6lBpgBDzDR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_02,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130060 From: Can Guo With OPP V2 enabled, devfreq can scale clocks amongst multiple frequency plans. However, the gear speed is only toggled between min and max during clock scaling. Enable multi-level gear scaling by mapping clock frequencies to gear speeds, so that when devfreq scales clock frequencies we can put the UFS link at the appropriate gear speeds accordingly. Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Reviewed-by: Bean Huo Reviewed-by: Bart Van Assche Tested-by: Neil Armstrong Reviewed-by: Peter Wang --- v1 -> v2: Rename the lable "do_pmc" to "config_pwr_mode". v2 -> v3: Use assignment instead memcpy() in function ufshcd_scale_gear(). v3 -> v4: Typo fixed for commit message. v4 -> v5: Change the data type of "new_gear" from 'int' to 'u32'. --- drivers/ufs/core/ufshcd.c | 44 ++++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 8d295cc827cc..9908c0d6a1e1 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -1308,16 +1308,26 @@ static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, /** * ufshcd_scale_gear - scale up/down UFS gear * @hba: per adapter instance + * @target_gear: target gear to scale to * @scale_up: True for scaling up gear and false for scaling down * * Return: 0 for success; -EBUSY if scaling can't happen at this time; * non-zero for any other errors. */ -static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) +static int ufshcd_scale_gear(struct ufs_hba *hba, u32 target_gear, bool scale_up) { int ret = 0; struct ufs_pa_layer_attr new_pwr_info; + if (target_gear) { + new_pwr_info = hba->pwr_info; + new_pwr_info.gear_tx = target_gear; + new_pwr_info.gear_rx = target_gear; + + goto config_pwr_mode; + } + + /* Legacy gear scaling, in case vops_freq_to_gear_speed() is not implemented */ if (scale_up) { memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, sizeof(struct ufs_pa_layer_attr)); @@ -1338,6 +1348,7 @@ static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) } } +config_pwr_mode: /* check if the power mode needs to be changed or not? */ ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); if (ret) @@ -1408,15 +1419,19 @@ static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool sc static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, bool scale_up) { + u32 old_gear = hba->pwr_info.gear_rx; + u32 new_gear = 0; int ret = 0; + new_gear = ufshcd_vops_freq_to_gear_speed(hba, freq); + ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); if (ret) return ret; /* scale down the gear before scaling down clocks */ if (!scale_up) { - ret = ufshcd_scale_gear(hba, false); + ret = ufshcd_scale_gear(hba, new_gear, false); if (ret) goto out_unprepare; } @@ -1424,13 +1439,13 @@ static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, ret = ufshcd_scale_clks(hba, freq, scale_up); if (ret) { if (!scale_up) - ufshcd_scale_gear(hba, true); + ufshcd_scale_gear(hba, old_gear, true); goto out_unprepare; } /* scale up the gear after scaling up clocks */ if (scale_up) { - ret = ufshcd_scale_gear(hba, true); + ret = ufshcd_scale_gear(hba, new_gear, true); if (ret) { ufshcd_scale_clks(hba, hba->devfreq->previous_freq, false); @@ -1723,6 +1738,8 @@ static ssize_t ufshcd_clkscale_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct ufs_hba *hba = dev_get_drvdata(dev); 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Bottomley" , Matthias Brugger , AngeloGioacchino Del Regno , Manivannan Sadhasivam , Andrew Halaney , linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support:Keyword:mediatek), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support:Keyword:mediatek) Subject: [PATCH v5 6/8] scsi: ufs: core: Check if scaling up is required when disable clkscale Date: Thu, 13 Feb 2025 16:00:06 +0800 Message-Id: <20250213080008.2984807-7-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> References: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ng-XFjBtEhVtIG9dXqBhJ1xpozRW7NZx X-Proofpoint-ORIG-GUID: Ng-XFjBtEhVtIG9dXqBhJ1xpozRW7NZx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_02,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxscore=0 spamscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130060 When disabling clkscale via the clkscale_enable sysfs entry, UFS driver shall perform scaling up once regardless. Check if scaling up is required or not first to avoid repetitive work. Signed-off-by: Ziqi Chen Co-developed-by: Can Guo Signed-off-by: Can Guo Reviewed-by: Bart Van Assche Tested-by: Neil Armstrong Reviewed-by: Bean Huo Reviewed-by: Peter Wang --- drivers/ufs/core/ufshcd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 9908c0d6a1e1..727ca930c2ef 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -1770,6 +1770,10 @@ static ssize_t ufshcd_clkscale_enable_store(struct device *dev, freq = clki->max_freq; ufshcd_suspend_clkscaling(hba); + + if (!ufshcd_is_devfreq_scaling_required(hba, freq, true)) + goto out_rel; + err = ufshcd_devfreq_scale(hba, freq, true); if (err) dev_err(hba->dev, "%s: failed to scale clocks up %d\n", From patchwork Thu Feb 13 08:00:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ziqi Chen X-Patchwork-Id: 13972899 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07B0120B807; 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Thu, 13 Feb 2025 08:00:59 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 51D80v1f020926; Thu, 13 Feb 2025 08:00:57 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 44p0bkxycb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Feb 2025 08:00:57 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 51D80uOs020920; Thu, 13 Feb 2025 08:00:56 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 51D80uSV020918 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Feb 2025 08:00:56 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 393357) id 84A9040C04; Thu, 13 Feb 2025 16:00:55 +0800 (CST) From: Ziqi Chen To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com, quic_ziqichen@quicinc.com, quic_nguyenb@quicinc.com, quic_nitirawa@quicinc.com, peter.wang@mediatek.com, quic_rampraka@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, Neil Armstrong , Alim Akhtar , "James E.J. Bottomley" , Matthias Brugger , AngeloGioacchino Del Regno , Manivannan Sadhasivam , Andrew Halaney , Eric Biggers , Minwoo Im , linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support:Keyword:mediatek), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support:Keyword:mediatek) Subject: [PATCH v5 7/8] scsi: ufs: core: Toggle Write Booster during clock scaling base on gear speed Date: Thu, 13 Feb 2025 16:00:07 +0800 Message-Id: <20250213080008.2984807-8-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> References: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: aM9pWxy1_Z6ESXLoG0QYa55UUxTaOM6c X-Proofpoint-GUID: aM9pWxy1_Z6ESXLoG0QYa55UUxTaOM6c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_02,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 malwarescore=0 clxscore=1015 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130060 From: Can Guo During clock scaling, Write Booster is toggled on or off based on whether the clock is scaled up or down. However, with OPP V2 powered multi-level gear scaling, the gear can be scaled amongst multiple gear speeds, e.g., it may scale down from G5 to G4, or from G4 to G2. To provide flexibilities, add a new field for clock scaling such that during clock scaling Write Booster can be enabled or disabled based on gear speeds but not based on scaling up or down. Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Reviewed-by: Bean Huo Tested-by: Neil Armstrong Reviewed-by: Peter Wang --- v1 - > v2: Initialize the local variables "wb_en" as "false". v3 -> v4: 1. Add comment for default initialized wb_gear. 2. Remove the unnecessary variable “wb_en" in function ufshcd_clock_scaling_unprepare(). --- drivers/ufs/core/ufshcd.c | 12 ++++++++---- include/ufs/ufshcd.h | 3 +++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 727ca930c2ef..628bf2aebbeb 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -1393,13 +1393,13 @@ static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) return ret; } -static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) +static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err) { up_write(&hba->clk_scaling_lock); - /* Enable Write Booster if we have scaled up else disable it */ + /* Enable Write Booster if current gear requires it else disable it */ if (ufshcd_enable_wb_if_scaling_up(hba) && !err) - ufshcd_wb_toggle(hba, scale_up); + ufshcd_wb_toggle(hba, hba->pwr_info.gear_rx >= hba->clk_scaling.wb_gear); mutex_unlock(&hba->wb_mutex); @@ -1454,7 +1454,7 @@ static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, } out_unprepare: - ufshcd_clock_scaling_unprepare(hba, ret, scale_up); + ufshcd_clock_scaling_unprepare(hba, ret); return ret; } @@ -1814,6 +1814,10 @@ static void ufshcd_init_clk_scaling(struct ufs_hba *hba) if (!hba->clk_scaling.min_gear) hba->clk_scaling.min_gear = UFS_HS_G1; + if (!hba->clk_scaling.wb_gear) + /* Use intermediate gear speed HS_G3 as the default wb_gear */ + hba->clk_scaling.wb_gear = UFS_HS_G3; + INIT_WORK(&hba->clk_scaling.suspend_work, ufshcd_clk_scaling_suspend_work); INIT_WORK(&hba->clk_scaling.resume_work, diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index b34301de3cf8..6633c1a1c224 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -447,6 +447,8 @@ struct ufs_clk_gating { * @resume_work: worker to resume devfreq * @target_freq: frequency requested by devfreq framework * @min_gear: lowest HS gear to scale down to + * @wb_gear: enable Write Booster when HS gear scales above or equal to it, else + * disable Write Booster * @is_enabled: tracks if scaling is currently enabled or not, controlled by * clkscale_enable sysfs node * @is_allowed: tracks if scaling is currently allowed or not, used to block @@ -467,6 +469,7 @@ struct ufs_clk_scaling { struct work_struct resume_work; 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Thu, 13 Feb 2025 08:00:59 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 44p0bkyak7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Feb 2025 08:00:59 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 51D80xIq032213; Thu, 13 Feb 2025 08:00:59 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 51D80wKI032212 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Feb 2025 08:00:59 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 393357) id F016840C04; Thu, 13 Feb 2025 16:00:57 +0800 (CST) From: Ziqi Chen To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com, quic_ziqichen@quicinc.com, quic_nguyenb@quicinc.com, quic_nitirawa@quicinc.com, peter.wang@mediatek.com, quic_rampraka@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, Keoseong Park , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 8/8] ABI: sysfs-driver-ufs: Add missing UFS sysfs attributes Date: Thu, 13 Feb 2025 16:00:08 +0800 Message-Id: <20250213080008.2984807-9-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> References: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ltfJGUWqJY3Ek81kOMh5sfRhD7Km-p8n X-Proofpoint-ORIG-GUID: ltfJGUWqJY3Ek81kOMh5sfRhD7Km-p8n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_02,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 phishscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130060 Add UFS driver sysfs attributes clkscale_enable, clkgate_enable and clkgate_delay_ms to this document. Signed-off-by: Ziqi Chen Reviewed-by: Bean Huo --- v1 -> v2: It is a new patch be added to this series since v2. v2 -> v3: 1. Typo fixed for commit message. 2. Improve the grammar of attributes' descriptions. V3 -> v4: The use of words is more standardized. --- Documentation/ABI/testing/sysfs-driver-ufs | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs index 5fa6655aee84..da8d1437d3f4 100644 --- a/Documentation/ABI/testing/sysfs-driver-ufs +++ b/Documentation/ABI/testing/sysfs-driver-ufs @@ -1559,3 +1559,36 @@ Description: Symbol - HCMID. This file shows the UFSHCD manufacturer id. The Manufacturer ID is defined by JEDEC in JEDEC-JEP106. The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/clkscale_enable +What: /sys/bus/platform/devices/*.ufs/clkscale_enable +Date: January 2025 +Contact: Ziqi Chen +Description: + This attribute shows whether the UFS clock scaling is enabled or not. + And it can be used to enable/disable the clock scaling by writing + 1 or 0 to this attribute. + + The attribute is read/write. + +What: /sys/bus/platform/drivers/ufshcd/*/clkgate_enable +What: /sys/bus/platform/devices/*.ufs/clkgate_enable +Date: January 2025 +Contact: Ziqi Chen +Description: + This attribute shows whether the UFS clock gating is enabled or not. + And it can be used to enable/disable the clock gating by writing + 1 or 0 to this attribute. + + The attribute is read/write. + +What: /sys/bus/platform/drivers/ufshcd/*/clkgate_delay_ms +What: /sys/bus/platform/devices/*.ufs/clkgate_delay_ms +Date: January 2025 +Contact: Ziqi Chen +Description: + This attribute shows and sets the number of milliseconds of idle time + before the UFS driver starts to perform clock gating. This can + prevent the UFS from frequently performing clock gating/ungating. + + The attribute is read/write.