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Thu, 13 Feb 2025 12:41:04 -0800 (PST) From: Denzeel Oliva To: andi.shyti@kernel.org, broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Denzeel Oliva Subject: [PATCH v2 1/2] spi: dt-bindings: samsung: add samsung,exynos990-spi compatible Date: Thu, 13 Feb 2025 20:40:43 +0000 Message-Id: <20250213204044.660-2-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213204044.660-1-wachiturroxd150@gmail.com> References: <20250213204044.660-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250213_124106_435126_0CAB10AB X-CRM114-Status: UNSURE ( 9.43 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add "samsung,exynos990-spi" dedicated compatible for the SPI controller on Exynos990 SoC. This ensures proper representation of the hardware in the device tree. Signed-off-by: Denzeel Oliva Reviewed-by: Sam Protsenko --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index 3c206a64d..1d3c95bd2 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -24,6 +24,7 @@ properties: - samsung,exynos4210-spi - samsung,exynos5433-spi - samsung,exynos850-spi + - samsung,exynos990-spi - samsung,exynosautov9-spi - tesla,fsd-spi - items: From patchwork Thu Feb 13 20:40:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13974025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E46FC021A6 for ; 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Thu, 13 Feb 2025 12:41:09 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5207aa40088sm285572e0c.10.2025.02.13.12.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 12:41:08 -0800 (PST) From: Denzeel Oliva To: andi.shyti@kernel.org, broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Denzeel Oliva Subject: [PATCH v2 2/2] spi: s3c64xx: add support exynos990-spi to new port config data Date: Thu, 13 Feb 2025 20:40:44 +0000 Message-Id: <20250213204044.660-3-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213204044.660-1-wachiturroxd150@gmail.com> References: <20250213204044.660-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250213_124110_180646_667D4871 X-CRM114-Status: GOOD ( 16.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Exynos990 uses the same version of USI SPI (v2.1) as the GS101. Removed fifo_lvl_mask and rx_lvl_offset, and changed to the new data configuration port. The difference from other new port configuration data is that fifo_depth is only specified in fifo-depth in DT. Exynos 990 data for SPI: - The depth of the FIFO is not the same size on all nodes. A depth of 64 bytes is used on most nodes, while a depth of 256 bytes is used on 3 specific nodes (SPI 8/9/10). - The Exynos 990 only allows access to 32-bit registers. If access is attempted with a different size, an error interrupt is generated. Therefore, it is necessary to perform write accesses to registers in 32-bit blocks. - To prevent potential issues when fifo-depth is not explicitly set in DT, a default value of 64 is assigned to ensure stable operation. Signed-off-by: Denzeel Oliva --- drivers/spi/spi-s3c64xx.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 389275dbc..5f55763f9 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1586,6 +1586,20 @@ static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config exynos990_spi_port_config = { + /* If not specified in DT, defaults to 64 */ + .fifo_depth = 64, + .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, + .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .use_32bit_io = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, @@ -1664,6 +1678,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { { .compatible = "samsung,exynos850-spi", .data = &exynos850_spi_port_config, }, + { .compatible = "samsung,exynos990-spi", + .data = &exynos990_spi_port_config, + }, { .compatible = "samsung,exynosautov9-spi", .data = &exynosautov9_spi_port_config, },