From patchwork Fri Feb 14 14:19:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13974997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41DE9C02198 for ; Fri, 14 Feb 2025 14:19:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D34D210ECAB; Fri, 14 Feb 2025 14:19:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aFN/cW5L"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0825810ECA6; Fri, 14 Feb 2025 14:19:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739542744; x=1771078744; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=msQYmafI/c0c6tU2qwhGKbFDzHpUJGVMCjEFwmmEiI8=; b=aFN/cW5L91AUjv4ZuDL1DxrRY3EIDM4sVDnDLC9/jB4yd0PTgZdgFArU ZWrAPMPzjzKwaL3pM04Ju9PTLcGxCyfu9zmKLE+idccGshiU5hyF1lU7u 3CUomNv63zGFSxnYhh4FYtKuzAY0mQwuKJgG8C8WXClKkq0SEkSjnPClE IRyAm55DG3fVYXyzsd9mfzWlQuNDFw4/UuRrpu2ZrHIQIKhX3BJ+4TTbQ vA390q2x9wWiBiTsk2zB4DajMceCQQjiAJWVuDRti3rIG9XTHlL4mL3dR A1MNcrNU81C39ilz3K5KqfNeCR5tdSGYhnubppNlWMQokdo0HaYirFZwg Q==; X-CSE-ConnectionGUID: G1Mr9xf4QT2e10zdC/LaxQ== X-CSE-MsgGUID: /WL2WczHS+uX3F21TBa5/A== X-IronPort-AV: E=McAfee;i="6700,10204,11345"; a="27892492" X-IronPort-AV: E=Sophos;i="6.13,286,1732608000"; d="scan'208";a="27892492" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:04 -0800 X-CSE-ConnectionGUID: kd6ijtDeQ2KhA1x0gJz80w== X-CSE-MsgGUID: RffigLOiSlCGZ+/NzdxFpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="136694225" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:02 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: stable@vger.kernel.org, Jani Nikula Subject: [PATCH v2 01/11] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro Date: Fri, 14 Feb 2025 16:19:51 +0200 Message-ID: <20250214142001.552916-2-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The format of the port width field in the DDI_BUF_CTL and the TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the x3 lane mode for HDMI FRL has a different encoding in the two registers. To account for this use the TRANS_DDI_FUNC_CTL's own port width macro. Cc: # v6.5+ Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI") Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 9600c2a346d4c..5d3d54922d629 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -805,8 +805,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, /* select data lane width */ tmp = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans)); - tmp &= ~DDI_PORT_WIDTH_MASK; - tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); + tmp &= ~TRANS_DDI_PORT_WIDTH_MASK; + tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); /* select input pipe */ tmp &= ~TRANS_DDI_EDP_INPUT_MASK; From patchwork Fri Feb 14 14:19:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13974996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7A9FC021A9 for ; Fri, 14 Feb 2025 14:19:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5AA8F10ECA9; Fri, 14 Feb 2025 14:19:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MLgskclv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97D1910ECA9; Fri, 14 Feb 2025 14:19:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739542746; x=1771078746; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8aOrwWx4Z/wQIBdiIqNxIrebV6N3+rO90d7LtuuH6pA=; b=MLgskclvklh0Vx9JFMK4yJFyblLl+gKTeaDPJkMeGFgPEyBd5R3MtE0T 9Yu/YU43NLNTiLfNcSE5njzFSHKluEoSTp+h1RqzpMMdUNBVIatrnfEs+ BVnOW3WnVItf/5AW887kj+eSWm9PwkjOEJVRZ5jhfh0wy3U4NIKzme1DY bbBfTrpvmvUV1S8c8D7j4Z9VA9BlksubtpaRLttyrO5AcYxCtFoZ/JsyC lSBJtRjNU0Bw9H8wG3zE41bT7nAOyRDDaxsK+xZOB60MhSDDNDgy932Cu lE2NMMNeFtU9zZWBypAPJyCU0AfuIDu8ig7bgYsQDC4+k96pmQbBvA23q g==; X-CSE-ConnectionGUID: wZr91KPqSAKr86VuLADykw== X-CSE-MsgGUID: uVgcQILSRiulX9Q3SRga3Q== X-IronPort-AV: E=McAfee;i="6700,10204,11345"; a="27892497" X-IronPort-AV: E=Sophos;i="6.13,286,1732608000"; d="scan'208";a="27892497" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:06 -0800 X-CSE-ConnectionGUID: TsH9+hTDR4eOVeHKPLcKIA== X-CSE-MsgGUID: S4zkhH13S4OZppsHDtb+KA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="136694241" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:04 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: stable@vger.kernel.org, Jani Nikula Subject: [PATCH v2 02/11] drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL Date: Fri, 14 Feb 2025 16:19:52 +0200 Message-ID: <20250214142001.552916-3-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Fix the port width programming in the DDI_BUF_CTL register on MTLP+, where this had an off-by-one error. Cc: # v6.5+ Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI") Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5433279227e18..5ef7857a893f8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3511,7 +3511,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); - buf_ctl |= DDI_PORT_WIDTH(lane_count); + buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); if (DISPLAY_VER(dev_priv) >= 20) buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 670cd2371f947..3eea191f20175 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3639,7 +3639,7 @@ enum skl_power_gate { #define DDI_BUF_IS_IDLE (1 << 7) #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) #define DDI_A_4_LANES (1 << 4) -#define DDI_PORT_WIDTH(width) (((width) - 1) << 1) +#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 : ((width) - 1)) << 1) #define DDI_PORT_WIDTH_MASK (7 << 1) #define DDI_PORT_WIDTH_SHIFT 1 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) From patchwork Fri Feb 14 14:19:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13974999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88944C021A7 for ; Fri, 14 Feb 2025 14:19:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E56610ECB3; Fri, 14 Feb 2025 14:19:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ZVBE5WGU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id F327210ECAA; Fri, 14 Feb 2025 14:19:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739542747; x=1771078747; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=imQR34fiGDTOkcgHMJG9BwFmIqw4EBsIZwKYYT6z6rE=; b=ZVBE5WGUzFrL1HaAjQegkh3dkbdsCn1py3EGYIA6EZiwZIeY/pnFCUMC +bjGjF5/Q/4mqpZnvaugJ47WFXIUKiRItQfS0nm+DHfvUe3/235cZ6Ufx 6rCu/A36SQ+gVhKGl+mqI/mVpuyEmp/+j6jL/cLzvkmwXyKK71LYWhfeH FRX6nol7aMB0R0jeHnBwK0wPxslImUFAICUEPf4jBd0rh/AdwlxCEbMXY FWgkHlv/3NvlS58k9Mp293684jULB8d3yUNr8eezYaYhc5HVW7jbPLS7e 7BU2grMJAlQuOE/Nq1RkizlmNsdTLMF46a0mSUY9fJ0Q6JYktwNO5R2Bg Q==; X-CSE-ConnectionGUID: BeCwnJ7gQYGDAdEEEflcOA== X-CSE-MsgGUID: /rqD0doAQfq1b362aHAlCw== X-IronPort-AV: E=McAfee;i="6700,10204,11345"; a="27892498" X-IronPort-AV: E=Sophos;i="6.13,286,1732608000"; d="scan'208";a="27892498" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:07 -0800 X-CSE-ConnectionGUID: MhjEodZOSeKN+Gin1mpXFg== X-CSE-MsgGUID: ca8cE2X5RAKzvFIhvexdVw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="136694248" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:05 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 03/11] drm/i915/ddi: Make all the PORT_WIDTH macros work the same way Date: Fri, 14 Feb 2025 16:19:53 +0200 Message-ID: <20250214142001.552916-4-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make the PORT_WIDTH macro of the XELPDP_PORT_CTL1 register work the same way as those used for the DDI_BUF_CTL and the TRANS_DDI_FUNC_CTL registers: accept a width parameter and convert it to the given register's encoding. v2: Robustify macro calls with parens. (Jani) Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 ++- drivers/gpu/drm/i915/display/intel_ddi.c | 22 ++----------------- 2 files changed, 4 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index 4a3cf08007e31..960f7f778fb81 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -110,7 +110,8 @@ #define XELPDP_TCSS_POWER_REQUEST REG_BIT(5) #define XELPDP_TCSS_POWER_STATE REG_BIT(4) #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1) -#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val) +#define XELPDP_PORT_WIDTH(width) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \ + ((width) == 3 ? 4 : (width) - 1)) #define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ _XELPDP_PORT_BUF_CTL1_LN0_A, \ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5ef7857a893f8..a09363e5dc148 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2525,23 +2525,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) OVERLAP_PIXELS_MASK, dss1); } -static u8 mtl_get_port_width(u8 lane_count) -{ - switch (lane_count) { - case 1: - return 0; - case 2: - return 1; - case 3: - return 4; - case 4: - return 3; - default: - MISSING_CASE(lane_count); - return 4; - } -} - static void mtl_ddi_enable_d2d(struct intel_encoder *encoder) { @@ -2575,7 +2558,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, enum port port = encoder->port; u32 val = 0; - val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); + val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); if (intel_dp_is_uhbr(crtc_state)) val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; @@ -3500,10 +3483,9 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, buf_ctl |= DDI_A_4_LANES; if (DISPLAY_VER(dev_priv) >= 14) { - u8 lane_count = mtl_get_port_width(crtc_state->lane_count); u32 port_buf = 0; - port_buf |= XELPDP_PORT_WIDTH(lane_count); + port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); if (dig_port->lane_reversal) port_buf |= XELPDP_PORT_REVERSAL; From patchwork Fri Feb 14 14:19:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13975000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 392DCC02198 for ; Fri, 14 Feb 2025 14:19:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6473110ECB4; Fri, 14 Feb 2025 14:19:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="j+zBldrb"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 595BC10ECAA; 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14 Feb 2025 06:19:08 -0800 X-CSE-ConnectionGUID: 2p/Q6HZzS3aVYQuSFU2YWQ== X-CSE-MsgGUID: Q6FrR5hBSAq2T7lB3ADahw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="136694253" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:07 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 04/11] drm/i915/ddi: Set missing TC DP PHY lane stagger delay in DDI_BUF_CTL Date: Fri, 14 Feb 2025 16:19:54 +0200 Message-ID: <20250214142001.552916-5-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the missing PHY lane stagger delay programming for ICL-ADL platforms on TypeC DP outputs. v2: (Jani) - Clarify code comment about lane stagger programming. - Robustify macro calls with parens. Bspec: 7534, 49533 Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 29 ++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a09363e5dc148..1e7ae93340ff4 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -328,9 +328,32 @@ static u32 ddi_buf_phy_link_rate(int port_clock) } } +static int dp_phy_lane_stagger_delay(int port_clock) +{ + /* + * Return the number of symbol clocks delay used to stagger the + * assertion/desassertion of the port lane enables. The target delay + * time is 100 ns or greater, return the number of symbols specific to + * the provided port_clock (aka link clock) corresponding to this delay + * time, i.e. so that + * + * number_of_symbols * duration_of_one_symbol >= 100 ns + * + * The delay must be applied only on TypeC DP outputs, for everything else + * the delay must be set to 0. + * + * Return the number of link symbols per 100 ns: + * port_clock (10 kHz) -> bits / 100 us + * / symbol_size -> symbols / 100 us + * / 1000 -> symbols / 100 ns + */ + return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); +} + static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -356,6 +379,12 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, if (!intel_tc_port_in_tbt_alt_mode(dig_port)) intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } + + if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { + int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); + + intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); + } } static int icl_calc_tbt_pll_link(struct intel_display *display, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3eea191f20175..50efaab3b5536 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3636,6 +3636,9 @@ enum skl_power_gate { #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) #define DDI_BUF_PORT_REVERSAL (1 << 16) +#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8) +#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \ + (symbols)) #define DDI_BUF_IS_IDLE (1 << 7) #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) #define DDI_A_4_LANES (1 << 4) From patchwork Fri Feb 14 14:19:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13974998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB0F1C021A4 for ; Fri, 14 Feb 2025 14:19:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 607D610ECB2; Fri, 14 Feb 2025 14:19:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="E+ucpwIm"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id B409710ECAD; Fri, 14 Feb 2025 14:19:09 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="136694260" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:08 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 05/11] drm/i915/ddi: Simplify the port enabling via DDI_BUF_CTL Date: Fri, 14 Feb 2025 16:19:55 +0200 Message-ID: <20250214142001.552916-6-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In the past intel_digital_port::dp.prepare_link_retrain() could be called directly (vs. from a modeset) to retrain an enabled link. In that case the port had to be first disabled and then re-enabled. That changed with commit 2885d283cce5 ("drm/i915/dp: Retrain SST links via a modeset commit"), after which the only way prepare_link_retrain() can be called is from a modeset during link training when the port is still disabled. Simplify things accordingly, assuming the disabled port state. v2: Don't use drm_i915_private in intel_ddi_prepare_link_retrain(). (Jani) Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 24 +++++------------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 1e7ae93340ff4..68c93071720ec 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3765,8 +3765,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, * necessary disable and enable port */ dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); - if (dp_tp_ctl & DP_TP_CTL_ENABLE) - mtl_disable_ddi_buf(encoder, crtc_state); + + drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; @@ -3805,30 +3805,16 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - u32 dp_tp_ctl, ddi_buf_ctl; - bool wait = false; + u32 dp_tp_ctl; dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); - if (dp_tp_ctl & DP_TP_CTL_ENABLE) { - ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); - if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { - intel_de_write(dev_priv, DDI_BUF_CTL(port), - ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); - wait = true; - } - - dp_tp_ctl &= ~DP_TP_CTL_ENABLE; - intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); - intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); - - if (wait) - intel_wait_ddi_buf_idle(dev_priv, port); - } + drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || From patchwork Fri Feb 14 14:19:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13975001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D58E5C021A6 for ; Fri, 14 Feb 2025 14:19:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9369E10ECB7; Fri, 14 Feb 2025 14:19:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WHnBVUFj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2010F10ECB2; Fri, 14 Feb 2025 14:19:11 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="136694273" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:09 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 06/11] drm/i915/ddi: Simplify the port disabling via DDI_BUF_CTL Date: Fri, 14 Feb 2025 16:19:56 +0200 Message-ID: <20250214142001.552916-7-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A port can be disabled only via a modeset (or during HW state sanitization) when the port is enabled. Thus it's not required to check the port's enabled state before disabling it. In any case if the port happened to be disabled, the following disabling would be just a nop and waiting for the buffer's idle state should succeed. Simplify the disabling sequence accordingly. Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 68c93071720ec..1badbf207e529 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3081,17 +3081,12 @@ static void mtl_disable_ddi_buf(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - u32 val; /* 3.b Clear DDI_CTL_DE Enable to 0. */ - val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); - if (val & DDI_BUF_CTL_ENABLE) { - val &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), val); + intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); - /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ - mtl_wait_ddi_buf_idle(dev_priv, port); - } + /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ + mtl_wait_ddi_buf_idle(dev_priv, port); /* 3.d Disable D2D Link */ mtl_ddi_disable_d2d_link(encoder); @@ -3108,15 +3103,8 @@ static void disable_ddi_buf(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - bool wait = false; - u32 val; - val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); - if (val & DDI_BUF_CTL_ENABLE) { - val &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), val); - wait = true; - } + intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); if (intel_crtc_has_dp_encoder(crtc_state)) intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), @@ -3124,8 +3112,7 @@ static void disable_ddi_buf(struct intel_encoder *encoder, intel_ddi_disable_fec(encoder, crtc_state); - if (wait) - intel_wait_ddi_buf_idle(dev_priv, port); + intel_wait_ddi_buf_idle(dev_priv, port); } static void intel_disable_ddi_buf(struct intel_encoder *encoder, From patchwork Fri Feb 14 14:19:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13975002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A0C1C021A9 for ; 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X-CSE-ConnectionGUID: aDDAuvYsS6CyRpJcxoOORA== X-CSE-MsgGUID: tOQg3sp+RvaQ7KcuVq6lLw== X-IronPort-AV: E=McAfee;i="6700,10204,11345"; a="27892504" X-IronPort-AV: E=Sophos;i="6.13,286,1732608000"; d="scan'208";a="27892504" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:13 -0800 X-CSE-ConnectionGUID: 4WfzXhTgRbyF20BJl5u+MQ== X-CSE-MsgGUID: O2whzwCuRoO/47fWxjF7Dw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="136694295" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:11 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula , Mika Kahola Subject: [PATCH v2 07/11] drm/i915/ddi: Simplify waiting for a port to get active/idle via DDI_BUF_CTL Date: Fri, 14 Feb 2025 16:19:57 +0200 Message-ID: <20250214142001.552916-8-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" When waiting for a port to get active/idle there is no point in the complexity of specifying an exact timeout and for that the suitable wait API instead of just using the maximum timeout. The sequence in particular is not performance critical at all either and due to scheduling it's not guaranteed anyhow how long the wait will last at the given timescale. In the usual case where the wait succeeds the actual time waited does not change with the increased timeout. Simplify things accordingly, describing the bspec platform specific timeouts in code comments. v2: Clarify the rationale in the commit log. (Jani) Cc: Jani Nikula Reviewed-by: Mika Kahola Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 78 +++++++++++------------- 1 file changed, 36 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 1badbf207e529..22eeaabc0d2de 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -177,69 +177,63 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, trans->entries[level].hsw.trans2); } -static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) +static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) { - int ret; + struct drm_i915_private *i915 = to_i915(display->drm); - /* FIXME: find out why Bspec's 100us timeout is too short */ - ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & - XELPDP_PORT_BUF_PHY_IDLE), 10000); - if (ret) - drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", - port_name(port)); + if (DISPLAY_VER(display) >= 14) + return XELPDP_PORT_BUF_CTL1(i915, port); + else + return DDI_BUF_CTL(port); } void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, enum port port) { - if (IS_BROXTON(dev_priv)) { + struct intel_display *display = &dev_priv->display; + + /* + * Bspec's platform specific timeouts: + * MTL+ : 100 us + * BXT : fixed 16 us + * HSW-ADL: 8 us + * + * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short + */ + if (display->platform.broxton) { udelay(16); return; } - if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & - DDI_BUF_IS_IDLE), 8)) - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", + static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); + if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), + DDI_BUF_IS_IDLE, 10)) + drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", port_name(port)); } static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - int timeout_us; - int ret; - /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ - if (DISPLAY_VER(dev_priv) < 10) { + /* + * Bspec's platform specific timeouts: + * MTL+ : 10000 us + * DG2 : 1200 us + * TGL-ADL combo PHY: 1000 us + * TGL-ADL TypeC PHY: 3000 us + * HSW-ICL : fixed 518 us + */ + if (DISPLAY_VER(display) < 10) { usleep_range(518, 1000); return; } - if (DISPLAY_VER(dev_priv) >= 14) { - timeout_us = 10000; - } else if (IS_DG2(dev_priv)) { - timeout_us = 1200; - } else if (DISPLAY_VER(dev_priv) >= 12) { - if (intel_encoder_is_tc(encoder)) - timeout_us = 3000; - else - timeout_us = 1000; - } else { - timeout_us = 500; - } - - if (DISPLAY_VER(dev_priv) >= 14) - ret = _wait_for(!(intel_de_read(dev_priv, - XELPDP_PORT_BUF_CTL1(dev_priv, port)) & - XELPDP_PORT_BUF_PHY_IDLE), - timeout_us, 10, 10); - else - ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), - timeout_us, 10, 10); - - if (ret) - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", + static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); + if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), + DDI_BUF_IS_IDLE, 10)) + drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", port_name(port)); } @@ -3086,7 +3080,7 @@ static void mtl_disable_ddi_buf(struct intel_encoder *encoder, intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ - mtl_wait_ddi_buf_idle(dev_priv, port); + intel_wait_ddi_buf_idle(dev_priv, port); /* 3.d Disable D2D Link */ mtl_ddi_disable_d2d_link(encoder); From patchwork Fri Feb 14 14:19:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13975004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD761C021A6 for ; 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X-CSE-ConnectionGUID: tFRzi0uAQmCwZFzy0Hsx5w== X-CSE-MsgGUID: c5vowx7JQ4uruBswkcB7jg== X-IronPort-AV: E=McAfee;i="6700,10204,11345"; a="27892513" X-IronPort-AV: E=Sophos;i="6.13,286,1732608000"; d="scan'208";a="27892513" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:21 -0800 X-CSE-ConnectionGUID: o88p05+GSFmS7sey6BQtYg== X-CSE-MsgGUID: CyoQLpR2Seu/+REB+lWOpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="136694316" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:12 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 08/11] drm/i915/ddi: Move platform checks within mtl_ddi_enable/disable_d2d_link() Date: Fri, 14 Feb 2025 16:19:58 +0200 Message-ID: <20250214142001.552916-9-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The prefix of the mtl_ddi_enable_d2d() / mtl_ddi_disable_d2d_link() names show already what are the relevant platforms, so the corresponding platform check is a detail that can be hidden in the functions, do so. While at it rename mtl_ddi_disable_d2d_link() to mtl_ddi_disable_d2d() for symmetry with mtl_ddi_enable_d2d(). v2: s/mtl_ddi_disable_d2d_link/mtl_ddi_disable_d2d (Jani) Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 22eeaabc0d2de..0cb6c95315fcd 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2556,6 +2556,9 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder) i915_reg_t reg; u32 set_bits, wait_bits; + if (DISPLAY_VER(dev_priv) < 14) + return; + if (DISPLAY_VER(dev_priv) >= 20) { reg = DDI_BUF_CTL(port); set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; @@ -3047,13 +3050,16 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, } static void -mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) +mtl_ddi_disable_d2d(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; i915_reg_t reg; u32 clr_bits, wait_bits; + if (DISPLAY_VER(dev_priv) < 14) + return; + if (DISPLAY_VER(dev_priv) >= 20) { reg = DDI_BUF_CTL(port); clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; @@ -3083,7 +3089,7 @@ static void mtl_disable_ddi_buf(struct intel_encoder *encoder, intel_wait_ddi_buf_idle(dev_priv, port); /* 3.d Disable D2D Link */ - mtl_ddi_disable_d2d_link(encoder); + mtl_ddi_disable_d2d(encoder); /* 3.e Disable DP_TP_CTL */ if (intel_crtc_has_dp_encoder(crtc_state)) { @@ -3432,8 +3438,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); /* e. Enable D2D Link for C10/C20 Phy */ - if (DISPLAY_VER(dev_priv) >= 14) - mtl_ddi_enable_d2d(encoder); + mtl_ddi_enable_d2d(encoder); encoder->set_signal_levels(encoder, crtc_state); From patchwork Fri Feb 14 14:19:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13975003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1975BC02198 for ; Fri, 14 Feb 2025 14:19:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B862410ECB9; Fri, 14 Feb 2025 14:19:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="i9NqIgnE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 540D610ECB5; Fri, 14 Feb 2025 14:19:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739542761; x=1771078761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tST1jQX2NtRDEUx6L5N+Qm9ut6P+m8C1Pjukfdxuqtw=; b=i9NqIgnE6Fh/I8m39+366qQmwr8317VE2028Nm3imOYR3/yWpEnmW2U2 zwC5BSDtPCncJyXGA7W3I7/ACspGQx79ntDmfSyYqACroU+LQKQriCDst WSX4dlYpgsaytrJ/canfWkNRKCv6SAFAP1sgoM6y3Az8Ey7RnbDyLjgTl 9stsjmPcyGW5xFnAXiVhEFP4F0arkPDM2BjWIb5//EA6F472APeXjdyLX Vzq6GxbSc21xEPhA9alf6Icf4kd/moiEn9uJJ3Z1M/jblAW/TVyLHXqbX oGQakDZooeeknQ0emXJa++qg4HAm1p29KkgEUeHgKYPrhGizp11g+UtlN w==; X-CSE-ConnectionGUID: HefWbE0IQm6RE3YV1MM4lw== X-CSE-MsgGUID: fLVSZ8F+QgWEjSxVlw03iw== X-IronPort-AV: E=McAfee;i="6700,10204,11345"; a="27892515" X-IronPort-AV: E=Sophos;i="6.13,286,1732608000"; d="scan'208";a="27892515" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:21 -0800 X-CSE-ConnectionGUID: GKVzyuPHSXyIq3kCva1HZw== X-CSE-MsgGUID: HfOeRbNYStOo6KuVmAZZKw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="136694380" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:16 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 09/11] drm/i915/ddi: Unify the platform specific functions disabling a port Date: Fri, 14 Feb 2025 16:19:59 +0200 Message-ID: <20250214142001.552916-10-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The functions disabling a port for MTL+ and earlier platforms only differ by an extra step on MTL+ (to disable the D2D link) and the point at which the port's idle state is waited for. Combine the two functions accounting for the above differences, removing the duplication. Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++-------------------- 1 file changed, 7 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 0cb6c95315fcd..56094a33b0c4a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3076,58 +3076,29 @@ mtl_ddi_disable_d2d(struct intel_encoder *encoder) port_name(port)); } -static void mtl_disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void intel_disable_ddi_buf(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - /* 3.b Clear DDI_CTL_DE Enable to 0. */ intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); - /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ - intel_wait_ddi_buf_idle(dev_priv, port); + if (DISPLAY_VER(display) >= 14) + intel_wait_ddi_buf_idle(dev_priv, port); - /* 3.d Disable D2D Link */ mtl_ddi_disable_d2d(encoder); - /* 3.e Disable DP_TP_CTL */ if (intel_crtc_has_dp_encoder(crtc_state)) { intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_ENABLE, 0); } -} - -static void disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - - intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); - - if (intel_crtc_has_dp_encoder(crtc_state)) - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), - DP_TP_CTL_ENABLE, 0); intel_ddi_disable_fec(encoder, crtc_state); - intel_wait_ddi_buf_idle(dev_priv, port); -} - -static void intel_disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (DISPLAY_VER(dev_priv) >= 14) { - mtl_disable_ddi_buf(encoder, crtc_state); - - /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ - intel_ddi_disable_fec(encoder, crtc_state); - } else { - disable_ddi_buf(encoder, crtc_state); - } + if (DISPLAY_VER(display) < 14) + intel_wait_ddi_buf_idle(dev_priv, port); intel_ddi_wait_for_fec_status(encoder, crtc_state, false); } From patchwork Fri Feb 14 14:20:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13975005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27B0EC021A7 for ; Fri, 14 Feb 2025 14:19:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 99A3110ECAF; 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X-CSE-ConnectionGUID: MFX7KqjXTrm/1mcOinrHDw== X-CSE-MsgGUID: cAeXkEpCQGyFZWMLJ9Gs5w== X-IronPort-AV: E=McAfee;i="6700,10204,11345"; a="27892516" X-IronPort-AV: E=Sophos;i="6.13,286,1732608000"; d="scan'208";a="27892516" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:21 -0800 X-CSE-ConnectionGUID: PPLJKzYpTRi+FeHaZwMXhg== X-CSE-MsgGUID: IAmuMyz/QqqUu25vu7qviA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="136694383" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:17 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 10/11] drm/i915/ddi: Add a helper to enable a port Date: Fri, 14 Feb 2025 16:20:00 +0200 Message-ID: <20250214142001.552916-11-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a helper to enable a port instead of open-coding it. While at it rename intel_disable_ddi_buf() to intel_ddi_buf_disable() for consistency. v2: (Jani) - s/intel_enable_ddi_buf/intel_ddi_buf_enable - s/intel_disable_ddi_buf/intel_ddi_buf_disable Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 40 +++++++++++------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 56094a33b0c4a..5082f38b0a02e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3076,7 +3076,18 @@ mtl_ddi_disable_d2d(struct intel_encoder *encoder) port_name(port)); } -static void intel_disable_ddi_buf(struct intel_encoder *encoder, +static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) +{ + struct intel_display *display = to_intel_display(encoder); + enum port port = encoder->port; + + intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); + intel_de_posting_read(display, DDI_BUF_CTL(port)); + + intel_wait_ddi_buf_active(encoder); +} + +static void intel_ddi_buf_disable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); @@ -3140,7 +3151,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_transcoder_clock(old_crtc_state); } - intel_disable_ddi_buf(encoder, old_crtc_state); + intel_ddi_buf_disable(encoder, old_crtc_state); intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); @@ -3189,7 +3200,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) < 12) intel_ddi_disable_transcoder_clock(old_crtc_state); - intel_disable_ddi_buf(encoder, old_crtc_state); + intel_ddi_buf_disable(encoder, old_crtc_state); if (DISPLAY_VER(dev_priv) >= 12) intel_ddi_disable_transcoder_clock(old_crtc_state); @@ -3396,7 +3407,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_connector *connector = conn_state->connector; enum port port = encoder->port; - u32 buf_ctl; + u32 buf_ctl = 0; if (!intel_hdmi_handle_sink_scrambling(encoder, connector, crtc_state->hdmi_high_tmds_clock_ratio, @@ -3461,8 +3472,6 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, * is filled with lane count, already set in the crtc_state. * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. */ - buf_ctl = DDI_BUF_CTL_ENABLE; - if (dig_port->lane_reversal) buf_ctl |= DDI_BUF_PORT_REVERSAL; if (dig_port->ddi_a_4_lanes) @@ -3488,9 +3497,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); - - intel_wait_ddi_buf_active(encoder); + intel_ddi_buf_enable(encoder, buf_ctl); } static void intel_ddi_enable(struct intel_atomic_state *state, @@ -3714,7 +3721,6 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(crtc_state); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - enum port port = encoder->port; u32 dp_tp_ctl; /* @@ -3748,15 +3754,11 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, mtl_port_buf_ctl_program(encoder, crtc_state); /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ - intel_dp->DP |= DDI_BUF_CTL_ENABLE; if (DISPLAY_VER(display) >= 20) intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; - intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(display, DDI_BUF_CTL(port)); - - /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ - intel_wait_ddi_buf_active(encoder); + intel_ddi_buf_enable(encoder, intel_dp->DP); + intel_dp->DP |= DDI_BUF_CTL_ENABLE; } static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, @@ -3766,7 +3768,6 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; u32 dp_tp_ctl; dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); @@ -3789,11 +3790,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) adlp_tbt_to_dp_alt_switch_wa(encoder); + intel_ddi_buf_enable(encoder, intel_dp->DP); intel_dp->DP |= DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); - - intel_wait_ddi_buf_active(encoder); } static void intel_ddi_set_link_train(struct intel_dp *intel_dp, From patchwork Fri Feb 14 14:20:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13975006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17BFCC021A4 for ; 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X-CSE-ConnectionGUID: SqqT641MQcqD8IImxvZULA== X-CSE-MsgGUID: VMZxX6fsQZOddGj8xoP90A== X-IronPort-AV: E=McAfee;i="6700,10204,11345"; a="27892517" X-IronPort-AV: E=Sophos;i="6.13,286,1732608000"; d="scan'208";a="27892517" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:21 -0800 X-CSE-ConnectionGUID: TweFm7msTyKx13SYSEdpeQ== X-CSE-MsgGUID: XuP9pAksTqGKTzOR1MmgTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="136694385" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 06:19:19 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 11/11] drm/i915/ddi: Sanitize DDI_BUF_CTL register definitions Date: Fri, 14 Feb 2025 16:20:01 +0200 Message-ID: <20250214142001.552916-12-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250214142001.552916-1-imre.deak@intel.com> References: <20250214142001.552916-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Align the DDI_BUF_CTL register flag definitions with how this is done elsewhere. v2: Robustify macro calls with parens. (Jani) Reviewed-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 50efaab3b5536..3a936a4aa2e88 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3625,27 +3625,29 @@ enum skl_power_gate { #define _DDI_BUF_CTL_B 0x64100 /* Known as DDI_CTL_DE in MTL+ */ #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) -#define DDI_BUF_CTL_ENABLE (1 << 31) +#define DDI_BUF_CTL_ENABLE REG_BIT(31) #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) -#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) -#define DDI_BUF_EMP_MASK (0xf << 24) -#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) +#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24) +#define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n)) +#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20) +#define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r)) #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) -#define DDI_BUF_PORT_REVERSAL (1 << 16) +#define DDI_BUF_PORT_REVERSAL REG_BIT(16) #define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8) #define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \ (symbols)) -#define DDI_BUF_IS_IDLE (1 << 7) +#define DDI_BUF_IS_IDLE REG_BIT(7) #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) -#define DDI_A_4_LANES (1 << 4) -#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 : ((width) - 1)) << 1) -#define DDI_PORT_WIDTH_MASK (7 << 1) +#define DDI_A_4_LANES REG_BIT(4) +#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) +#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \ + ((width) == 3 ? 4 : (width) - 1)) #define DDI_PORT_WIDTH_SHIFT 1 -#define DDI_INIT_DISPLAY_DETECTED (1 << 0) +#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0) /* DDI Buffer Translations */ #define _DDI_BUF_TRANS_A 0x64E00