From patchwork Sat Feb 15 01:36:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975895 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1382638DE3 for ; Sat, 15 Feb 2025 01:36:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739583401; cv=none; b=XP1ugilMenDpYvk78H/PWO6YiqiMFAdVtg9V6qoj1LHFlZ5XrdKtQbM4cI9BA04ujQxvQXq7KmVvMBgwH4P7tfip5OxEuZTb5qidj2VTzkckYGzh40wEM0Lu3zCED37gF1hA7QFogMbSfoiAB+neTdPO6z42YFA5F2lVjWmZeAY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739583401; c=relaxed/simple; bh=gC55Rn0QCScvbLdX9GUMbAZaL3gXRtlxoZ6aHYyAUYU=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=MWfU/uhdY6PDhEM8NgPNyYJCflHk0GVzfoapkhVK3XJR1i1EtNPnmerwuMyn9wVVmMCTIBuU5SiqrHZdzfryt3bbhH/0Owv6yJObjbAxB5sxpr5lJBjzSNav9yWKIiEisx4gvF5EL5I3hNRSVWw5ZIGKOeuTZtT9YRUdDYX+uqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=Y9zA2j6O; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Y9zA2j6O" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2fa514fa6c7so6360816a91.3 for ; Fri, 14 Feb 2025 17:36:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1739583399; x=1740188199; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=ArY4hGYgC1pxKO2UIP9bmr5ON9KNT/VwgyhK+65WX6w=; b=Y9zA2j6O40WooGoY5teiicV4UhEEgejN20Hh5qilDFMRPqIZOIEkpFfsd8HcOnaqBf NGWS9Prh4Kri+yByV4+q/QHs2IVfiUdwcL/s0FGqoJxAacIhFkI8FJEQJxqDRAHmvLKu XYMwjobxfgCYJmNudc3BfkkVXru99WCIYzLFjcwZTKGyiq/Z3ICxCb+5klWLAgB8aRtC XtzmL2eFOrtNGjfLaVIU9ceSb2Kxttnkai3s2GXNBDJhpvvmFNspKX2ZTVVcGBth07pS DmUx2n37ucJa5QiNpS+u2qwu7FwEPjSMfYOVNx4q03hlvCMGMmo+YNtynYvXCgQrL0XA IQzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739583399; x=1740188199; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ArY4hGYgC1pxKO2UIP9bmr5ON9KNT/VwgyhK+65WX6w=; b=Yd0rBa8mZnhaPBGxYaP4jOfyubwdN1+GixrXMJgpFBm7ROWGiY4msxhT3rVLnW7oJ6 9hhmXEjukqvb0HJw29XPI6Zanxu7PrfJA1RYktdJSxiOdSCfgP8WOLnGN4ucCAuXz+cz hQWFiUcoJuOqoi15rqSKOgmsKaj3kv50qejvAF8dBC+KeGl3psuv7e3VZI828zowsiAx WJ8wDfDDTP2zyCDXba++5ybQpa2Yzy9ZEI//o03ojUsjX/REPfucNtoQUJTYwOPZ8ybJ 17pxzoqWnOUg+wJ4dh2NTdcr5hxRze1g17kk/XxVF2YLVpx3tB9ykTIebrLeZUFv1ypB Ir6g== X-Gm-Message-State: AOJu0Yx+CSHY0Mpp5d54mLtpRVllPXMkcFMqeQkRhGiHw3eFWIsUNn8R qFTN3UIILYAjQM0SV+nQt5f87XU3eoW/xgMtbUg2MPVAzbCyrcCALqSzRlFVliEybfrpuUL+sj8 6Ew== X-Google-Smtp-Source: AGHT+IFoaWfBBnKGIVP1BaHnGQ98kUXJrVdhtWU+JyElpIpEys10qlRGXsOQKNPI9GkQ3+W+G5IuPWoBugE= X-Received: from pjf8.prod.google.com ([2002:a17:90b:3f08:b0:2fa:284f:adae]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1e4f:b0:2fa:13e9:8cb0 with SMTP id 98e67ed59e1d1-2fc41153fe0mr1705785a91.31.1739583399444; Fri, 14 Feb 2025 17:36:39 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:18 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-2-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 01/18] x86: pmu: Remove duplicate code in pmu_init() From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Xiong Zhang There are totally same code in pmu_init() helper, remove the duplicate code. Reviewed-by: Jim Mattson Signed-off-by: Xiong Zhang Signed-off-by: Dapeng Mi Reviewed-by: Mingwei Zhang Signed-off-by: Sean Christopherson --- lib/x86/pmu.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c index 0f2afd65..d06e9455 100644 --- a/lib/x86/pmu.c +++ b/lib/x86/pmu.c @@ -16,11 +16,6 @@ void pmu_init(void) pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; } - if (pmu.version > 1) { - pmu.nr_fixed_counters = cpuid_10.d & 0x1f; - pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; - } - pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff; pmu.gp_counter_width = (cpuid_10.a >> 16) & 0xff; pmu.gp_counter_mask_length = (cpuid_10.a >> 24) & 0xff; From patchwork Sat Feb 15 01:36:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975896 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB84D13DDAE for ; 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Fri, 14 Feb 2025 17:36:41 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:19 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-3-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 02/18] x86: pmu: Remove blank line and redundant space From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi code style changes. Reviewed-by: Mingwei Zhang Signed-off-by: Dapeng Mi Reviewed-by: Jim Mattson Signed-off-by: Sean Christopherson --- x86/pmu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index ce9abbe1..865dbe67 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -205,8 +205,7 @@ static noinline void __measure(pmu_counter_t *evt, uint64_t count) static bool verify_event(uint64_t count, struct pmu_event *e) { // printf("%d <= %ld <= %d\n", e->min, count, e->max); - return count >= e->min && count <= e->max; - + return count >= e->min && count <= e->max; } static bool verify_counter(pmu_counter_t *cnt) From patchwork Sat Feb 15 01:36:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975897 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C625614A62A for ; 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Fri, 14 Feb 2025 17:36:43 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:20 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-4-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 03/18] x86: pmu: Refine fixed_events[] names From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi In SDM the fixed counter is numbered from 0 but currently the fixed_events names are numbered from 1. It would cause confusion for users. So Change the fixed_events[] names to number from 0 as well and keep identical with SDM. Reviewed-by: Mingwei Zhang Signed-off-by: Dapeng Mi Reviewed-by: Jim Mattson Signed-off-by: Sean Christopherson --- x86/pmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 865dbe67..60db8bdf 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -45,9 +45,9 @@ struct pmu_event { {"branches", 0x00c2, 1*N, 1.1*N}, {"branch misses", 0x00c3, 0, 0.1*N}, }, fixed_events[] = { - {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, - {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, - {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} + {"fixed 0", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, + {"fixed 1", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, + {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} }; char *buf; From patchwork Sat Feb 15 01:36:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975898 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AC6D44C94 for ; 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Fri, 14 Feb 2025 17:36:44 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:21 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-5-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 04/18] x86: pmu: Align fields in pmu_counter_t to better pack the struct From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi Hoist "idx" up in the pmu_counter_t structure so that the structure is naturally packed for 64-bit builds. Signed-off-by: Dapeng Mi Link: https://lore.kernel.org/r/20240914101728.33148-5-dapeng1.mi@linux.intel.com [sean: rewrite changelog] Signed-off-by: Sean Christopherson --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index 60db8bdf..a0268db8 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -21,9 +21,9 @@ typedef struct { uint32_t ctr; + uint32_t idx; uint64_t config; uint64_t count; - int idx; } pmu_counter_t; struct pmu_event { From patchwork Sat Feb 15 01:36:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975899 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E89D27DA62 for ; Sat, 15 Feb 2025 01:36:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 14 Feb 2025 17:36:46 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:22 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-6-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 05/18] x86: pmu: Enlarge cnt[] length to 48 in check_counters_many() From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi Considering there are already 8 GP counters and 4 fixed counters on latest Intel processors, like Sapphire Rapids. The original cnt[] array length 10 is definitely not enough to cover all supported PMU counters on these new processors even through currently KVM only supports 3 fixed counters at most. This would cause out of bound memory access and may trigger false alarm on PMU counter validation It's probably more and more GP and fixed counters are introduced in the future and then directly extends the cnt[] array length to 48 once and for all. Base on the layout of IA32_PERF_GLOBAL_CTRL and IA32_PERF_GLOBAL_STATUS, 48 looks enough in near feature. Reviewed-by: Jim Mattson Signed-off-by: Dapeng Mi [sean: assert() on the size] Signed-off-by: Sean Christopherson --- x86/pmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index a0268db8..d3617c80 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -255,7 +255,7 @@ static void check_fixed_counters(void) static void check_counters_many(void) { - pmu_counter_t cnt[10]; + pmu_counter_t cnt[48]; int i, n; for (i = 0, n = 0; n < pmu.nr_gp_counters; i++) { @@ -273,6 +273,7 @@ static void check_counters_many(void) n++; } + assert(n <= ARRAY_SIZE(cnt)); measure_many(cnt, n); for (i = 0; i < n; i++) From patchwork Sat Feb 15 01:36:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975900 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3F201547E9 for ; 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Fri, 14 Feb 2025 17:36:48 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:23 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-7-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 06/18] x86: pmu: Print measured event count if test fails From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi Print the measured event count if the test case fails. This helps users quickly know why the test case fails. Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index d3617c80..89197352 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -204,8 +204,12 @@ static noinline void __measure(pmu_counter_t *evt, uint64_t count) static bool verify_event(uint64_t count, struct pmu_event *e) { - // printf("%d <= %ld <= %d\n", e->min, count, e->max); - return count >= e->min && count <= e->max; + bool pass = count >= e->min && count <= e->max; + + if (!pass) + printf("FAIL: %d <= %"PRId64" <= %d\n", e->min, count, e->max); + + return pass; } static bool verify_counter(pmu_counter_t *cnt) From patchwork Sat Feb 15 01:36:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975901 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7C6C156F44 for ; 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Fri, 14 Feb 2025 17:36:49 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:24 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-8-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 07/18] x86: pmu: Fix potential out of bound access for fixed events From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi Current PMU code doesn't check whether PMU fixed counter number is larger than pre-defined fixed events. If so, it would cause memory access out of range. So limit validated fixed counters number to MIN(pmu.nr_fixed_counters, ARRAY_SIZE(fixed_events)) and print message to warn that KUT/pmu tests need to be updated if fixed counters number exceeds defined fixed events number. Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 89197352..4353d1da 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -54,6 +54,7 @@ char *buf; static struct pmu_event *gp_events; static unsigned int gp_events_size; +static unsigned int fixed_counters_num; static inline void loop(void) { @@ -113,8 +114,12 @@ static struct pmu_event* get_counter_event(pmu_counter_t *cnt) for (i = 0; i < gp_events_size; i++) if (gp_events[i].unit_sel == (cnt->config & 0xffff)) return &gp_events[i]; - } else - return &fixed_events[cnt->ctr - MSR_CORE_PERF_FIXED_CTR0]; + } else { + unsigned int idx = cnt->ctr - MSR_CORE_PERF_FIXED_CTR0; + + if (idx < ARRAY_SIZE(fixed_events)) + return &fixed_events[idx]; + } return (void*)0; } @@ -204,8 +209,12 @@ static noinline void __measure(pmu_counter_t *evt, uint64_t count) static bool verify_event(uint64_t count, struct pmu_event *e) { - bool pass = count >= e->min && count <= e->max; + bool pass; + if (!e) + return false; + + pass = count >= e->min && count <= e->max; if (!pass) printf("FAIL: %d <= %"PRId64" <= %d\n", e->min, count, e->max); @@ -250,7 +259,7 @@ static void check_fixed_counters(void) }; int i; - for (i = 0; i < pmu.nr_fixed_counters; i++) { + for (i = 0; i < fixed_counters_num; i++) { cnt.ctr = fixed_events[i].unit_sel; measure_one(&cnt); report(verify_event(cnt.count, &fixed_events[i]), "fixed-%d", i); @@ -271,7 +280,7 @@ static void check_counters_many(void) gp_events[i % gp_events_size].unit_sel; n++; } - for (i = 0; i < pmu.nr_fixed_counters; i++) { + for (i = 0; i < fixed_counters_num; i++) { cnt[n].ctr = fixed_events[i].unit_sel; cnt[n].config = EVNTSEL_OS | EVNTSEL_USR; n++; @@ -420,7 +429,7 @@ static void check_rdpmc(void) else report(cnt.count == (u32)val, "fast-%d", i); } - for (i = 0; i < pmu.nr_fixed_counters; i++) { + for (i = 0; i < fixed_counters_num; i++) { uint64_t x = val & ((1ull << pmu.fixed_counter_width) - 1); pmu_counter_t cnt = { .ctr = MSR_CORE_PERF_FIXED_CTR0 + i, @@ -745,6 +754,12 @@ int main(int ac, char **av) printf("Fixed counters: %d\n", pmu.nr_fixed_counters); printf("Fixed counter width: %d\n", pmu.fixed_counter_width); + fixed_counters_num = MIN(pmu.nr_fixed_counters, ARRAY_SIZE(fixed_events)); + if (pmu.nr_fixed_counters > ARRAY_SIZE(fixed_events)) + report_info("Fixed counters number %d > defined fixed events %u. " + "Please update test case.", pmu.nr_fixed_counters, + (uint32_t)ARRAY_SIZE(fixed_events)); + apic_write(APIC_LVTPC, PMI_VECTOR); check_counters(); From patchwork Sat Feb 15 01:36:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975902 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEA29156F44 for ; Sat, 15 Feb 2025 01:36:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739583415; cv=none; b=rB9RsNpdmSFJY4wdXWm+Y1F5E4XptBWYAd9Np4HG74EsGSkPQx4cMVuZeY1kOEvrGVEQH9Br9+dmusNiD6pCjWAOMr2eNX7MbuuicdSfE5kfwV0RJ7QQbDeQjDiXdnpvDdBB2UcurUZJfYrlaFbSYHf2VGjYejB407qXM95IZTU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739583415; c=relaxed/simple; bh=heUNsR7O2oJmARCK5a9rDX4QUcsxloKKOM3pTSe69YA=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=YL2dWZm1WumqiLfF7/W3TDG8gXAjcDB2qbsCtqupcOdEzOztI10JnLUvUtm1FiXWmStoWlMFNtDmUlINX60s9OliZO7xCq7CK6VWr2Qwrsw2weqAUyPX6eoJqEkpRBM+vNbpkdU1BPT4ARxWkryRNz8ZbyksF1H2Hh8FbepyFUo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=cyo5wAnM; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="cyo5wAnM" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-2fc2b258e82so3106484a91.0 for ; Fri, 14 Feb 2025 17:36:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1739583412; x=1740188212; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=u4eIK5GYRC3vU5hQex9Sd/VmwsqD31JoX2XJtktxhXE=; b=cyo5wAnMUkAnH2H2BHOSuyCu32/SGPfMiVvCUqA2nqUC1W2w3tlmHh4fvkNL3WIWQL KYLZLH5waYBrMvkE4OIb8roTA3crCjRcwpVZ8jEUEJDIBO68gMUpyOyNZUoKf0yg1p9H Hjs80aGYRg6NF9Wq0+IKG3XYXIFntmxmZl6+EgaezsNtzSV+s+L6oNn5Qdvkvgqda/ep 7PSf6pIwUEXuRmJRD3f3RY8nDrq3LxTjm8ILecE01EPeYVuUpgfturMFTrDlNUWhTxWh qMeAtXYtXkaIoGXgoGHmL+Um31oRtUOtzvIBVvXQRTYhYfiKwTuP/sxe2n6Yu0g4NWEz I/tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739583412; x=1740188212; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=u4eIK5GYRC3vU5hQex9Sd/VmwsqD31JoX2XJtktxhXE=; b=fp3Q917BOBwNjN46oVNmRwdvqVg4nqWm2nZKnPQVC1p1FO8HVHKjq6AiscK9CxOY2w kaS16UPsZZIyORfitZc9XoLImcItHkN7TYo1PZ6TpMUCOqrMrY8Xkkgy/qYg5/v3lBw9 F+NhUCtNlzuNF8fwyimnUwyh4qNboQgJP1OGMDWFVdAdhs7Q/A6n7ITIfyEjjxhGX4T2 h8ygEpr26F0Va0ZB+VgfCa4WY3LcEiUqcklOGfNJY0EhNje88ALsMmGS01KhHD695Ayt 0XwCNHjgc5/NEWYjrQL9ltZF20ZOueaoVOJhrGRn44qM9jc8orVDHxG90HMX1lSmj+pr jKgQ== X-Gm-Message-State: AOJu0YzxkHrFFMuHeSfhTIhR1L32GVxSCpbCehOzEY0zmne2uK9pJL3L RdgaDldMdARBO9oQj6sh6KdhXMd4v9npvuMblIFfpLPLdYWBIEm/dmGSfkA0V5ZV2AigSAybSaz axg== X-Google-Smtp-Source: AGHT+IFIXWCFY/0NnOqfgay1QRWDMr/mYoZDPPhaohi9WHk7ocn1hlK1qE31P1uYU65aJkV3l7P2NWx58WE= X-Received: from pfbgj13.prod.google.com ([2002:a05:6a00:840d:b0:730:7d23:bc34]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:4311:b0:1e1:9f57:eab4 with SMTP id adf61e73a8af0-1ee8cb4f0a7mr2476498637.16.1739583411856; Fri, 14 Feb 2025 17:36:51 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:25 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-9-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 08/18] x86: pmu: Fix cycles event validation failure From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi When running pmu test on SPR, sometimes the following failure is reported. PMU version: 2 GP counters: 8 GP counter width: 48 Mask length: 8 Fixed counters: 3 Fixed counter width: 48 1000000 <= 55109398 <= 50000000 FAIL: Intel: core cycles-0 1000000 <= 18279571 <= 50000000 PASS: Intel: core cycles-1 1000000 <= 12238092 <= 50000000 PASS: Intel: core cycles-2 1000000 <= 7981727 <= 50000000 PASS: Intel: core cycles-3 1000000 <= 6984711 <= 50000000 PASS: Intel: core cycles-4 1000000 <= 6773673 <= 50000000 PASS: Intel: core cycles-5 1000000 <= 6697842 <= 50000000 PASS: Intel: core cycles-6 1000000 <= 6747947 <= 50000000 PASS: Intel: core cycles-7 The count of the "core cycles" on first counter would exceed the upper boundary and leads to a failure, and then the "core cycles" count would drop gradually and reach a stable state. That looks reasonable. The "core cycles" event is defined as the 1st event in xxx_gp_events[] array and it is always verified at first. when the program loop() is executed at the first time it needs to warm up the pipeline and cache, such as it has to wait for cache is filled. All these warm-up work leads to a quite large core cycles count which may exceeds the verification range. To avoid the false positive of cycles event caused by warm-up, explicitly introduce a warm-up state before really starting verification. Signed-off-by: Dapeng Mi [sean: use a for loop and an more obviously arbitrary number] Signed-off-by: Sean Christopherson --- x86/pmu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index 4353d1da..e672b540 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -603,11 +603,27 @@ static void check_tsx_cycles(void) report_prefix_pop(); } +static void warm_up(void) +{ + int i; + + /* + * Since cycles event is always run as the first event, there would be + * a warm-up state to warm up the cache, it leads to the measured cycles + * value may exceed the pre-defined cycles upper boundary and cause + * false positive. To avoid this, introduce an warm-up state before + * the real verification. + */ + for (i = 0; i < 10; i++) + loop(); +} + static void check_counters(void) { if (is_fep_available()) check_emulated_instr(); + warm_up(); check_gp_counters(); check_fixed_counters(); check_rdpmc(); From patchwork Sat Feb 15 01:36:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975903 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 589A7146D57 for ; Sat, 15 Feb 2025 01:36:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739583416; cv=none; b=cpayGsqZdWYY/ynB5vlHBu5CbuPkJJFDMDFZvR2fuWan9b0pVQXw5Oay5dtGoQnuAqY0LKDqOYYZSb6+7qBauCjX5f6c9+d0gODe2DKw8WuKgjxzlOAjYdvGYhB0CWHgR47wewaBSB2/08UBLdLycBP73Sg+7fwAz7e3MYPiPl0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739583416; c=relaxed/simple; bh=g2UtA37LTLnaBI/4XrlLogCALh/D7CCUimiX5kJFwyQ=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=LRLjgYe9rwLGXleYXTSRNvsRJh30LzG6k2V0s9oZ/51YMU7u1m8/MAwpCztbL3qlp90Z17bBgFr17G2Wl4fjTaTky1Ql3r/q4+KRJbbB6q9fYGC5RjIvlDKnYk6mxMn6hki2MQ6DsOqcYVS25MkJA8oY8C8E15X8xnAiZvTj0Dw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=3CKMF/Vc; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="3CKMF/Vc" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2f46b7851fcso8454012a91.1 for ; Fri, 14 Feb 2025 17:36:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1739583413; x=1740188213; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=Uy9reQyVdJbAJ0FPCNe5rNP+p5qm8ddnVApJHMSA5Ck=; b=3CKMF/Vc++xI95NLGAUGEHLU5n9KLKS0SmoCx3+OyP0EpYKfrSyZ1LAlA0mGhQo+cW YyBpkkpxCyCB/XdAgAQKbIDqPe5R2tHAsGN8E2+3XOb4w8v8c3KRJRFDty7gsh/0jRQS iDj4iC1RHlmd6pns1CLT27Q5XRieQNEyngBJOUTHkVUKY+9uwjgKE3EyshYKUFQza7gK 59MRIjIJNz/Pv4CxUQ0RVNBvP4dmE3Jz6eGV0tlSuXXzesG3ki91C4J/mF86mrUj4/eG nGDgRYm6nRy3JTgZUYYzhvMqDcvQsNpgbqk+R0FXd837jz3XpZP52QlSXMG+zbocEQ9j Ayag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739583413; x=1740188213; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Uy9reQyVdJbAJ0FPCNe5rNP+p5qm8ddnVApJHMSA5Ck=; b=UmuXdhBcGnm+e1FGh+MWbPXFpfaG3vUSCVKMoLFWhe7VVm5N6NGBV+EgPOY++T+t2I N/JINZH9fcwuA95yjhsgfhQqKk7g+Pf0Q36KApU2GQ+mn/aJ33aXSCJbeoouhfVyTQAQ acWzHm8Y/fea2QnCMag+FNQAgT3IfBWLEFjui9IU2ADiyq9baLL+e9QeGOIW3wDBtle7 nqdPyK4e040zRD2yGl1FtwQsPKwynVI7cJKPNDuhpNQ8znmhpWd5EnEafFJdiwz2BmsF yJhhVzX2ff0k5KAMPNptacDPbwVdaVRn/9S4PFo6qvQtgoYc0eXIYaH97BoT4GxY7w8Z qA2g== X-Gm-Message-State: AOJu0Yxa1xJ85g5c/fQFHj2VnZe4/I1qGWl2yrqN7munFs3lMsg5An2a oF/tQuXlzqdVp3T0ipKyncG0IqPx+UTCcfbAjn/cJYWUUAx+zO0a+UJdETLOhI8jpyhfASFP6UR XNw== X-Google-Smtp-Source: AGHT+IH3/69V9qwTKWvz/CsJbONgT65RLc3QIgbQavfteLmCbKtUQLUMesOhZ7kFWVm6c4mSl1+6J1UUryc= X-Received: from pjbeu15.prod.google.com ([2002:a17:90a:f94f:b0:2fc:1eb0:5743]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:52c8:b0:2ee:ab29:1482 with SMTP id 98e67ed59e1d1-2fc40f21294mr2286075a91.16.1739583413637; Fri, 14 Feb 2025 17:36:53 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:26 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-10-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 09/18] x86: pmu: Use macro to replace hard-coded branches event index From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi Currently the branches event index is a hard-coded number. User could add new events and cause the branches event index changes in the future, but don't notice the hard-coded event index and forget to update the event index synchronously, then the issue comes. Thus, replace the hard-coded index to a macro. Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index e672b540..befbbe18 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -50,6 +50,22 @@ struct pmu_event { {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} }; +/* + * Events index in intel_gp_events[], ensure consistent with + * intel_gp_events[]. + */ +enum { + INTEL_BRANCHES_IDX = 5, +}; + +/* + * Events index in amd_gp_events[], ensure consistent with + * amd_gp_events[]. + */ +enum { + AMD_BRANCHES_IDX = 2, +}; + char *buf; static struct pmu_event *gp_events; @@ -493,7 +509,8 @@ static void check_emulated_instr(void) { uint64_t status, instr_start, brnch_start; uint64_t gp_counter_width = (1ull << pmu.gp_counter_width) - 1; - unsigned int branch_idx = pmu.is_intel ? 5 : 2; + unsigned int branch_idx = pmu.is_intel ? + INTEL_BRANCHES_IDX : AMD_BRANCHES_IDX; pmu_counter_t brnch_cnt = { .ctr = MSR_GP_COUNTERx(0), /* branch instructions */ From patchwork Sat Feb 15 01:36:27 2025 Content-Type: text/plain; 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Fri, 14 Feb 2025 17:36:55 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:27 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-11-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 10/18] x86: pmu: Use macro to replace hard-coded ref-cycles event index From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi Replace hard-coded ref-cycles event index with macro to avoid possible mismatch issue if new event is added in the future and cause ref-cycles event index changed, but forget to update the hard-coded ref-cycles event index. Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index befbbe18..7ecde9f6 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -55,6 +55,7 @@ struct pmu_event { * intel_gp_events[]. */ enum { + INTEL_REF_CYCLES_IDX = 2, INTEL_BRANCHES_IDX = 5, }; @@ -709,7 +710,8 @@ static void set_ref_cycle_expectations(void) { pmu_counter_t cnt = { .ctr = MSR_IA32_PERFCTR0, - .config = EVNTSEL_OS | EVNTSEL_USR | intel_gp_events[2].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | + intel_gp_events[INTEL_REF_CYCLES_IDX].unit_sel, }; uint64_t tsc_delta; uint64_t t0, t1, t2, t3; @@ -745,8 +747,10 @@ static void set_ref_cycle_expectations(void) if (!tsc_delta) return; - intel_gp_events[2].min = (intel_gp_events[2].min * cnt.count) / tsc_delta; - intel_gp_events[2].max = (intel_gp_events[2].max * cnt.count) / tsc_delta; + intel_gp_events[INTEL_REF_CYCLES_IDX].min = + (intel_gp_events[INTEL_REF_CYCLES_IDX].min * cnt.count) / tsc_delta; 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Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 7ecde9f6..c7eda47a 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -55,6 +55,7 @@ struct pmu_event { * intel_gp_events[]. */ enum { + INTEL_INSTRUCTIONS_IDX = 1, INTEL_REF_CYCLES_IDX = 2, INTEL_BRANCHES_IDX = 5, }; @@ -64,6 +65,7 @@ enum { * amd_gp_events[]. */ enum { + AMD_INSTRUCTIONS_IDX = 1, AMD_BRANCHES_IDX = 2, }; @@ -329,11 +331,16 @@ static uint64_t measure_for_overflow(pmu_counter_t *cnt) static void check_counter_overflow(void) { + int i; uint64_t overflow_preset; - int i; + int instruction_idx = pmu.is_intel ? + INTEL_INSTRUCTIONS_IDX : + AMD_INSTRUCTIONS_IDX; + pmu_counter_t cnt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | + gp_events[instruction_idx].unit_sel /* instructions */, }; overflow_preset = measure_for_overflow(&cnt); @@ -389,13 +396,18 @@ static void check_counter_overflow(void) static void check_gp_counter_cmask(void) { + int instruction_idx = pmu.is_intel ? + INTEL_INSTRUCTIONS_IDX : + AMD_INSTRUCTIONS_IDX; + pmu_counter_t cnt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | + gp_events[instruction_idx].unit_sel /* instructions */, }; cnt.config |= (0x2 << EVNTSEL_CMASK_SHIFT); measure_one(&cnt); - report(cnt.count < gp_events[1].min, "cmask"); + report(cnt.count < gp_events[instruction_idx].min, "cmask"); } static void do_rdpmc_fast(void *ptr) @@ -470,9 +482,14 @@ static void check_running_counter_wrmsr(void) { uint64_t status; uint64_t count; + unsigned int instruction_idx = pmu.is_intel ? + INTEL_INSTRUCTIONS_IDX : + AMD_INSTRUCTIONS_IDX; + pmu_counter_t evt = { .ctr = MSR_GP_COUNTERx(0), - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | + gp_events[instruction_idx].unit_sel, }; report_prefix_push("running counter wrmsr"); @@ -481,7 +498,7 @@ static void check_running_counter_wrmsr(void) loop(); wrmsr(MSR_GP_COUNTERx(0), 0); stop_event(&evt); - report(evt.count < gp_events[1].min, "cntr"); + report(evt.count < gp_events[instruction_idx].min, "cntr"); /* clear status before overflow test */ if (this_cpu_has_perf_global_status()) @@ -512,6 +529,9 @@ static void check_emulated_instr(void) uint64_t gp_counter_width = (1ull << pmu.gp_counter_width) - 1; unsigned int branch_idx = pmu.is_intel ? INTEL_BRANCHES_IDX : AMD_BRANCHES_IDX; + unsigned int instruction_idx = pmu.is_intel ? + INTEL_INSTRUCTIONS_IDX : + AMD_INSTRUCTIONS_IDX; pmu_counter_t brnch_cnt = { .ctr = MSR_GP_COUNTERx(0), /* branch instructions */ @@ -520,7 +540,7 @@ static void check_emulated_instr(void) pmu_counter_t instr_cnt = { .ctr = MSR_GP_COUNTERx(1), /* instructions */ - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[instruction_idx].unit_sel, }; report_prefix_push("emulated instruction"); From patchwork Sat Feb 15 01:36:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975906 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E06714D28C for ; Sat, 15 Feb 2025 01:36:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 14 Feb 2025 17:36:58 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:29 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-13-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 12/18] x86: pmu: Enable and disable PMCs in loop() asm blob From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi Currently enabling PMCs, executing loop() and disabling PMCs are divided 3 separated functions. So there could be other instructions executed between enabling PMCS and running loop() or running loop() and disabling PMCs, e.g. if there are multiple counters enabled in measure_many() function, the instructions which enabling the 2nd and more counters would be counted in by the 1st counter. So current implementation can only verify the correctness of count by an rough range rather than a precise count even for instructions and branches events. Strictly speaking, this verification is meaningless as the test could still pass even though KVM vPMU has something wrong and reports an incorrect instructions or branches count which is in the rough range. Thus, move the PMCs enabling and disabling into the loop() asm blob and ensure only the loop asm instructions would be counted, then the instructions or branches events can be verified with an precise count instead of an rough range. Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 80 ++++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 65 insertions(+), 15 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index c7eda47a..06d867d9 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -19,6 +19,15 @@ #define EXPECTED_INSTR 17 #define EXPECTED_BRNCH 5 +#define LOOP_ASM(_wrmsr) \ + _wrmsr "\n\t" \ + "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ + "1: mov (%1), %2; add $64, %1;\n\t" \ + "nop; nop; nop; nop; nop; nop; nop;\n\t" \ + "loop 1b;\n\t" \ + "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ + _wrmsr "\n\t" + typedef struct { uint32_t ctr; uint32_t idx; @@ -75,13 +84,43 @@ static struct pmu_event *gp_events; static unsigned int gp_events_size; static unsigned int fixed_counters_num; -static inline void loop(void) + +static inline void __loop(void) +{ + unsigned long tmp, tmp2, tmp3; + + asm volatile(LOOP_ASM("nop") + : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) + : "0"(N), "1"(buf)); +} + +/* + * Enable and disable counters in a whole asm blob to ensure + * no other instructions are counted in the window between + * counters enabling and really LOOP_ASM code executing. + * Thus counters can verify instructions and branches events + * against precise counts instead of a rough valid count range. + */ +static inline void __precise_loop(u64 cntrs) { unsigned long tmp, tmp2, tmp3; + unsigned int global_ctl = pmu.msr_global_ctl; + u32 eax = cntrs & (BIT_ULL(32) - 1); + u32 edx = cntrs >> 32; - asm volatile("1: mov (%1), %2; add $64, %1; nop; nop; nop; nop; nop; nop; nop; loop 1b" - : "=c"(tmp), "=r"(tmp2), "=r"(tmp3): "0"(N), "1"(buf)); + asm volatile(LOOP_ASM("wrmsr") + : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) + : "a"(eax), "d"(edx), "c"(global_ctl), + "0"(N), "1"(buf) + : "edi"); +} +static inline void loop(u64 cntrs) +{ + if (!this_cpu_has_perf_global_ctrl()) + __loop(); + else + __precise_loop(cntrs); } volatile uint64_t irq_received; @@ -181,18 +220,17 @@ static void __start_event(pmu_counter_t *evt, uint64_t count) ctrl = (ctrl & ~(0xf << shift)) | (usrospmi << shift); wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl); } - global_enable(evt); apic_write(APIC_LVTPC, PMI_VECTOR); } static void start_event(pmu_counter_t *evt) { __start_event(evt, 0); + global_enable(evt); } -static void stop_event(pmu_counter_t *evt) +static void __stop_event(pmu_counter_t *evt) { - global_disable(evt); if (is_gp(evt)) { wrmsr(MSR_GP_EVENT_SELECTx(event_to_global_idx(evt)), evt->config & ~EVNTSEL_EN); @@ -204,14 +242,24 @@ static void stop_event(pmu_counter_t *evt) evt->count = rdmsr(evt->ctr); } +static void stop_event(pmu_counter_t *evt) +{ + global_disable(evt); + __stop_event(evt); +} + static noinline void measure_many(pmu_counter_t *evt, int count) { int i; + u64 cntrs = 0; + + for (i = 0; i < count; i++) { + __start_event(&evt[i], 0); + cntrs |= BIT_ULL(event_to_global_idx(&evt[i])); + } + loop(cntrs); for (i = 0; i < count; i++) - start_event(&evt[i]); - loop(); - for (i = 0; i < count; i++) - stop_event(&evt[i]); + __stop_event(&evt[i]); } static void measure_one(pmu_counter_t *evt) @@ -221,9 +269,11 @@ static void measure_one(pmu_counter_t *evt) static noinline void __measure(pmu_counter_t *evt, uint64_t count) { + u64 cntrs = BIT_ULL(event_to_global_idx(evt)); + __start_event(evt, count); - loop(); - stop_event(evt); + loop(cntrs); + __stop_event(evt); } static bool verify_event(uint64_t count, struct pmu_event *e) @@ -495,7 +545,7 @@ static void check_running_counter_wrmsr(void) report_prefix_push("running counter wrmsr"); start_event(&evt); - loop(); + __loop(); wrmsr(MSR_GP_COUNTERx(0), 0); stop_event(&evt); report(evt.count < gp_events[instruction_idx].min, "cntr"); @@ -512,7 +562,7 @@ static void check_running_counter_wrmsr(void) wrmsr(MSR_GP_COUNTERx(0), count); - loop(); + __loop(); stop_event(&evt); if (this_cpu_has_perf_global_status()) { @@ -653,7 +703,7 @@ static void warm_up(void) * the real verification. */ for (i = 0; i < 10; i++) - loop(); + loop(0); } static void check_counters(void) From patchwork Sat Feb 15 01:36:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975907 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E28F015198A for ; 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Fri, 14 Feb 2025 17:37:00 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:30 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-14-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 13/18] x86: pmu: Improve instruction and branches events verification From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are moved in __precise_count_loop(). Thus, instructions and branches events can be verified against a precise count instead of a rough range. Unfortunately, AMD CPUs count VMRUN as a branch instruction in guest context, which leads to intermittent failures as the counts will vary depending on how many asynchronous exits occur while running the measured code, e.g. if the host takes IRQs, NMIs, etc. So only enable this precise check for Intel processors. Signed-off-by: Dapeng Mi Link: https://lore.kernel.org/all/6d512a14-ace1-41a3-801e-0beb41425734@amd.com [sean: explain AMD VMRUN behavior, use "INSNS"] Signed-off-by: Sean Christopherson --- x86/pmu.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index 06d867d9..217ab938 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -19,6 +19,10 @@ #define EXPECTED_INSTR 17 #define EXPECTED_BRNCH 5 +/* Enable GLOBAL_CTRL + disable GLOBAL_CTRL instructions */ +#define EXTRA_INSNS (3 + 3) +#define LOOP_INSNS (N * 10 + EXTRA_INSNS) +#define LOOP_BRANCHES (N) #define LOOP_ASM(_wrmsr) \ _wrmsr "\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ @@ -123,6 +127,27 @@ static inline void loop(u64 cntrs) __precise_loop(cntrs); } +static void adjust_events_range(struct pmu_event *gp_events, + int instruction_idx, int branch_idx) +{ + /* + * If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are + * moved in __precise_loop(). Thus, instructions and branches events + * can be verified against a precise count instead of a rough range. + * + * Skip the precise checks on AMD, as AMD CPUs count VMRUN as a branch + * instruction in guest context, which* leads to intermittent failures + * as the counts will vary depending on how many asynchronous VM-Exits + * occur while running the measured code, e.g. if the host takes IRQs. + */ + if (pmu.is_intel && this_cpu_has_perf_global_ctrl()) { + gp_events[instruction_idx].min = LOOP_INSNS; + gp_events[instruction_idx].max = LOOP_INSNS; + gp_events[branch_idx].min = LOOP_BRANCHES; + gp_events[branch_idx].max = LOOP_BRANCHES; + } +} + volatile uint64_t irq_received; static void cnt_overflow(isr_regs_t *regs) @@ -833,6 +858,9 @@ static void check_invalid_rdpmc_gp(void) int main(int ac, char **av) { + int instruction_idx; + int branch_idx; + setup_vm(); handle_irq(PMI_VECTOR, cnt_overflow); buf = malloc(N*64); @@ -846,13 +874,18 @@ int main(int ac, char **av) } gp_events = (struct pmu_event *)intel_gp_events; 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Fri, 14 Feb 2025 17:37:01 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:31 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-15-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 14/18] x86: pmu: Improve LLC misses event verification From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi When running pmu test on SPR, sometimes the following failure is reported. 1 <= 0 <= 1000000 FAIL: Intel: llc misses-4 Currently The LLC misses occurring only depends on probability. It's possible that there is no LLC misses happened in the whole loop(), especially along with processors have larger and larger cache size just like what we observed on SPR. Thus, add clflush instruction into the loop() asm blob and ensure once LLC miss is triggered at least. Suggested-by: Jim Mattson Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 39 ++++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 217ab938..97c05177 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -19,19 +19,30 @@ #define EXPECTED_INSTR 17 #define EXPECTED_BRNCH 5 -/* Enable GLOBAL_CTRL + disable GLOBAL_CTRL instructions */ -#define EXTRA_INSNS (3 + 3) +/* Enable GLOBAL_CTRL + disable GLOBAL_CTRL + clflush/mfence instructions */ +#define EXTRA_INSNS (3 + 3 +2) #define LOOP_INSNS (N * 10 + EXTRA_INSNS) #define LOOP_BRANCHES (N) -#define LOOP_ASM(_wrmsr) \ +#define LOOP_ASM(_wrmsr, _clflush) \ _wrmsr "\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ + _clflush "\n\t" \ + "mfence;\n\t" \ "1: mov (%1), %2; add $64, %1;\n\t" \ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" \ "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ _wrmsr "\n\t" +#define _loop_asm(_wrmsr, _clflush) \ +do { \ + asm volatile(LOOP_ASM(_wrmsr, _clflush) \ + : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) \ + : "a"(eax), "d"(edx), "c"(global_ctl), \ + "0"(N), "1"(buf) \ + : "edi"); \ +} while (0) + typedef struct { uint32_t ctr; uint32_t idx; @@ -88,14 +99,17 @@ static struct pmu_event *gp_events; static unsigned int gp_events_size; static unsigned int fixed_counters_num; - static inline void __loop(void) { unsigned long tmp, tmp2, tmp3; + u32 global_ctl = 0; + u32 eax = 0; + u32 edx = 0; - asm volatile(LOOP_ASM("nop") - : "=c"(tmp), "=r"(tmp2), "=r"(tmp3) - : "0"(N), "1"(buf)); + if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("nop", "clflush (%1)"); + else + _loop_asm("nop", "nop"); } /* @@ -108,15 +122,14 @@ static inline void __loop(void) static inline void __precise_loop(u64 cntrs) { unsigned long tmp, tmp2, tmp3; - unsigned int global_ctl = pmu.msr_global_ctl; + u32 global_ctl = pmu.msr_global_ctl; u32 eax = cntrs & (BIT_ULL(32) - 1); u32 edx = cntrs >> 32; - asm volatile(LOOP_ASM("wrmsr") - : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) - : "a"(eax), "d"(edx), "c"(global_ctl), - "0"(N), "1"(buf) - : "edi"); + if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("wrmsr", "clflush (%1)"); + else + _loop_asm("wrmsr", "nop"); } static inline void loop(u64 cntrs) From patchwork Sat Feb 15 01:36:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975909 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A16E15198A for ; Sat, 15 Feb 2025 01:37:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739583425; cv=none; b=BRTdxvebgixlIT6nPaxr2pYx+Jlgy1XMikrnXFhOS80DVpSjNdwwxOQOv01CcsNxJR8h9YZz/W5iaDz3s31dgYXVf3S/gaER39t02VaV+b4An1dzMxo41bXHFW70UhPzGoHvyeO0TynRY2N6cKtV+ChhnpB3OF2KoyYKBNvgurU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Thus adjust the lower boundary of llc-misses event to 0 to avoid possible false positive. Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index 97c05177..1fc94f26 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -81,6 +81,7 @@ struct pmu_event { enum { INTEL_INSTRUCTIONS_IDX = 1, INTEL_REF_CYCLES_IDX = 2, + INTEL_LLC_MISSES_IDX = 4, INTEL_BRANCHES_IDX = 5, }; @@ -889,6 +890,15 @@ int main(int ac, char **av) gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); instruction_idx = INTEL_INSTRUCTIONS_IDX; branch_idx = INTEL_BRANCHES_IDX; + + /* + * For legacy Intel CPUS without clflush/clflushopt support, + * there is no way to force to trigger a LLC miss, thus set + * the minimum value to 0 to avoid false positives. + */ + if (!this_cpu_has(X86_FEATURE_CLFLUSH)) + gp_events[INTEL_LLC_MISSES_IDX].min = 0; + report_prefix_push("Intel"); set_ref_cycle_expectations(); } else { From patchwork Sat Feb 15 01:36:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975910 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBAE3189903 for ; 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Fri, 14 Feb 2025 17:37:05 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:33 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-17-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 16/18] x86: pmu: Add IBPB indirect jump asm blob From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi Currently the lower boundary of branch misses event is set to 0. Strictly speaking 0 shouldn't be a valid count since it can't tell us if branch misses event counter works correctly or even disabled. Whereas it's also possible and reasonable that branch misses event count is 0 especailly for such simple loop() program with advanced branch predictor. To eliminate such ambiguity and make branch misses event verification more acccurately, an extra IBPB indirect jump asm blob is appended and IBPB command is leveraged to clear the branch target buffer and force to cause a branch miss for the indirect jump. Suggested-by: Jim Mattson Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 70 ++++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 56 insertions(+), 14 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 1fc94f26..63156ea8 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -19,24 +19,52 @@ #define EXPECTED_INSTR 17 #define EXPECTED_BRNCH 5 -/* Enable GLOBAL_CTRL + disable GLOBAL_CTRL + clflush/mfence instructions */ -#define EXTRA_INSNS (3 + 3 +2) +#define IBPB_JMP_INSNS 9 +#define IBPB_JMP_BRANCHES 2 + +#if defined(__i386__) || defined(_M_IX86) /* i386 */ +#define IBPB_JMP_ASM(_wrmsr) \ + "mov $1, %%eax; xor %%edx, %%edx;\n\t" \ + "mov $73, %%ecx;\n\t" \ + _wrmsr "\n\t" \ + "call 1f\n\t" \ + "1: pop %%eax\n\t" \ + "add $(2f-1b), %%eax\n\t" \ + "jmp *%%eax;\n\t" \ + "nop;\n\t" \ + "2: nop;\n\t" +#else /* x86_64 */ +#define IBPB_JMP_ASM(_wrmsr) \ + "mov $1, %%eax; xor %%edx, %%edx;\n\t" \ + "mov $73, %%ecx;\n\t" \ + _wrmsr "\n\t" \ + "call 1f\n\t" \ + "1: pop %%rax\n\t" \ + "add $(2f-1b), %%rax\n\t" \ + "jmp *%%rax;\n\t" \ + "nop;\n\t" \ + "2: nop;\n\t" +#endif + +/* GLOBAL_CTRL enable + disable + clflush/mfence + IBPB_JMP */ +#define EXTRA_INSNS (3 + 3 + 2 + IBPB_JMP_INSNS) #define LOOP_INSNS (N * 10 + EXTRA_INSNS) -#define LOOP_BRANCHES (N) -#define LOOP_ASM(_wrmsr, _clflush) \ - _wrmsr "\n\t" \ +#define LOOP_BRANCHES (N + IBPB_JMP_BRANCHES) +#define LOOP_ASM(_wrmsr1, _clflush, _wrmsr2) \ + _wrmsr1 "\n\t" \ "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ _clflush "\n\t" \ "mfence;\n\t" \ "1: mov (%1), %2; add $64, %1;\n\t" \ "nop; nop; nop; nop; nop; nop; nop;\n\t" \ "loop 1b;\n\t" \ + IBPB_JMP_ASM(_wrmsr2) \ "mov %%edi, %%ecx; xor %%eax, %%eax; xor %%edx, %%edx;\n\t" \ - _wrmsr "\n\t" + _wrmsr1 "\n\t" -#define _loop_asm(_wrmsr, _clflush) \ +#define _loop_asm(_wrmsr1, _clflush, _wrmsr2) \ do { \ - asm volatile(LOOP_ASM(_wrmsr, _clflush) \ + asm volatile(LOOP_ASM(_wrmsr1, _clflush, _wrmsr2) \ : "=b"(tmp), "=r"(tmp2), "=r"(tmp3) \ : "a"(eax), "d"(edx), "c"(global_ctl), \ "0"(N), "1"(buf) \ @@ -100,6 +128,12 @@ static struct pmu_event *gp_events; static unsigned int gp_events_size; static unsigned int fixed_counters_num; +static int has_ibpb(void) +{ + return this_cpu_has(X86_FEATURE_SPEC_CTRL) || + this_cpu_has(X86_FEATURE_AMD_IBPB); +} + static inline void __loop(void) { unsigned long tmp, tmp2, tmp3; @@ -107,10 +141,14 @@ static inline void __loop(void) u32 eax = 0; u32 edx = 0; - if (this_cpu_has(X86_FEATURE_CLFLUSH)) - _loop_asm("nop", "clflush (%1)"); + if (this_cpu_has(X86_FEATURE_CLFLUSH) && has_ibpb()) + _loop_asm("nop", "clflush (%1)", "wrmsr"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("nop", "clflush (%1)", "nop"); + else if (has_ibpb()) + _loop_asm("nop", "nop", "wrmsr"); else - _loop_asm("nop", "nop"); + _loop_asm("nop", "nop", "nop"); } /* @@ -127,10 +165,14 @@ static inline void __precise_loop(u64 cntrs) u32 eax = cntrs & (BIT_ULL(32) - 1); u32 edx = cntrs >> 32; - if (this_cpu_has(X86_FEATURE_CLFLUSH)) - _loop_asm("wrmsr", "clflush (%1)"); + if (this_cpu_has(X86_FEATURE_CLFLUSH) && has_ibpb()) + _loop_asm("wrmsr", "clflush (%1)", "wrmsr"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + _loop_asm("wrmsr", "clflush (%1)", "nop"); + else if (has_ibpb()) + _loop_asm("wrmsr", "nop", "wrmsr"); else - _loop_asm("wrmsr", "nop"); + _loop_asm("wrmsr", "nop", "nop"); } static inline void loop(u64 cntrs) From patchwork Sat Feb 15 01:36:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975911 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC47515198A for ; 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Fri, 14 Feb 2025 17:37:07 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 14 Feb 2025 17:36:34 -0800 In-Reply-To: <20250215013636.1214612-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250215013636.1214612-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: <20250215013636.1214612-18-seanjc@google.com> Subject: [kvm-unit-tests PATCH v7 17/18] x86: pmu: Adjust lower boundary of branch-misses event From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Jim Mattson , Xiong Zhang , Dapeng Mi , Mingwei Zhang , Sean Christopherson From: Dapeng Mi Since the IBPB command is added to force to trigger a branch miss at least, the lower boundary of branch misses event is increased to 1 by default. For these CPUs without IBPB support, adjust dynamically the lower boundary to 0 to avoid false positive. Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 63156ea8..3133abed 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -90,12 +90,12 @@ struct pmu_event { {"llc references", 0x4f2e, 1, 2*N}, {"llc misses", 0x412e, 1, 1*N}, {"branches", 0x00c4, 1*N, 1.1*N}, - {"branch misses", 0x00c5, 0, 0.1*N}, + {"branch misses", 0x00c5, 1, 0.1*N}, }, amd_gp_events[] = { {"core cycles", 0x0076, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, {"branches", 0x00c2, 1*N, 1.1*N}, - {"branch misses", 0x00c3, 0, 0.1*N}, + {"branch misses", 0x00c3, 1, 0.1*N}, }, fixed_events[] = { {"fixed 0", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, {"fixed 1", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, @@ -111,6 +111,7 @@ enum { INTEL_REF_CYCLES_IDX = 2, INTEL_LLC_MISSES_IDX = 4, INTEL_BRANCHES_IDX = 5, + INTEL_BRANCH_MISS_IDX = 6, }; /* @@ -120,6 +121,7 @@ enum { enum { AMD_INSTRUCTIONS_IDX = 1, AMD_BRANCHES_IDX = 2, + AMD_BRANCH_MISS_IDX = 3, }; char *buf; @@ -184,7 +186,8 @@ static inline void loop(u64 cntrs) } static void adjust_events_range(struct pmu_event *gp_events, - int instruction_idx, int branch_idx) + int instruction_idx, int branch_idx, + int branch_miss_idx) { /* * If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are @@ -202,6 +205,15 @@ static void adjust_events_range(struct pmu_event *gp_events, gp_events[branch_idx].min = LOOP_BRANCHES; gp_events[branch_idx].max = LOOP_BRANCHES; } + + /* + * For CPUs without IBPB support, no way to force to trigger a branch + * miss and the measured branch misses is possible to be 0. Thus + * overwrite the lower boundary of branch misses event to 0 to avoid + * false positive. + */ + if (!has_ibpb()) + gp_events[branch_miss_idx].min = 0; } volatile uint64_t irq_received; @@ -916,6 +928,7 @@ int main(int ac, char **av) { int instruction_idx; int branch_idx; + int branch_miss_idx; setup_vm(); handle_irq(PMI_VECTOR, cnt_overflow); @@ -932,6 +945,7 @@ int main(int ac, char **av) gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); instruction_idx = INTEL_INSTRUCTIONS_IDX; branch_idx = INTEL_BRANCHES_IDX; + branch_miss_idx = INTEL_BRANCH_MISS_IDX; /* * For legacy Intel CPUS without clflush/clflushopt support, @@ -948,9 +962,10 @@ int main(int ac, char **av) gp_events = (struct pmu_event *)amd_gp_events; instruction_idx = AMD_INSTRUCTIONS_IDX; branch_idx = AMD_BRANCHES_IDX; + branch_miss_idx = AMD_BRANCH_MISS_IDX; report_prefix_push("AMD"); } - adjust_events_range(gp_events, instruction_idx, branch_idx); + adjust_events_range(gp_events, instruction_idx, branch_idx, branch_miss_idx); printf("PMU version: %d\n", pmu.version); printf("GP counters: %d\n", pmu.nr_gp_counters); From patchwork Sat Feb 15 01:36:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13975912 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6564153808 for ; Sat, 15 Feb 2025 01:37:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739583430; cv=none; b=rjwJq/6XQHex5BIwB8klnbSzKfB78Pk7inndWLbra3iufL7U35QCUMn57Gfb4/TJzeWmCPI4OsbcXdaAbMWFaCvHB7fPOeh9pmmgQuhdbZ82AwhzqmGVCICiNdlGg+R+5LINz9VO2mR9NFuzZyqsNv45DUPDIRGEn00jlCL/MQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Move enabling and disabling PERF_GLOBAL_CTRL MSR into kvm_fep_asm blob, thus instructions and branches events can be verified against precise counts. Signed-off-by: Dapeng Mi Signed-off-by: Sean Christopherson --- x86/pmu.c | 108 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 65 insertions(+), 43 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 3133abed..108eab4b 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -14,11 +14,6 @@ #define N 1000000 -// These values match the number of instructions and branches in the -// assembly block in check_emulated_instr(). -#define EXPECTED_INSTR 17 -#define EXPECTED_BRNCH 5 - #define IBPB_JMP_INSNS 9 #define IBPB_JMP_BRANCHES 2 @@ -71,6 +66,40 @@ do { \ : "edi"); \ } while (0) +/* the number of instructions and branches of the kvm_fep_asm() blob */ +#define KVM_FEP_INSNS 22 +#define KVM_FEP_BRANCHES 5 + +/* + * KVM_FEP is a magic prefix that forces emulation so + * 'KVM_FEP "jne label\n"' just counts as a single instruction. + */ +#define kvm_fep_asm(_wrmsr) \ +do { \ + asm volatile( \ + _wrmsr "\n\t" \ + "mov %%ecx, %%edi;\n\t" \ + "mov $0x0, %%eax;\n\t" \ + "cmp $0x0, %%eax;\n\t" \ + KVM_FEP "jne 1f\n\t" \ + KVM_FEP "jne 1f\n\t" \ + KVM_FEP "jne 1f\n\t" \ + KVM_FEP "jne 1f\n\t" \ + KVM_FEP "jne 1f\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "mov $0xa, %%eax; cpuid;\n\t" \ + "1: mov %%edi, %%ecx; \n\t" \ + "xor %%eax, %%eax; \n\t" \ + "xor %%edx, %%edx;\n\t" \ + _wrmsr "\n\t" \ + : \ + : "a"(eax), "d"(edx), "c"(ecx) \ + : "ebx", "edi"); \ +} while (0) + typedef struct { uint32_t ctr; uint32_t idx; @@ -668,6 +697,7 @@ static void check_running_counter_wrmsr(void) static void check_emulated_instr(void) { + u32 eax, edx, ecx; uint64_t status, instr_start, brnch_start; uint64_t gp_counter_width = (1ull << pmu.gp_counter_width) - 1; unsigned int branch_idx = pmu.is_intel ? @@ -675,6 +705,7 @@ static void check_emulated_instr(void) unsigned int instruction_idx = pmu.is_intel ? INTEL_INSTRUCTIONS_IDX : AMD_INSTRUCTIONS_IDX; + pmu_counter_t brnch_cnt = { .ctr = MSR_GP_COUNTERx(0), /* branch instructions */ @@ -690,55 +721,46 @@ static void check_emulated_instr(void) if (this_cpu_has_perf_global_status()) pmu_clear_global_status(); - start_event(&brnch_cnt); - start_event(&instr_cnt); + __start_event(&brnch_cnt, 0); + __start_event(&instr_cnt, 0); - brnch_start = -EXPECTED_BRNCH; - instr_start = -EXPECTED_INSTR; + brnch_start = -KVM_FEP_BRANCHES; + instr_start = -KVM_FEP_INSNS; wrmsr(MSR_GP_COUNTERx(0), brnch_start & gp_counter_width); wrmsr(MSR_GP_COUNTERx(1), instr_start & gp_counter_width); - // KVM_FEP is a magic prefix that forces emulation so - // 'KVM_FEP "jne label\n"' just counts as a single instruction. - asm volatile( - "mov $0x0, %%eax\n" - "cmp $0x0, %%eax\n" - KVM_FEP "jne label\n" - KVM_FEP "jne label\n" - KVM_FEP "jne label\n" - KVM_FEP "jne label\n" - KVM_FEP "jne label\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "mov $0xa, %%eax\n" - "cpuid\n" - "label:\n" - : - : - : "eax", "ebx", "ecx", "edx"); - if (this_cpu_has_perf_global_ctrl()) - wrmsr(pmu.msr_global_ctl, 0); + if (this_cpu_has_perf_global_ctrl()) { + eax = BIT(0) | BIT(1); + ecx = pmu.msr_global_ctl; + edx = 0; + kvm_fep_asm("wrmsr"); + } else { + eax = ecx = edx = 0; + kvm_fep_asm("nop"); + } - stop_event(&brnch_cnt); - stop_event(&instr_cnt); + __stop_event(&brnch_cnt); + __stop_event(&instr_cnt); // Check that the end count - start count is at least the expected // number of instructions and branches. - report(instr_cnt.count - instr_start >= EXPECTED_INSTR, - "instruction count"); - report(brnch_cnt.count - brnch_start >= EXPECTED_BRNCH, - "branch count"); + if (this_cpu_has_perf_global_ctrl()) { + report(instr_cnt.count - instr_start == KVM_FEP_INSNS, + "instruction count"); + report(brnch_cnt.count - brnch_start == KVM_FEP_BRANCHES, + "branch count"); + } else { + report(instr_cnt.count - instr_start >= KVM_FEP_INSNS, + "instruction count"); + report(brnch_cnt.count - brnch_start >= KVM_FEP_BRANCHES, + "branch count"); + } + if (this_cpu_has_perf_global_status()) { // Additionally check that those counters overflowed properly. status = rdmsr(pmu.msr_global_status); - report(status & 1, "branch counter overflow"); - report(status & 2, "instruction counter overflow"); + report(status & BIT_ULL(0), "branch counter overflow"); + report(status & BIT_ULL(1), "instruction counter overflow"); } report_prefix_pop();