From patchwork Sat Feb 15 23:34:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13976251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0A48C021A4 for ; Sat, 15 Feb 2025 23:37:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=sbLLDWdkkmGg2gJ/dWXDp9NJrL5rckyuc1qaW2EiOzg=; b=hZo0NO4Bua/yVRlGYXnVJHBU5T jOorQIccc9utszlovUAwjW/nuDagVx12nNpryGUFTF8kue2jrhYuALB6SaRVavcPpfpLXqa5UoXoE wFIM0Zmj1L9NGnEhDCavxYrl2CDmQMpcTFFeDvfFc/q+McftP9uUmzt5ZLdvqsULONm9prG22yaxd cMON55ehkkTtYN5T2c6wGt1bRYkrWxUJjsdYaJfnhdtWz4E8pwhsCrBLCam1ZrgrGetZj0NtUgBji osux4Io3F7utwzepGzBQzrw1IZift2+gTnf7KuKCnrW7FpbL3fiIaykEoENXJSkZT75hRJaoXhgib UxeGgnNw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tjRiN-00000000tsL-3U4X; Sat, 15 Feb 2025 23:36:51 +0000 Received: from sender4-op-o14.zoho.com ([136.143.188.14]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tjRgv-00000000tYl-0qBi; Sat, 15 Feb 2025 23:35:22 +0000 ARC-Seal: i=1; a=rsa-sha256; t=1739662508; cv=none; d=zohomail.com; s=zohoarc; b=mbifMoSoMISXAR3xZXE43PYTb4VKgKz3cmubZVfwwT2VLJgOT22619GtQ8sidUBoPXi0Sko/Anpf+p5uar7g90Xe3Ztxunk3hAHVDTagAScw//nKcNeljvApYgOdaSU0gYe4GgkXADDA/TdUqUxGXe+EbA3ohQZ8NwR5YQfszMc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1739662508; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=sbLLDWdkkmGg2gJ/dWXDp9NJrL5rckyuc1qaW2EiOzg=; b=KUAoQz/q6ZiXs1LrledRyiwjuenPgJq1NSTzToxd5g+3XHObSDX3zabLyyWhMYGUoA2H4IjJiA5qC3nZ7erEjl9Fkbx+v0PUJpN3T7enOKcAc2ibH01fY/IbB78YNqGqJKr9iSkXIqFRSNkETeNFo51SGjBDRjpIvyMWP5cimYk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1739662508; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=sbLLDWdkkmGg2gJ/dWXDp9NJrL5rckyuc1qaW2EiOzg=; b=jbPHXtKR3x8zgy3OraOCzqKnb5xaJx6sWJxZLhDmx6BWw1Ma1PzwJDqA8ofG3pHy F24QkmqCJCQeHj2JuAVy4DgkdK9uuZFxGQOw6kjE29S07J5ne7VaKxxUJqWNNfB7Wc/ A2pf+mdyOC46VtBThZRlGsnH6tv2UXN7L9a9T+tI= Received: by mx.zohomail.com with SMTPS id 173966250691519.102304818019547; Sat, 15 Feb 2025 15:35:06 -0800 (PST) From: Nicolas Frattaroli Date: Sun, 16 Feb 2025 00:34:50 +0100 Subject: [PATCH 1/6] dt-bindings: rockchip-thermal: Add RK3576 compatible MIME-Version: 1.0 Message-Id: <20250216-rk3576-tsadc-upstream-v1-1-6ec969322a14@collabora.com> References: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> In-Reply-To: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250215_153521_302148_C66BD574 X-CRM114-Status: UNSURE ( 8.04 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a new compatible for the thermal sensor device on the RK3576 SoC. Signed-off-by: Nicolas Frattaroli Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index b717ea8261ca24ebaf709f410ec6372de1366b8a..49ceed68c92ce5a32ed8d4f39bd88fd052de0e80 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -21,6 +21,7 @@ properties: - rockchip,rk3368-tsadc - rockchip,rk3399-tsadc - rockchip,rk3568-tsadc + - rockchip,rk3576-tsadc - rockchip,rk3588-tsadc - rockchip,rv1108-tsadc From patchwork Sat Feb 15 23:34:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13976253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D08BC021A4 for ; Sat, 15 Feb 2025 23:39:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=8av1iXNMpvlvtcg8scR+m4/u77ONzUeOM2pGww4zkIw=; b=wwxk6K6HLxvpKpeSTtWvQjXxxF hatP9nnPXbENqbid6kkQ/PPAfnEPiS21skvkf0NGaDwvEw3Pfu4wKva70ue23IERQm58mGlPHm+vV uSpcrDDaawQxGBZpHgEeamI1oxMEahrGbhNHh5ATzcfG/PNXB7PI0lMeS11Pb6ithXw2/hubsuKIg gWtRn7d0n0PXm+yrbvYWFIj3qoqEa99msMaMN3iN+ETlNgQDXpeqifBUSzErF+bRJtDP1FHB9Q6Sb 6qBuN2XcQ0iQnSsmoPD1At0KERlcqRIAU7SqfRBP6OiTNL9l6GHln8x8GbHIVNJL5WY71H81Ez4Pg ioYRVVlQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tjRlE-00000000uKA-0KZ2; Sat, 15 Feb 2025 23:39:48 +0000 Received: from sender4-op-o14.zoho.com ([136.143.188.14]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tjRgy-00000000tZp-0SsE; Sat, 15 Feb 2025 23:35:25 +0000 ARC-Seal: i=1; a=rsa-sha256; t=1739662512; cv=none; d=zohomail.com; s=zohoarc; b=aFv4rUM8HzHqC0CcPeHNBZkJLFKYzYUH1zAdZi1xwzOWiS+0Y5ZwTJ0GHv5pHDjFnIuK8EILzPbzt7l8XmGnaPRVzsZURAWVT+Apw+VdtiRtSosb9eoLEXQTgOM9mE1SaVtdm0suq++Ys+A6ZC1he1+M41Hayh1zV/0kzUxm0zA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1739662512; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=8av1iXNMpvlvtcg8scR+m4/u77ONzUeOM2pGww4zkIw=; b=dourin8Sf2DJ9HKzwJcgqVM90jmr/X1u4h9JepWnW3bjVLOvlPswWMEBaBw4AuTypt4Y9AnGtiZO3Cxd0ux6J3yORgDtzN3URFquOyn+iop3/FbrKzIC+F8nxd14GLWw41mHYE2bO3NNtGiGa+oVxn1JWIeJu/K9t0j8T85ttsU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1739662512; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=8av1iXNMpvlvtcg8scR+m4/u77ONzUeOM2pGww4zkIw=; b=kDI5ka04HpnqwELOTw4cEJm+lkj7jT4ASVw/Nf0Ju56JXsREzgZpqW803mE07L92 +9/BuW7kgryJOZ7J9JswByStD9SRV6CXAg6NmkIg8bHHG0PYcMTLN7UStJBwzo/5pTp ds7auqYn2NcEFXF/R/XfodtqG11MTqEbMZKFJgHg= Received: by mx.zohomail.com with SMTPS id 1739662510999466.30832668154085; Sat, 15 Feb 2025 15:35:10 -0800 (PST) From: Nicolas Frattaroli Date: Sun, 16 Feb 2025 00:34:51 +0100 Subject: [PATCH 2/6] arm64: dts: rockchip: Add thermal nodes to RK3576 MIME-Version: 1.0 Message-Id: <20250216-rk3576-tsadc-upstream-v1-2-6ec969322a14@collabora.com> References: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> In-Reply-To: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250215_153524_187824_896EDB15 X-CRM114-Status: GOOD ( 13.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the TSADC node to the RK3576. Additionally, add everything the TSADC needs to function, i.e. thermal zones, their trip points and maps, as well as adjust the CPU cooling-cells property. The polling-delay properties are set to 0 as we do have interrupts for this TSADC on this particular SoC. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 164 ++++++++++++++++++++++++++++++- 1 file changed, 162 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 29b47799849ad50540755d62622865d84226c6c4..73df515a3937414d89515b4ddccf71f33f6a4fe7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3576"; @@ -113,9 +114,9 @@ cpu_l0: cpu@0 { capacity-dmips-mhz = <485>; clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <120>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l1: cpu@1 { @@ -127,6 +128,7 @@ cpu_l1: cpu@1 { clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l2: cpu@2 { @@ -138,6 +140,7 @@ cpu_l2: cpu@2 { clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l3: cpu@3 { @@ -149,6 +152,7 @@ cpu_l3: cpu@3 { clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b0: cpu@100 { @@ -159,9 +163,9 @@ cpu_b0: cpu@100 { capacity-dmips-mhz = <1024>; clocks = <&scmi_clk ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <320>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b1: cpu@101 { @@ -173,6 +177,7 @@ cpu_b1: cpu@101 { clocks = <&scmi_clk ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b2: cpu@102 { @@ -184,6 +189,7 @@ cpu_b2: cpu@102 { clocks = <&scmi_clk ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b3: cpu@103 { @@ -195,6 +201,7 @@ cpu_b3: cpu@103 { clocks = <&scmi_clk ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; idle-states { @@ -431,6 +438,143 @@ psci { method = "smc"; }; + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor for cluster1 (big Cortex-A72 cores) */ + bigcore_thermal: bigcore-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore_alert: bigcore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore_crit: bigcore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor for cluster0 (little Cortex-A53 cores) */ + littlecore_thermal: littlecore-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + gpu_alert: gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr_thermal: ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + ddr_crit: ddr-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -1694,6 +1838,22 @@ saradc: adc@2ae00000 { status = "disabled"; }; + tsadc: tsadc@2ae70000 { + compatible = "rockchip,rk3576-tsadc"; + reg = <0x0 0x2ae70000 0x0 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + }; + i2c9: i2c@2ae80000 { compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0x2ae80000 0x0 0x1000>; From patchwork Sat Feb 15 23:34:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13976264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D0D0C021A0 for ; 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dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1739662516; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=nG2yRgvMP5dkYbP38lgXb6PzBoAUvs3TSS4EYrU79I8=; b=k56Xl7mRjNy1ddOtPV7y/xKt0EnTTf+TvluN+43rC9kYD/sR7KCQA/88w+jQygtO O4urixkbaw7OHkaBunlpJT0Den4KIwLg55C7xkekiqn/yM2rwCnaQyTWECyGHVpysET j2FWX6S3o7pSbpzKxnpkxSEOOI3IWP9zx70XRsDg= Received: by mx.zohomail.com with SMTPS id 1739662515179742.073174152887; Sat, 15 Feb 2025 15:35:15 -0800 (PST) From: Nicolas Frattaroli Date: Sun, 16 Feb 2025 00:34:52 +0100 Subject: [PATCH 3/6] thermal: rockchip: Support RK3576 SoC in the thermal driver MIME-Version: 1.0 Message-Id: <20250216-rk3576-tsadc-upstream-v1-3-6ec969322a14@collabora.com> References: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> In-Reply-To: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli , Ye Zhang X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250215_153527_041531_25795225 X-CRM114-Status: GOOD ( 11.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ye Zhang The RK3576 SoC has six TS-ADC channels: TOP, BIG_CORE, LITTLE_CORE, DDR, NPU and GPU. Signed-off-by: Ye Zhang [ported to mainline, reworded commit message] Signed-off-by: Nicolas Frattaroli --- drivers/thermal/rockchip_thermal.c | 42 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index f551df48eef935757629f4a6b2a619f1506c1cf3..81f11af83f2b215177b93dc11800eb812aa9f1dd 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1060,6 +1060,22 @@ static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); } +static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs, + enum tshut_mode mode) +{ + u32 val_gpio, val_cru; + + if (mode == TSHUT_MODE_GPIO) { + val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_cru = TSADCV2_INT_SRC_EN_MASK(chn); + } else { + val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); + } + writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN); + writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); +} + static const struct rockchip_tsadc_chip px30_tsadc_data = { /* cpu, gpu */ .chn_offset = 0, @@ -1283,6 +1299,28 @@ static const struct rockchip_tsadc_chip rk3568_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rk3576_tsadc_data = { + /* top, big_core, little_core, ddr, npu, gpu */ + .chn_offset = 0, + .chn_num = 6, /* six channels for tsadc */ + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + .initialize = rk_tsadcv8_initialize, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv4_tshut_mode, + .table = { + .id = rk3588_code_table, + .length = ARRAY_SIZE(rk3588_code_table), + .data_mask = TSADCV4_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct rockchip_tsadc_chip rk3588_tsadc_data = { /* top, big_core0, big_core1, little_core, center, gpu, npu */ .chn_offset = 0, @@ -1341,6 +1379,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { .compatible = "rockchip,rk3568-tsadc", .data = (void *)&rk3568_tsadc_data, }, + { + .compatible = "rockchip,rk3576-tsadc", + .data = (void *)&rk3576_tsadc_data, + }, { .compatible = "rockchip,rk3588-tsadc", .data = (void *)&rk3588_tsadc_data, From patchwork Sat Feb 15 23:34:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13976265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6E07C021A0 for ; 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dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1739662520; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=ykTHsvTL+qGG5v5/5FMPfK6N4hOl/V+kaltWfaRofSE=; b=ISc1ttd3t4Zjep98WFy0mkAl/V3p+1YBlSRUbXiixs9gNWDVsR41TS5PF8BuCr+2 kZxilXTIXj7V/9UY8yxv66w1YkLF52Mv4ZVzJKuSdisByNKdy6IYoNMZjK34zWHxzlR C/9Q14QD4fnOWsSMTe2fUnOiSnS3NRSsWi1kdgNs= Received: by mx.zohomail.com with SMTPS id 1739662519156579.278733592755; Sat, 15 Feb 2025 15:35:19 -0800 (PST) From: Nicolas Frattaroli Date: Sun, 16 Feb 2025 00:34:53 +0100 Subject: [PATCH 4/6] dt-bindings: thermal: rockchip: document otp thermal trim MIME-Version: 1.0 Message-Id: <20250216-rk3576-tsadc-upstream-v1-4-6ec969322a14@collabora.com> References: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> In-Reply-To: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250215_153529_920827_6ACF6982 X-CRM114-Status: UNSURE ( 8.39 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Several Rockchip SoCs, such as the RK3576, can store calibration trim data for thermal sensors in OTP cells. This capability should be documented. Such a rockchip thermal sensor may reference cell handles that store both a chip-wide trim for all the sensors, as well as cell handles for each individual sensor channel pointing to that specific sensor's trim value. Additionally, the thermal sensor may optionally reference cells which store the base in terms of degrees celsius and decicelsius that the trim is relative to. Signed-off-by: Nicolas Frattaroli --- .../bindings/thermal/rockchip-thermal.yaml | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index 49ceed68c92ce5a32ed8d4f39bd88fd052de0e80..8d27ddefcc64e29f0faab059888805802c948b41 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -40,6 +40,21 @@ properties: - const: tsadc - const: apb_pclk + nvmem-cells: + items: + - description: cell handle of the low byte of the chip fallback trim value + - description: cell handle of the high byte of the chip fallback trim value + - description: cell handle to where the trim's base temperature is stored + - description: + cell handle to where the trim's tenths of Celsius base value is stored + + nvmem-cell-names: + enum: + - trim_l + - trim_h + - trim_base + - trim_base_frac + resets: minItems: 1 maxItems: 3 @@ -51,6 +66,12 @@ properties: - const: tsadc - const: tsadc-phy + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + "#thermal-sensor-cells": const: 1 @@ -72,6 +93,29 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] +patternProperties: + "^([a-z]+)@[0-9]+$": + type: object + properties: + reg: + maxItems: 1 + description: sensor ID, a.k.a. channel number + + nvmem-cells: + items: + - description: handle of cell containing low byte of calibration data + - description: handle of cell containing high byte of calibration data + + nvmem-cell-names: + items: + - const: trim_l + - const: trim_h + + required: + - reg + + unevaluatedProperties: false + required: - compatible - reg From patchwork Sat Feb 15 23:34:54 2025 Content-Type: text/plain; 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Sat, 15 Feb 2025 15:35:23 -0800 (PST) From: Nicolas Frattaroli Date: Sun, 16 Feb 2025 00:34:54 +0100 Subject: [PATCH 5/6] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes MIME-Version: 1.0 Message-Id: <20250216-rk3576-tsadc-upstream-v1-5-6ec969322a14@collabora.com> References: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> In-Reply-To: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250215_153534_470296_9322D5B4 X-CRM114-Status: GOOD ( 10.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Thanks to Heiko's work getting OTP working on the RK3576, we can specify the thermal sensor trim values which are stored there now, and with my driver addition to rockchip_thermal, we can make use of these. Add them to the devicetree for the SoC. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 75 ++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 73df515a3937414d89515b4ddccf71f33f6a4fe7..c55d7096a3e985d48240c2cab3de572b9ece2b23 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1441,6 +1441,48 @@ gpu_leakage: gpu-leakage@21 { log_leakage: log-leakage@22 { reg = <0x22 0x1>; }; + bigcore_tsadc_trim_l: bigcore-tsadc-trim-l@24 { + reg = <0x24 0x1>; + }; + bigcore_tsadc_trim_h: bigcore-tsadc-trim-h@25 { + reg = <0x25 0x1>; + bits = <0 2>; + }; + litcore_tsadc_trim_l: litcore-tsadc-trim-l@26 { + reg = <0x26 0x1>; + }; + litcore_tsadc_trim_h: litcore-tsadc-trim-h@27 { + reg = <0x27 0x1>; + bits = <0 2>; + }; + ddr_tsadc_trim_l: ddr-tsadc-trim-l@28 { + reg = <0x28 0x1>; + }; + ddr_tsadc_trim_h: ddr-tsadc-trim-h@29 { + reg = <0x29 0x1>; + bits = <0 2>; + }; + npu_tsadc_trim_l: npu-tsadc-trim-l@2a { + reg = <0x2a 0x1>; + }; + npu_tsadc_trim_h: npu-tsadc-trim-h@2b { + reg = <0x2b 0x1>; + bits = <0 2>; + }; + gpu_tsadc_trim_l: gpu-tsadc-trim-l@2c { + reg = <0x2c 0x1>; + }; + gpu_tsadc_trim_h: gpu-tsadc-trim-h@2d { + reg = <0x2d 0x1>; + bits = <0 2>; + }; + soc_tsadc_trim_l: soc-tsadc-trim-l@64 { + reg = <0x64 0x1>; + }; + soc_tsadc_trim_h: soc-tsadc-trim-h@65 { + reg = <0x65 0x1>; + bits = <0 2>; + }; }; gic: interrupt-controller@2a701000 { @@ -1852,6 +1894,39 @@ tsadc: tsadc@2ae70000 { rockchip,hw-tshut-temp = <120000>; rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + #address-cells = <1>; + #size-cells = <0>; + + tsadc@0 { + reg = <0>; + nvmem-cells = <&soc_tsadc_trim_l>, <&soc_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; + tsadc@1 { + reg = <1>; + nvmem-cells = <&bigcore_tsadc_trim_l>, <&bigcore_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; + tsadc@2 { + reg = <2>; + nvmem-cells = <&litcore_tsadc_trim_l>, <&litcore_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; + tsadc@3 { + reg = <3>; + nvmem-cells = <&ddr_tsadc_trim_l>, <&ddr_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; + tsadc@4 { + reg = <4>; + nvmem-cells = <&npu_tsadc_trim_l>, <&npu_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; + tsadc@5 { + reg = <5>; + nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; }; i2c9: i2c@2ae80000 { From patchwork Sat Feb 15 23:34:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 13976268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97A04C021A0 for ; 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dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1739662528; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=rIiQUTbPnBm//PD1F9vMMgdWlYsFfKyxd0qhgz5/CPE=; b=Nt0RGcgS9nPO2/DnHZMcojQAt2JrHspZr6Y3hvadXIkqW6Xz/NcEI1vlIx1VGM9/ ThBO08uQ2rbBYthMaIxqsttEao+xI1RiVQl4/rW0GdmTVeQ7KqtSrVmvC5O7ibby/UC /MCLne57PQNKXGOOr1uA8bR73r1inMPxGtkBEMVI= Received: by mx.zohomail.com with SMTPS id 1739662527392816.652601948843; Sat, 15 Feb 2025 15:35:27 -0800 (PST) From: Nicolas Frattaroli Date: Sun, 16 Feb 2025 00:34:55 +0100 Subject: [PATCH 6/6] thermal: rockchip: support reading trim values from OTP MIME-Version: 1.0 Message-Id: <20250216-rk3576-tsadc-upstream-v1-6-6ec969322a14@collabora.com> References: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> In-Reply-To: <20250216-rk3576-tsadc-upstream-v1-0-6ec969322a14@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250215_153539_695068_703902BB X-CRM114-Status: GOOD ( 32.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Many of the Rockchip SoCs support storing trim values for the sensors in factory programmable memory. These values specify a fixed offset from the sensor's returned temperature to get a more accurate picture of what temperature the silicon is actually at. The way this is implemented is with various OTP cells, which may be absent. There may both be whole-TSADC trim values, as well as per-sensor trim values. In the downstream driver, whole-chip trim values override the per-sensor trim values. This rewrite of the functionality changes the semantics to something I see as slightly more useful: allow the whole-chip trim values to serve as a fallback for lacking per-sensor trim values, instead of overriding already present sensor trim values. Additionally, the chip may specify an offset (trim_base, trim_base_frac) in degrees celsius and degrees decicelsius respectively which defines what the basis is from which the trim, if any, should be calculated from. By default, this is 30 degrees Celsius, but the chip can once again specify a different value through OTP cells. The implementation of these trim calculations have been tested extensively on an RK3576, where it was confirmed to get rid of pesky 1.8 degree Celsius offsets between certain sensors. Signed-off-by: Nicolas Frattaroli --- drivers/thermal/rockchip_thermal.c | 238 +++++++++++++++++++++++++++++++++---- 1 file changed, 216 insertions(+), 22 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 81f11af83f2b215177b93dc11800eb812aa9f1dd..177fa53d46dbe7dce7d0d1b0c527da9a0313b2fc 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -69,16 +70,18 @@ struct chip_tsadc_table { * struct rockchip_tsadc_chip - hold the private data of tsadc chip * @chn_offset: the channel offset of the first channel * @chn_num: the channel number of tsadc chip - * @tshut_temp: the hardware-controlled shutdown temperature value + * @trim_slope: used to convert the trim code to a temperature in millicelsius + * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) * @initialize: SoC special initialize tsadc controller method * @irq_ack: clear the interrupt * @control: enable/disable method for the tsadc controller - * @get_temp: get the temperature + * @get_temp: get the raw temperature, unadjusted by trim * @set_alarm_temp: set the high temperature interrupt * @set_tshut_temp: set the hardware-controlled shutdown temperature * @set_tshut_mode: set the hardware-controlled shutdown mode + * @get_trim_code: convert a hardware temperature code to one adjusted for by trim * @table: the chip-specific conversion table */ struct rockchip_tsadc_chip { @@ -86,6 +89,9 @@ struct rockchip_tsadc_chip { int chn_offset; int chn_num; + /* Used to convert trim code to trim temp */ + int trim_slope; + /* The hardware-controlled tshut property */ int tshut_temp; enum tshut_mode tshut_mode; @@ -105,6 +111,8 @@ struct rockchip_tsadc_chip { int (*set_tshut_temp)(const struct chip_tsadc_table *table, int chn, void __iomem *reg, int temp); void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); + int (*get_trim_code)(const struct chip_tsadc_table *table, + int code, int trim_base, int trim_base_frac); /* Per-table methods */ struct chip_tsadc_table table; @@ -114,12 +122,16 @@ struct rockchip_tsadc_chip { * struct rockchip_thermal_sensor - hold the information of thermal sensor * @thermal: pointer to the platform/configuration data * @tzd: pointer to a thermal zone + * @of_node: pointer to the device_node representing this sensor, if any * @id: identifier of the thermal sensor + * @trim_temp: per-sensor trim temperature value */ struct rockchip_thermal_sensor { struct rockchip_thermal_data *thermal; struct thermal_zone_device *tzd; + struct device_node *of_node; int id; + int trim_temp; }; /** @@ -132,7 +144,12 @@ struct rockchip_thermal_sensor { * @pclk: the advanced peripherals bus clock * @grf: the general register file will be used to do static set by software * @regs: the base address of tsadc controller - * @tshut_temp: the hardware-controlled shutdown temperature value + * @trim_base: major component of sensor trim value, in Celsius + * @trim_base_frac: minor component of sensor trim value, in Decicelsius + * @trim_h: upper part of fallback trim value for each channel + * @trim_l: lower part of fallback trim value for each channel + * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim + * @trim_temp: the fallback trim temperature for the whole sensor * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) */ @@ -149,7 +166,13 @@ struct rockchip_thermal_data { struct regmap *grf; void __iomem *regs; + int trim_base; + int trim_base_frac; + int trim_h; + int trim_l; + int tshut_temp; + int trim_temp; enum tshut_mode tshut_mode; enum tshut_polarity tshut_polarity; }; @@ -249,6 +272,9 @@ struct rockchip_thermal_data { #define GRF_CON_TSADC_CH_INV (0x10001 << 1) + +#define RK_MAX_TEMP (180000) + /** * struct tsadc_table - code to temperature conversion table * @code: the value of adc channel @@ -1076,6 +1102,15 @@ static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs, writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); } +static int rk_tsadcv2_get_trim_code(const struct chip_tsadc_table *table, + int code, int trim_base, int trim_base_frac) +{ + int temp = trim_base * 1000 + trim_base_frac * 100; + u32 base_code = rk_tsadcv2_temp_to_code(table, temp); + + return code - base_code; +} + static const struct rockchip_tsadc_chip px30_tsadc_data = { /* cpu, gpu */ .chn_offset = 0, @@ -1313,6 +1348,8 @@ static const struct rockchip_tsadc_chip rk3576_tsadc_data = { .set_alarm_temp = rk_tsadcv3_alarm_temp, .set_tshut_temp = rk_tsadcv3_tshut_temp, .set_tshut_mode = rk_tsadcv4_tshut_mode, + .get_trim_code = rk_tsadcv2_get_trim_code, + .trim_slope = 923, .table = { .id = rk3588_code_table, .length = ARRAY_SIZE(rk3588_code_table), @@ -1424,11 +1461,8 @@ static int rockchip_thermal_set_trips(struct thermal_zone_device *tz, int low, i struct rockchip_thermal_data *thermal = sensor->thermal; const struct rockchip_tsadc_chip *tsadc = thermal->chip; - dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", - __func__, sensor->id, low, high); - return tsadc->set_alarm_temp(&tsadc->table, - sensor->id, thermal->regs, high); + sensor->id, thermal->regs, high + sensor->trim_temp); } static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_temp) @@ -1440,6 +1474,8 @@ static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_te retval = tsadc->get_temp(&tsadc->table, sensor->id, thermal->regs, out_temp); + *out_temp -= sensor->trim_temp; + return retval; } @@ -1448,6 +1484,108 @@ static const struct thermal_zone_device_ops rockchip_of_thermal_ops = { .set_trips = rockchip_thermal_set_trips, }; +/** + * rockchip_get_efuse_value - read an OTP cell from a device node + * @np: pointer to the device node with the nvmem-cells property + * @cell_name: name of cell that should be read + * @value: pointer to where the read value will be placed + * + * Return: Negative errno on failure, during which *value will not be touched, + * or 0 on success. + */ +static int rockchip_get_efuse_value(struct device_node *np, const char *cell_name, + int *value) +{ + struct nvmem_cell *cell; + int ret = 0; + size_t len; + u8 *buf; + int i; + + cell = of_nvmem_cell_get(np, cell_name); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + buf = nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len > sizeof(*value)) { + ret = -ERANGE; + goto exit; + } + + /* Copy with implicit endian conversion */ + *value = 0; + for (i = 0; i < len; i++) + *value |= (int) buf[i] << (8 * i); + +exit: + kfree(buf); + return ret; +} + +static int rockchip_get_trim_configuration(struct device *dev, struct device_node *np, + struct rockchip_thermal_data *thermal) +{ + const struct rockchip_tsadc_chip *tsadc = thermal->chip; + int trim_base = 0, trim_base_frac = 0, trim_l = 0, trim_h = 0; + int trim_code; + int ret; + + thermal->trim_base = 0; + thermal->trim_base_frac = 0; + thermal->trim_l = 0; + thermal->trim_h = 0; + + if (!tsadc->get_trim_code) + return 0; + + ret = rockchip_get_efuse_value(np, "trim_base", &trim_base); + if (ret < 0) { + if (ret == -ENOENT) { + trim_base = 30; + dev_dbg(dev, "trim_base is absent, defaulting to 30\n"); + } else { + dev_err(dev, "failed reading nvmem value of trim_base: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + ret = rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac); + if (ret < 0) { + if (ret == -ENOENT) { + dev_dbg(dev, "trim_base_frac is absent, defaulting to 0\n"); + } else { + dev_err(dev, "failed reading nvmem value of trim_base_frac: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + thermal->trim_base = trim_base; + thermal->trim_base_frac = trim_base_frac; + + /* + * If the tsadc node contains the trim_h and trim_l properties, then it + * is used in the absence of per-channel trim values + */ + if (!rockchip_get_efuse_value(np, "trim_l", &trim_l)) + thermal->trim_l = trim_l; + if (!rockchip_get_efuse_value(np, "trim_h", &trim_h)) + thermal->trim_h = trim_h; + if (trim_h > 0 || trim_l > 0) { + trim_code = tsadc->get_trim_code(&tsadc->table, + (trim_h << 8) | trim_l, + trim_base, trim_base_frac); + thermal->trim_temp = thermal->chip->trim_slope * trim_code; + } + + return 0; +} + static int rockchip_configure_from_dt(struct device *dev, struct device_node *np, struct rockchip_thermal_data *thermal) @@ -1508,6 +1646,8 @@ static int rockchip_configure_from_dt(struct device *dev, if (IS_ERR(thermal->grf)) dev_warn(dev, "Missing rockchip,grf property\n"); + rockchip_get_trim_configuration(dev, np, thermal); + return 0; } @@ -1518,23 +1658,58 @@ rockchip_thermal_register_sensor(struct platform_device *pdev, int id) { const struct rockchip_tsadc_chip *tsadc = thermal->chip; + struct device *dev = &pdev->dev; + int trim_l = thermal->trim_l; + int trim_h = thermal->trim_h; + int trim_code, tshut_temp; + int trim_temp = 0; int error; + if (thermal->trim_temp) + trim_temp = thermal->trim_temp; + + if (tsadc->get_trim_code && sensor->of_node) { + error = rockchip_get_efuse_value(sensor->of_node, "trim_l", &trim_l); + if (error < 0 && error != -ENOENT) { + dev_err(dev, "failed reading trim_l of sensor %d: %pe\n", + id, ERR_PTR(error)); + return error; + } + error = rockchip_get_efuse_value(sensor->of_node, "trim_h", &trim_h); + if (error < 0 && error != -ENOENT) { + dev_err(dev, "failed reading trim_h of sensor %d: %pe\n", + id, ERR_PTR(error)); + return error; + } + if (trim_h > 0 || trim_l > 0) { + trim_code = tsadc->get_trim_code(&tsadc->table, + (trim_h << 8) | trim_l, + thermal->trim_base, + thermal->trim_base_frac); + trim_temp = thermal->chip->trim_slope * trim_code; + } + } + + sensor->trim_temp = trim_temp; + + dev_dbg(dev, "trim of sensor %d is %d\n", id, sensor->trim_temp); + + tshut_temp = min(thermal->tshut_temp + sensor->trim_temp, RK_MAX_TEMP); + tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); - error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, - thermal->tshut_temp); + error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, tshut_temp); if (error) - dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", - __func__, thermal->tshut_temp, error); + dev_err(dev, "%s: invalid tshut=%d, error=%d\n", + __func__, tshut_temp, error); sensor->thermal = thermal; sensor->id = id; - sensor->tzd = devm_thermal_of_zone_register(&pdev->dev, id, sensor, + sensor->tzd = devm_thermal_of_zone_register(dev, id, sensor, &rockchip_of_thermal_ops); if (IS_ERR(sensor->tzd)) { error = PTR_ERR(sensor->tzd); - dev_err(&pdev->dev, "failed to register sensor %d: %d\n", + dev_err(dev, "failed to register sensor %d: %d\n", id, error); return error; } @@ -1557,9 +1732,11 @@ static int rockchip_thermal_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct rockchip_thermal_data *thermal; + struct device_node *child; int irq; int i; int error; + u32 chn; irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -1610,6 +1787,18 @@ static int rockchip_thermal_probe(struct platform_device *pdev) thermal->chip->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); + for_each_available_child_of_node(np, child) { + if (!of_property_read_u32(child, "reg", &chn)) { + if (chn < thermal->chip->chn_num) + thermal->sensors[chn].of_node = child; + else + dev_warn(&pdev->dev, + "sensor address (%d) too large, ignoring its trim\n", + chn); + } + + } + for (i = 0; i < thermal->chip->chn_num; i++) { error = rockchip_thermal_register_sensor(pdev, thermal, &thermal->sensors[i], @@ -1679,8 +1868,11 @@ static int __maybe_unused rockchip_thermal_suspend(struct device *dev) static int __maybe_unused rockchip_thermal_resume(struct device *dev) { struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); - int i; + const struct rockchip_tsadc_chip *tsadc = thermal->chip; + struct rockchip_thermal_sensor *sensor; + int tshut_temp; int error; + int i; error = clk_enable(thermal->clk); if (error) @@ -1694,21 +1886,23 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev) rockchip_thermal_reset_controller(thermal->reset); - thermal->chip->initialize(thermal->grf, thermal->regs, - thermal->tshut_polarity); + tsadc->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); for (i = 0; i < thermal->chip->chn_num; i++) { - int id = thermal->sensors[i].id; + sensor = &thermal->sensors[i]; + + tshut_temp = min(thermal->tshut_temp + sensor->trim_temp, + RK_MAX_TEMP); - thermal->chip->set_tshut_mode(id, thermal->regs, + tsadc->set_tshut_mode(sensor->id, thermal->regs, thermal->tshut_mode); - error = thermal->chip->set_tshut_temp(&thermal->chip->table, - id, thermal->regs, - thermal->tshut_temp); + error = tsadc->set_tshut_temp(&thermal->chip->table, + sensor->id, thermal->regs, + tshut_temp); if (error) dev_err(dev, "%s: invalid tshut=%d, error=%d\n", - __func__, thermal->tshut_temp, error); + __func__, tshut_temp, error); } thermal->chip->control(thermal->regs, true);