From patchwork Mon Feb 17 07:00:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13977177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9691C021A0 for ; Mon, 17 Feb 2025 07:00:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D39010E375; Mon, 17 Feb 2025 07:00:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UIo3xW7F"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 163DA10E37D; Mon, 17 Feb 2025 07:00:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739775654; x=1771311654; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K6HIgMdjre2uqCZgYogyWGI9TdGSS4JOwwxeb3HpUds=; b=UIo3xW7FQojpKYKiAyFIe+3zDHpkNc5nDm/D3OMKlENalT4QCM9LS+8V t4Qh5U3G2avXWuaZqUfL4M7krSp+pPdIO7IA1ONsoA5TENpuKSFAK/LW3 PlF02T7SVKxwvO0avqyaPHC/fSPn/NaJkEzilTyVw24aSSfqDf8T0CojM mHbpLkbOUQwQuImWZOhAYXQ1+TplVpfHt5CyBknkIAtyoOieXpKyTEGP1 TOG+obOB9j1Ctf+8AwvTRQRc88ceerqfg9qqb3CzxSPRaFUWDZ+UIti5R j2Iav2ql9lSjWlKsf9nssTLniwgzc2IewKdii1esOpIj+ouIU1NFKG4Ay A==; X-CSE-ConnectionGUID: HQVr/algTrSfZvo++oqfjg== X-CSE-MsgGUID: Yq9eU3PzSJaYEDK/aOvhAQ== X-IronPort-AV: E=McAfee;i="6700,10204,11347"; a="39676244" X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="39676244" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2025 23:00:53 -0800 X-CSE-ConnectionGUID: vK8kjcz6SqOrGAxJfwR1KQ== X-CSE-MsgGUID: Dw8WxfarRB2ZJrd5GI/97Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="114233349" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 16 Feb 2025 23:00:51 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 09:00:50 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Vinod Govindapillai Subject: [PATCH v2 1/8] drm/i915: Add missing else to the if ladder in missing else Date: Mon, 17 Feb 2025 09:00:40 +0200 Message-ID: <20250217070047.953-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250217070047.953-1-ville.syrjala@linux.intel.com> References: <20250217070047.953-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The if ladder in gen8_de_pipe_fault_mask() was missing one else, add it. Doesn't actually matter since each if branch just returns directly. But the code is less confusing when you always do things the same way. Reviewed-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 880eaed83cd5..d3ba8e2cf5a1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -908,7 +908,7 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) GEN9_PIPE_PLANE3_FAULT | GEN9_PIPE_PLANE2_FAULT | GEN9_PIPE_PLANE1_FAULT; - if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) + else if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) return GEN12_PIPEDMC_FAULT | GEN9_PIPE_CURSOR_FAULT | GEN11_PIPE_PLANE5_FAULT | From patchwork Mon Feb 17 07:00:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13977178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86F2EC021A4 for ; Mon, 17 Feb 2025 07:00:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2170E10E37E; Mon, 17 Feb 2025 07:00:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OL4KwKa4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id D0B4B10E37E; Mon, 17 Feb 2025 07:00:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739775657; x=1771311657; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s77FXiKdgdgE5WXes6kt/HkXrgUx3/1ERmmBksC9opw=; b=OL4KwKa4zqliFbs8QIEHxaeMqughM7dCoy2Bs4q95BrPgMPMn5tU7b88 n0Mwp1K35hjqAnsLhQVllKlasEIrvGe54RRw6L/+vBvQutZcVd2hfpJVz nTX2GqH+KPQ/x+QAqBj6IMnD1/5xtMFN/omxK6wB4kJZsWRspRQSVKLUX i64MLa1UeOXPGUQQxvNMprIJkeatWFvqDMR5MJY9GXTTVh2YevbJ31klC PCFybJnKrl00C7ndBhgE6VkFDQ6RSYc8I1R3Tb95lNUlohQ39RvFJFDpl prHwTDEwr+7I8ILzKYm5LvCeNVq3Miy4QaZZHVjRcuvVJcg8KYY7H9Ajm A==; X-CSE-ConnectionGUID: kGPiv0oFSSeCdoySDb/yvg== X-CSE-MsgGUID: Wa0PwAnyQ7Kc7MNnmICHoA== X-IronPort-AV: E=McAfee;i="6700,10204,11347"; a="39676250" X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="39676250" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2025 23:00:57 -0800 X-CSE-ConnectionGUID: sVD7mHeFTjmk6K4nSBn/2w== X-CSE-MsgGUID: 2wRT57xySfmD1ESEX3C7aA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="114233368" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 16 Feb 2025 23:00:54 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 09:00:53 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Vinod Govindapillai Subject: [PATCH v2 2/8] drm/i915: Introduce a minimal plane error state Date: Mon, 17 Feb 2025 09:00:41 +0200 Message-ID: <20250217070047.953-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250217070047.953-1-ville.syrjala@linux.intel.com> References: <20250217070047.953-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä I want to capture a little bit more information about the state of the plane upon faults. To that end introduce a small plane error state struct and provide per-plane vfuncs to read it out. For now we just stick the CTL, SURF, and SURFLIVE (if available) registers contents in there. v2: Use struct intel_display instead of dev_priv Reviewed-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 41 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_cursor.c | 26 ++++++++++++ .../drm/i915/display/intel_display_types.h | 7 ++++ drivers/gpu/drm/i915/display/intel_sprite.c | 36 ++++++++++++++++ .../drm/i915/display/skl_universal_plane.c | 12 ++++++ 5 files changed, 122 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index aef8d8b7ea85..013295f66d56 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -557,6 +557,40 @@ static void i9xx_plane_disable_arm(struct intel_dsb *dsb, intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 0); } +static void g4x_primary_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + + error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); + error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane)); + error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane)); +} + +static void i965_plane_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + + error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); + error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane)); +} + +static void i8xx_plane_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + + error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); + error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane)); +} + static void g4x_primary_async_flip(struct intel_dsb *dsb, struct intel_plane *plane, @@ -976,6 +1010,13 @@ intel_primary_plane_create(struct intel_display *display, enum pipe pipe) plane->get_hw_state = i9xx_plane_get_hw_state; plane->check_plane = i9xx_plane_check; + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) + plane->capture_error = g4x_primary_capture_error; + else if (DISPLAY_VER(display) >= 4) + plane->capture_error = i965_plane_capture_error; + else + plane->capture_error = i8xx_plane_capture_error; + if (HAS_ASYNC_FLIPS(display)) { if (display->platform.valleyview || display->platform.cherryview) { plane->async_flip = vlv_primary_async_flip; diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index f31efac89e95..3276a5b4a9b0 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -765,6 +765,27 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, return ret; } +static void g4x_cursor_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe)); + error->surf = intel_de_read(display, CURBASE(display, crtc->pipe)); + error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe)); +} + +static void i9xx_cursor_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe)); + error->surf = intel_de_read(display, CURBASE(display, crtc->pipe)); +} + static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { @@ -1030,6 +1051,11 @@ intel_cursor_plane_create(struct intel_display *display, cursor->check_plane = i9xx_check_cursor; } + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) + cursor->capture_error = g4x_cursor_capture_error; + else + cursor->capture_error = i9xx_cursor_capture_error; + cursor->cursor.base = ~0; cursor->cursor.cntl = ~0; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 6c1c88ed0ba6..a4e3f33f75eb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1437,6 +1437,10 @@ struct intel_crtc { bool block_dc_for_vblank; }; +struct intel_plane_error { + u32 ctl, surf, surflive; +}; + struct intel_plane { struct drm_plane base; enum i9xx_plane_id i9xx_plane; @@ -1488,6 +1492,9 @@ struct intel_plane { void (*disable_arm)(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state); + void (*capture_error)(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error); bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); int (*check_plane)(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state); diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index ab5bc8a08f0f..1ad6c8a94b3d 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -447,6 +447,17 @@ vlv_sprite_disable_arm(struct intel_dsb *dsb, intel_de_write_fw(display, SPSURF(pipe, plane_id), 0); } +static void vlv_sprite_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id)); + error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id)); + error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id)); +} + static bool vlv_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) @@ -872,6 +883,17 @@ ivb_sprite_disable_arm(struct intel_dsb *dsb, intel_de_write_fw(display, SPRSURF(pipe), 0); } +static void ivb_sprite_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, SPRCTL(crtc->pipe)); + error->surf = intel_de_read(display, SPRSURF(crtc->pipe)); + error->surflive = intel_de_read(display, SPRSURFLIVE(crtc->pipe)); +} + static bool ivb_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) @@ -1207,6 +1229,17 @@ g4x_sprite_disable_arm(struct intel_dsb *dsb, intel_de_write_fw(display, DVSSURF(pipe), 0); } +static void g4x_sprite_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, DVSCNTR(crtc->pipe)); + error->surf = intel_de_read(display, DVSSURF(crtc->pipe)); + error->surflive = intel_de_read(display, DVSSURFLIVE(crtc->pipe)); +} + static bool g4x_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) @@ -1587,6 +1620,7 @@ intel_sprite_plane_create(struct intel_display *display, plane->update_noarm = vlv_sprite_update_noarm; plane->update_arm = vlv_sprite_update_arm; plane->disable_arm = vlv_sprite_disable_arm; + plane->capture_error = vlv_sprite_capture_error; plane->get_hw_state = vlv_sprite_get_hw_state; plane->check_plane = vlv_sprite_check; plane->max_stride = i965_plane_max_stride; @@ -1610,6 +1644,7 @@ intel_sprite_plane_create(struct intel_display *display, plane->update_noarm = ivb_sprite_update_noarm; plane->update_arm = ivb_sprite_update_arm; plane->disable_arm = ivb_sprite_disable_arm; + plane->capture_error = ivb_sprite_capture_error; plane->get_hw_state = ivb_sprite_get_hw_state; plane->check_plane = g4x_sprite_check; @@ -1634,6 +1669,7 @@ intel_sprite_plane_create(struct intel_display *display, plane->update_noarm = g4x_sprite_update_noarm; plane->update_arm = g4x_sprite_update_arm; plane->disable_arm = g4x_sprite_disable_arm; + plane->capture_error = g4x_sprite_capture_error; plane->get_hw_state = g4x_sprite_get_hw_state; plane->check_plane = g4x_sprite_check; plane->max_stride = g4x_sprite_max_stride; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 110f66dd5cf0..cd9762947f1d 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1661,6 +1661,17 @@ icl_plane_update_arm(struct intel_dsb *dsb, skl_plane_surf(plane_state, color_plane)); } +static void skl_plane_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id)); + error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id)); + error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id)); +} + static void skl_plane_async_flip(struct intel_dsb *dsb, struct intel_plane *plane, @@ -2803,6 +2814,7 @@ skl_universal_plane_create(struct intel_display *display, plane->update_arm = skl_plane_update_arm; plane->disable_arm = skl_plane_disable_arm; } + plane->capture_error = skl_plane_capture_error; plane->get_hw_state = skl_plane_get_hw_state; plane->check_plane = skl_plane_check; From patchwork Mon Feb 17 07:00:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13977179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 060FDC021A6 for ; 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X-CSE-ConnectionGUID: aKvVkbr7TaG0vtjIZin8IA== X-CSE-MsgGUID: ZT4S0YMBTL6tPOjRw6eiHQ== X-IronPort-AV: E=McAfee;i="6700,10204,11347"; a="39676256" X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="39676256" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2025 23:01:00 -0800 X-CSE-ConnectionGUID: D0NyPdYFSvy0sRN9N4OGrw== X-CSE-MsgGUID: UEcigzpKS/66EcMsw2PDxw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="114233386" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 16 Feb 2025 23:00:57 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 09:00:56 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Vinod Govindapillai Subject: [PATCH v2 3/8] drm/i915: Pimp display fault reporting Date: Mon, 17 Feb 2025 09:00:42 +0200 Message-ID: <20250217070047.953-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250217070047.953-1-ville.syrjala@linux.intel.com> References: <20250217070047.953-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Decode the display faults a bit more extensively so that one doesn't have to translate the bitmask to planes/etc. manually. Also for plane faults we can read out a bit of state from the relevant plane(s) and dump that out. Reviewed-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +- .../gpu/drm/i915/display/intel_atomic_plane.h | 2 + .../gpu/drm/i915/display/intel_display_irq.c | 156 +++++++++++++++++- 3 files changed, 155 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index aecff35d0ce2..124cd9ddba0b 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -682,7 +682,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ old_plane_state, new_plane_state); } -static struct intel_plane * +struct intel_plane * intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index d21eb7699dbd..65edd88d28a9 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -19,6 +19,8 @@ struct intel_plane; struct intel_plane_state; enum plane_id; +struct intel_plane * +intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id); bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier); unsigned int intel_adjusted_rate(const struct drm_rect *src, const struct drm_rect *dst, diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index d3ba8e2cf5a1..8c73dc872384 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -10,6 +10,7 @@ #include "i915_irq.h" #include "i915_reg.h" #include "icl_dsi_regs.h" +#include "intel_atomic_plane.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_irq.h" @@ -67,6 +68,52 @@ intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_re intel_dmc_wl_put(display, reg); } +struct pipe_fault_handler { + bool (*handle)(struct intel_crtc *crtc, enum plane_id plane_id); + u32 fault; + enum plane_id plane_id; +}; + +static bool handle_plane_fault(struct intel_crtc *crtc, enum plane_id plane_id) +{ + struct intel_display *display = to_intel_display(crtc); + struct intel_plane_error error = {}; + struct intel_plane *plane; + + plane = intel_crtc_get_plane(crtc, plane_id); + if (!plane || !plane->capture_error) + return false; + + plane->capture_error(crtc, plane, &error); + + drm_err_ratelimited(display->drm, + "[CRTC:%d:%s][PLANE:%d:%s] fault (CTL=0x%x, SURF=0x%x, SURFLIVE=0x%x)\n", + crtc->base.base.id, crtc->base.name, + plane->base.base.id, plane->base.name, + error.ctl, error.surf, error.surflive); + + return true; +} + +static void intel_pipe_fault_irq_handler(struct intel_display *display, + const struct pipe_fault_handler *handlers, + enum pipe pipe, u32 fault_errors) +{ + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); + const struct pipe_fault_handler *handler; + + for (handler = handlers; handler && handler->fault; handler++) { + if ((fault_errors & handler->fault) == 0) + continue; + + if (handler->handle(crtc, handler->plane_id)) + fault_errors &= ~handler->fault; + } + + WARN_ONCE(fault_errors, "[CRTC:%d:%s] unreported faults 0x%x\n", + crtc->base.base.id, crtc->base.name, fault_errors); +} + static void intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) { @@ -947,6 +994,108 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) GEN8_PIPE_PRIMARY_FAULT; } +static bool handle_plane_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) +{ + struct intel_display *display = to_intel_display(crtc); + + drm_err_ratelimited(display->drm, + "[CRTC:%d:%s] PLANE ATS fault\n", + crtc->base.base.id, crtc->base.name); + + return false; +} + +static bool handle_pipedmc_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) +{ + struct intel_display *display = to_intel_display(crtc); + + drm_err_ratelimited(display->drm, + "[CRTC:%d:%s] PIPEDMC ATS fault\n", + crtc->base.base.id, crtc->base.name); + + return false; +} + +static bool handle_pipedmc_fault(struct intel_crtc *crtc, enum plane_id plane_id) +{ + struct intel_display *display = to_intel_display(crtc); + + drm_err_ratelimited(display->drm, + "[CRTC:%d:%s] PIPEDMC fault\n", + crtc->base.base.id, crtc->base.name); + + return false; +} + +static const struct pipe_fault_handler mtl_pipe_fault_handlers[] = { + { .fault = MTL_PLANE_ATS_FAULT, .handle = handle_plane_ats_fault, }, + { .fault = MTL_PIPEDMC_ATS_FAULT, .handle = handle_pipedmc_ats_fault, }, + { .fault = GEN12_PIPEDMC_FAULT, .handle = handle_pipedmc_fault, }, + { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, + { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, + { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, + { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, + { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, + { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler tgl_pipe_fault_handlers[] = { + { .fault = GEN12_PIPEDMC_FAULT, .handle = handle_pipedmc_fault, }, + { .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, }, + { .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, }, + { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, + { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, + { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, + { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, + { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, + { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler icl_pipe_fault_handlers[] = { + { .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, }, + { .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, }, + { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, + { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, + { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, + { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, + { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, + { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler skl_pipe_fault_handlers[] = { + { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, + { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, + { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, + { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, + { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler bdw_pipe_fault_handlers[] = { + { .fault = GEN8_PIPE_SPRITE_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = GEN8_PIPE_PRIMARY_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = GEN8_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler * +gen8_pipe_fault_handlers(struct intel_display *display) +{ + if (DISPLAY_VER(display) >= 14) + return mtl_pipe_fault_handlers; + else if (DISPLAY_VER(display) >= 12) + return tgl_pipe_fault_handlers; + else if (DISPLAY_VER(display) >= 11) + return icl_pipe_fault_handlers; + else if (DISPLAY_VER(display) >= 9) + return skl_pipe_fault_handlers; + else + return bdw_pipe_fault_handlers; +} + static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv) { wake_up_all(&dev_priv->display.pmdemand.waitqueue); @@ -1233,10 +1382,9 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); if (fault_errors) - drm_err_ratelimited(&dev_priv->drm, - "Fault errors on pipe %c: 0x%08x\n", - pipe_name(pipe), - fault_errors); + intel_pipe_fault_irq_handler(display, + gen8_pipe_fault_handlers(display), + pipe, fault_errors); } if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && From patchwork Mon Feb 17 07:00:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13977180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83018C021A6 for ; Mon, 17 Feb 2025 07:01:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2525710E386; 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X-CSE-ConnectionGUID: bVlTNd0BTsuXFNUVn2KTvw== X-CSE-MsgGUID: NfOJ28BzS0+tJHbk6g5Zow== X-IronPort-AV: E=McAfee;i="6700,10204,11347"; a="39676260" X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="39676260" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2025 23:01:03 -0800 X-CSE-ConnectionGUID: XBUYuFrlSfmTquG7/t355g== X-CSE-MsgGUID: MTS3I1EJTe+rbUTq3nqJTg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="114233424" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 16 Feb 2025 23:01:00 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 09:00:59 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Vinod Govindapillai Subject: [PATCH v2 4/8] drm/i915: Hook in display GTT faults for IVB/HSW Date: Mon, 17 Feb 2025 09:00:43 +0200 Message-ID: <20250217070047.953-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250217070047.953-1-ville.syrjala@linux.intel.com> References: <20250217070047.953-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Dump out the display fault information from the IVB/HSW error interrupt handler. Bspec: 8203 Reviewed-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_display_irq.c | 46 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 11 +++++ 2 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 8c73dc872384..cd53008ab590 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -720,6 +720,39 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) intel_pch_fifo_underrun_irq_handler(display, PIPE_B); } +static u32 ivb_err_int_pipe_fault_mask(enum pipe pipe) +{ + switch (pipe) { + case PIPE_A: + return ERR_INT_SPRITE_A_FAULT | + ERR_INT_PRIMARY_A_FAULT | + ERR_INT_CURSOR_A_FAULT; + case PIPE_B: + return ERR_INT_SPRITE_B_FAULT | + ERR_INT_PRIMARY_B_FAULT | + ERR_INT_CURSOR_B_FAULT; + case PIPE_C: + return ERR_INT_SPRITE_C_FAULT | + ERR_INT_PRIMARY_C_FAULT | + ERR_INT_CURSOR_C_FAULT; + default: + return 0; + } +} + +static const struct pipe_fault_handler ivb_pipe_fault_handlers[] = { + { .fault = ERR_INT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = ERR_INT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = ERR_INT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = ERR_INT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = ERR_INT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = ERR_INT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = ERR_INT_SPRITE_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = ERR_INT_PRIMARY_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = ERR_INT_CURSOR_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + static void ivb_err_int_handler(struct drm_i915_private *dev_priv) { struct intel_display *display = &dev_priv->display; @@ -729,7 +762,15 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv) if (err_int & ERR_INT_POISON) drm_err(&dev_priv->drm, "Poison interrupt\n"); + if (err_int & ERR_INT_INVALID_GTT_PTE) + drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); + + if (err_int & ERR_INT_INVALID_PTE_DATA) + drm_err_ratelimited(display->drm, "Invalid PTE data\n"); + for_each_pipe(dev_priv, pipe) { + u32 fault_errors; + if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) intel_cpu_fifo_underrun_irq_handler(display, pipe); @@ -739,6 +780,11 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv) else hsw_pipe_crc_irq_handler(dev_priv, pipe); } + + fault_errors = err_int & ivb_err_int_pipe_fault_mask(pipe); + if (fault_errors) + intel_pipe_fault_irq_handler(display, ivb_pipe_fault_handlers, + pipe, fault_errors); } intel_de_write(display, GEN7_ERR_INT, err_int); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3a936a4aa2e8..b8756e5d2cae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -374,6 +374,17 @@ #define GEN7_ERR_INT _MMIO(0x44040) #define ERR_INT_POISON (1 << 31) +#define ERR_INT_INVALID_GTT_PTE (1 << 29) +#define ERR_INT_INVALID_PTE_DATA (1 << 28) +#define ERR_INT_SPRITE_C_FAULT (1 << 23) +#define ERR_INT_PRIMARY_C_FAULT (1 << 22) +#define ERR_INT_CURSOR_C_FAULT (1 << 21) +#define ERR_INT_SPRITE_B_FAULT (1 << 20) +#define ERR_INT_PRIMARY_B_FAULT (1 << 19) +#define ERR_INT_CURSOR_B_FAULT (1 << 18) +#define ERR_INT_SPRITE_A_FAULT (1 << 17) +#define ERR_INT_PRIMARY_A_FAULT (1 << 16) +#define ERR_INT_CURSOR_A_FAULT (1 << 15) #define ERR_INT_MMIO_UNCLAIMED (1 << 13) #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) From patchwork Mon Feb 17 07:00:44 2025 Content-Type: text/plain; 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16 Feb 2025 23:01:06 -0800 X-CSE-ConnectionGUID: CYuCD7LyQZKV774+EFsz8Q== X-CSE-MsgGUID: c7fDNh2gRXWkO3ROVH/FAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="114233455" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 16 Feb 2025 23:01:03 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 09:01:03 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Vinod Govindapillai Subject: [PATCH v2 5/8] drm/i915: Hook in display GTT faults for ILK/SNB Date: Mon, 17 Feb 2025 09:00:44 +0200 Message-ID: <20250217070047.953-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250217070047.953-1-ville.syrjala@linux.intel.com> References: <20250217070047.953-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Hook up display GTT fault interrupts for ILK/SNB. Bspec: 8559 Reviewed-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_display_irq.c | 56 ++++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 10 ++++ 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index cd53008ab590..1fa44f6bf880 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -844,6 +844,56 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) cpt_serr_int_handler(dev_priv); } +static u32 ilk_gtt_fault_pipe_fault_mask(enum pipe pipe) +{ + switch (pipe) { + case PIPE_A: + return GTT_FAULT_SPRITE_A_FAULT | + GTT_FAULT_PRIMARY_A_FAULT | + GTT_FAULT_CURSOR_A_FAULT; + case PIPE_B: + return GTT_FAULT_SPRITE_B_FAULT | + GTT_FAULT_PRIMARY_B_FAULT | + GTT_FAULT_CURSOR_B_FAULT; + default: + return 0; + } +} + +static const struct pipe_fault_handler ilk_pipe_fault_handlers[] = { + { .fault = GTT_FAULT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = GTT_FAULT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = GTT_FAULT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = GTT_FAULT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = GTT_FAULT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = GTT_FAULT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static void ilk_gtt_fault_irq_handler(struct intel_display *display) +{ + enum pipe pipe; + u32 gtt_fault; + + gtt_fault = intel_de_read(display, ILK_GTT_FAULT); + intel_de_write(display, ILK_GTT_FAULT, gtt_fault); + + if (gtt_fault & GTT_FAULT_INVALID_GTT_PTE) + drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); + + if (gtt_fault & GTT_FAULT_INVALID_PTE_DATA) + drm_err_ratelimited(display->drm, "Invalid PTE data\n"); + + for_each_pipe(display, pipe) { + u32 fault_errors; + + fault_errors = gtt_fault & ilk_gtt_fault_pipe_fault_mask(pipe); + if (fault_errors) + intel_pipe_fault_irq_handler(display, ilk_pipe_fault_handlers, + pipe, fault_errors); + } +} + void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) { struct intel_display *display = &dev_priv->display; @@ -862,6 +912,9 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) if (de_iir & DE_POISON) drm_err(&dev_priv->drm, "Poison interrupt\n"); + if (de_iir & DE_GTT_FAULT) + ilk_gtt_fault_irq_handler(display); + for_each_pipe(dev_priv, pipe) { if (de_iir & DE_PIPE_VBLANK(pipe)) intel_handle_vblank(dev_priv, pipe); @@ -1988,7 +2041,8 @@ void ilk_de_irq_postinstall(struct drm_i915_private *i915) DE_PLANE_FLIP_DONE_IVB(PLANE_A) | DE_DP_A_HOTPLUG_IVB); } else { - display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | + display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | + DE_PCH_EVENT | DE_GTT_FAULT | DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | DE_POISON); extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b8756e5d2cae..5e91fcf40a0f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -372,6 +372,16 @@ #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) +#define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */ +#define GTT_FAULT_INVALID_GTT_PTE (1 << 7) +#define GTT_FAULT_INVALID_PTE_DATA (1 << 6) +#define GTT_FAULT_CURSOR_B_FAULT (1 << 5) +#define GTT_FAULT_CURSOR_A_FAULT (1 << 4) +#define GTT_FAULT_SPRITE_B_FAULT (1 << 3) +#define GTT_FAULT_SPRITE_A_FAULT (1 << 2) +#define GTT_FAULT_PRIMARY_B_FAULT (1 << 1) +#define GTT_FAULT_PRIMARY_A_FAULT (1 << 0) + #define GEN7_ERR_INT _MMIO(0x44040) #define ERR_INT_POISON (1 << 31) #define ERR_INT_INVALID_GTT_PTE (1 << 29) From patchwork Mon Feb 17 07:00:45 2025 Content-Type: text/plain; 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16 Feb 2025 23:01:09 -0800 X-CSE-ConnectionGUID: WPIfUpi/Qs2F/jFSuhY0cQ== X-CSE-MsgGUID: Mkb7RpW1SwOf1fovfONfqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="114233488" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 16 Feb 2025 23:01:07 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 09:01:06 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Vinod Govindapillai Subject: [PATCH v2 6/8] drm/i915: Introduce i915_error_regs Date: Mon, 17 Feb 2025 09:00:45 +0200 Message-ID: <20250217070047.953-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250217070047.953-1-ville.syrjala@linux.intel.com> References: <20250217070047.953-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Introduce i915_error_regs as the EIR/EMR counterpart to the IIR/IMR/IER i915_irq_regs, and update the irq reset/postingstall to utilize them accordingly. v2: Include xe compat versions Reviewed-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä Acked-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_irq.c | 29 +++++++++++++++++++++-- drivers/gpu/drm/i915/i915_irq.h | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/i915_reg_defs.h | 8 +++++++ drivers/gpu/drm/xe/display/ext/i915_irq.c | 23 ++++++++++++++++++ 5 files changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f98e5cc14724..bba0a0acf0ae 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -120,6 +120,29 @@ void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, intel_uncore_posting_read(uncore, regs.imr); } +void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs) +{ + intel_uncore_write(uncore, regs.emr, 0xffffffff); + intel_uncore_posting_read(uncore, regs.emr); + + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); +} + +void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs, + u32 emr_val) +{ + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); + + intel_uncore_write(uncore, regs.emr, emr_val); + intel_uncore_posting_read(uncore, regs.emr); +} + /** * ivb_parity_work - Workqueue called when a parity error interrupt * occurred. @@ -867,6 +890,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv) i9xx_display_irq_reset(dev_priv); + gen2_error_reset(uncore, GEN2_ERROR_REGS); gen2_irq_reset(uncore, GEN2_IRQ_REGS); dev_priv->irq_mask = ~0u; } @@ -876,7 +900,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = &dev_priv->uncore; u32 enable_mask; - intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv)); + gen2_error_init(uncore, GEN2_ERROR_REGS, i9xx_error_mask(dev_priv)); dev_priv->irq_mask = ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | @@ -972,6 +996,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv) i9xx_display_irq_reset(dev_priv); + gen2_error_reset(uncore, GEN2_ERROR_REGS); gen2_irq_reset(uncore, GEN2_IRQ_REGS); dev_priv->irq_mask = ~0u; } @@ -1000,7 +1025,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = &dev_priv->uncore; u32 enable_mask; - intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv)); + gen2_error_init(uncore, GEN2_ERROR_REGS, i965_error_mask(dev_priv)); dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h index 0457f6402e05..58789b264575 100644 --- a/drivers/gpu/drm/i915/i915_irq.h +++ b/drivers/gpu/drm/i915/i915_irq.h @@ -47,4 +47,8 @@ void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs); void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, u32 imr_val, u32 ier_val); +void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs); +void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs, + u32 emr_val); + #endif /* __I915_IRQ_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5e91fcf40a0f..be1aab838be9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -472,6 +472,9 @@ #define GM45_ERROR_CP_PRIV (1 << 3) #define I915_ERROR_MEMORY_REFRESH (1 << 1) #define I915_ERROR_INSTRUCTION (1 << 0) + +#define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR) + #define INSTPM _MMIO(0x20c0) #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index e251bcc0c89f..94a8f902689e 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -294,4 +294,12 @@ struct i915_irq_regs { #define I915_IRQ_REGS(_imr, _ier, _iir) \ ((const struct i915_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) }) +struct i915_error_regs { + i915_reg_t emr; + i915_reg_t eir; +}; + +#define I915_ERROR_REGS(_emr, _eir) \ + ((const struct i915_error_regs){ .emr = (_emr), .eir = (_eir) }) + #endif /* __I915_REG_DEFS__ */ diff --git a/drivers/gpu/drm/xe/display/ext/i915_irq.c b/drivers/gpu/drm/xe/display/ext/i915_irq.c index ac4cda2d81c7..3c6bca66ddab 100644 --- a/drivers/gpu/drm/xe/display/ext/i915_irq.c +++ b/drivers/gpu/drm/xe/display/ext/i915_irq.c @@ -51,6 +51,29 @@ void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, intel_uncore_posting_read(uncore, regs.imr); } +void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs) +{ + intel_uncore_write(uncore, regs.emr, 0xffffffff); + intel_uncore_posting_read(uncore, regs.emr); + + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); +} + +void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs, + u32 emr_val) +{ + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); + + intel_uncore_write(uncore, regs.emr, emr_val); + intel_uncore_posting_read(uncore, regs.emr); +} + bool intel_irqs_enabled(struct xe_device *xe) { return atomic_read(&xe->irq.enabled); From patchwork Mon Feb 17 07:00:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13977183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94C3AC021A4 for ; Mon, 17 Feb 2025 07:01:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3925C10E374; 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X-CSE-ConnectionGUID: +cShpAmCRwyeoN6+Lazc4Q== X-CSE-MsgGUID: n/9o4o4+RIyj5j2qlzNpqw== X-IronPort-AV: E=McAfee;i="6700,10204,11347"; a="39676269" X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="39676269" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2025 23:01:13 -0800 X-CSE-ConnectionGUID: x9gPQw7+Q3C09FHbICALOw== X-CSE-MsgGUID: 1eyu9LiTRpWUoFmPOSoLvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="114233509" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 16 Feb 2025 23:01:10 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 09:01:09 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Vinod Govindapillai Subject: [PATCH v2 7/8] drm/i915: Un-invert {i9xx,i965}_error_mask() Date: Mon, 17 Feb 2025 09:00:46 +0200 Message-ID: <20250217070047.953-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250217070047.953-1-ville.syrjala@linux.intel.com> References: <20250217070047.953-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Make life a bit more straightforward by removing the bitwise not from {i9xx,i965}_error_mask() and instead do it when feeding the value to gen2_error_init(). Make life a bit easier I think. Reviewed-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index bba0a0acf0ae..da130e1b5cc1 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -838,10 +838,10 @@ static u32 i9xx_error_mask(struct drm_i915_private *i915) * so we just have to mask off all page table errors via EMR. */ if (HAS_FBC(i915)) - return ~I915_ERROR_MEMORY_REFRESH; + return I915_ERROR_MEMORY_REFRESH; else - return ~(I915_ERROR_PAGE_TABLE | - I915_ERROR_MEMORY_REFRESH); + return I915_ERROR_PAGE_TABLE | + I915_ERROR_MEMORY_REFRESH; } static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, @@ -900,7 +900,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = &dev_priv->uncore; u32 enable_mask; - gen2_error_init(uncore, GEN2_ERROR_REGS, i9xx_error_mask(dev_priv)); + gen2_error_init(uncore, GEN2_ERROR_REGS, ~i9xx_error_mask(dev_priv)); dev_priv->irq_mask = ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | @@ -1011,13 +1011,13 @@ static u32 i965_error_mask(struct drm_i915_private *i915) * so we can always enable the page table errors. */ if (IS_G4X(i915)) - return ~(GM45_ERROR_PAGE_TABLE | - GM45_ERROR_MEM_PRIV | - GM45_ERROR_CP_PRIV | - I915_ERROR_MEMORY_REFRESH); + return GM45_ERROR_PAGE_TABLE | + GM45_ERROR_MEM_PRIV | + GM45_ERROR_CP_PRIV | + I915_ERROR_MEMORY_REFRESH; else - return ~(I915_ERROR_PAGE_TABLE | - I915_ERROR_MEMORY_REFRESH); + return I915_ERROR_PAGE_TABLE | + I915_ERROR_MEMORY_REFRESH; } static void i965_irq_postinstall(struct drm_i915_private *dev_priv) @@ -1025,7 +1025,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = &dev_priv->uncore; u32 enable_mask; - gen2_error_init(uncore, GEN2_ERROR_REGS, i965_error_mask(dev_priv)); + gen2_error_init(uncore, GEN2_ERROR_REGS, ~i965_error_mask(dev_priv)); dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | From patchwork Mon Feb 17 07:00:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13977184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 729D4C021A4 for ; Mon, 17 Feb 2025 07:01:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 10EAF10E383; Mon, 17 Feb 2025 07:01:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bg/CzpGa"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 09A1510E382; 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16 Feb 2025 23:01:16 -0800 X-CSE-ConnectionGUID: XD2ihTiuSK21qDIt6Kcd0Q== X-CSE-MsgGUID: uQIH5VJRSwqO1VeIwqT4gg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,292,1732608000"; d="scan'208";a="114233532" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 16 Feb 2025 23:01:13 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 09:01:12 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Vinod Govindapillai Subject: [PATCH v2 8/8] drm/i915: Hook up display fault interrupts for VLV/CHV Date: Mon, 17 Feb 2025 09:00:47 +0200 Message-ID: <20250217070047.953-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250217070047.953-1-ville.syrjala@linux.intel.com> References: <20250217070047.953-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Hook up the display fault irq handlers for VLV/CHV. Unfortunately the actual hardware doesn't agree with the spec on how DPINVGTT should behave. The docs claim that the status bits can be cleared by writing '1' to them, but in reality there doesn't seem to be any way to clear them. So we must disable and ignore any fault we've already seen in the past. The entire register does reset when the display power well goes down, so we can just always re-enable all the bits in irq postinstall without having to track the state beyond that. v2: Use intel_display instead of dev_priv Move xe gen2_error_{init,reset}() out Reviewed-by: Vinod Govindapillai Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_display_irq.c | 132 +++++++++++++++++- .../gpu/drm/i915/display/intel_display_irq.h | 3 + drivers/gpu/drm/i915/i915_irq.c | 14 ++ drivers/gpu/drm/i915/i915_reg.h | 10 ++ 4 files changed, 158 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 1fa44f6bf880..99fb7fc7be39 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1784,6 +1784,114 @@ void bdw_disable_vblank(struct drm_crtc *_crtc) schedule_work(&display->irq.vblank_dc_work); } +static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe) +{ + switch (pipe) { + case PIPE_A: + return SPRITEB_INVALID_GTT_STATUS | + SPRITEA_INVALID_GTT_STATUS | + PLANEA_INVALID_GTT_STATUS | + CURSORA_INVALID_GTT_STATUS; + case PIPE_B: + return SPRITED_INVALID_GTT_STATUS | + SPRITEC_INVALID_GTT_STATUS | + PLANEB_INVALID_GTT_STATUS | + CURSORB_INVALID_GTT_STATUS; + case PIPE_C: + return SPRITEF_INVALID_GTT_STATUS | + SPRITEE_INVALID_GTT_STATUS | + PLANEC_INVALID_GTT_STATUS | + CURSORC_INVALID_GTT_STATUS; + default: + return 0; + } +} + +static const struct pipe_fault_handler vlv_pipe_fault_handlers[] = { + { .fault = SPRITEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, + { .fault = SPRITEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = PLANEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = CURSORA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = SPRITED_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, + { .fault = SPRITEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = PLANEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = CURSORB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = SPRITEF_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, + { .fault = SPRITEE_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = PLANEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = CURSORC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static void vlv_page_table_error_irq_ack(struct intel_display *display, u32 *dpinvgtt) +{ + u32 status, enable, tmp; + + tmp = intel_de_read(display, DPINVGTT); + + enable = tmp >> 16; + status = tmp & 0xffff; + + /* + * Despite what the docs claim, the status bits seem to get + * stuck permanently (similar the old PGTBL_ER register), so + * we have to disable and ignore them once set. They do get + * reset if the display power well goes down, so no need to + * track the enable mask explicitly. + */ + *dpinvgtt = status & enable; + enable &= ~status; + + /* customary ack+disable then re-enable to guarantee an edge */ + intel_de_write(display, DPINVGTT, status); + intel_de_write(display, DPINVGTT, enable << 16); +} + +static void vlv_page_table_error_irq_handler(struct intel_display *display, u32 dpinvgtt) +{ + enum pipe pipe; + + for_each_pipe(display, pipe) { + u32 fault_errors; + + fault_errors = dpinvgtt & vlv_dpinvgtt_pipe_fault_mask(pipe); + if (fault_errors) + intel_pipe_fault_irq_handler(display, vlv_pipe_fault_handlers, + pipe, fault_errors); + } +} + +void vlv_display_error_irq_ack(struct intel_display *display, + u32 *eir, u32 *dpinvgtt) +{ + u32 emr; + + *eir = intel_de_read(display, VLV_EIR); + + if (*eir & VLV_ERROR_PAGE_TABLE) + vlv_page_table_error_irq_ack(display, dpinvgtt); + + intel_de_write(display, VLV_EIR, *eir); + + /* + * Toggle all EMR bits to make sure we get an edge + * in the ISR master error bit if we don't clear + * all the EIR bits. + */ + emr = intel_de_read(display, VLV_EMR); + intel_de_write(display, VLV_EMR, 0xffffffff); + intel_de_write(display, VLV_EMR, emr); +} + +void vlv_display_error_irq_handler(struct intel_display *display, + u32 eir, u32 dpinvgtt) +{ + drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir); + + if (eir & VLV_ERROR_PAGE_TABLE) + vlv_page_table_error_irq_handler(display, dpinvgtt); +} + static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv) { struct intel_display *display = &dev_priv->display; @@ -1793,6 +1901,9 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv) else intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); + gen2_error_reset(to_intel_uncore(display->drm), + VLV_ERROR_REGS); + i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); intel_de_rmw(display, PORT_HOTPLUG_STAT(dev_priv), 0, 0); @@ -1820,6 +1931,12 @@ void i9xx_display_irq_reset(struct drm_i915_private *i915) i9xx_pipestat_irq_reset(i915); } +static u32 vlv_error_mask(void) +{ + /* TODO enable other errors too? */ + return VLV_ERROR_PAGE_TABLE; +} + void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) { struct intel_display *display = &dev_priv->display; @@ -1830,6 +1947,18 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) if (!dev_priv->display.irq.vlv_display_irqs_enabled) return; + if (IS_CHERRYVIEW(dev_priv)) + intel_de_write(display, DPINVGTT, + DPINVGTT_STATUS_MASK_CHV | + DPINVGTT_EN_MASK_CHV); + else + intel_de_write(display, DPINVGTT, + DPINVGTT_STATUS_MASK_VLV | + DPINVGTT_EN_MASK_VLV); + + gen2_error_init(to_intel_uncore(display->drm), + VLV_ERROR_REGS, ~vlv_error_mask()); + pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); @@ -1840,7 +1969,8 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | I915_LPE_PIPE_A_INTERRUPT | - I915_LPE_PIPE_B_INTERRUPT; + I915_LPE_PIPE_B_INTERRUPT | + I915_MASTER_ERROR_INTERRUPT; if (IS_CHERRYVIEW(dev_priv)) enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h index 75ab38a0908e..d9867cd0a220 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.h +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h @@ -76,6 +76,9 @@ void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_ void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]); +void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt); +void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt); + void intel_display_irq_init(struct drm_i915_private *i915); void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index da130e1b5cc1..37ca4a35daf2 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -241,6 +241,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) do { u32 iir, gt_iir, pm_iir; + u32 eir = 0, dpinvgtt = 0; u32 pipe_stats[I915_MAX_PIPES] = {}; u32 hotplug_status = 0; u32 ier = 0; @@ -278,6 +279,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) if (iir & I915_DISPLAY_PORT_INTERRUPT) hotplug_status = i9xx_hpd_irq_ack(dev_priv); + if (iir & I915_MASTER_ERROR_INTERRUPT) + vlv_display_error_irq_ack(display, &eir, &dpinvgtt); + /* Call regardless, as some status bits might not be * signalled in IIR */ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); @@ -304,6 +308,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) if (hotplug_status) i9xx_hpd_irq_handler(dev_priv, hotplug_status); + if (iir & I915_MASTER_ERROR_INTERRUPT) + vlv_display_error_irq_handler(display, eir, dpinvgtt); + valleyview_pipestat_irq_handler(dev_priv, pipe_stats); } while (0); @@ -328,6 +335,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) do { u32 master_ctl, iir; + u32 eir = 0, dpinvgtt = 0; u32 pipe_stats[I915_MAX_PIPES] = {}; u32 hotplug_status = 0; u32 ier = 0; @@ -361,6 +369,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) if (iir & I915_DISPLAY_PORT_INTERRUPT) hotplug_status = i9xx_hpd_irq_ack(dev_priv); + if (iir & I915_MASTER_ERROR_INTERRUPT) + vlv_display_error_irq_ack(display, &eir, &dpinvgtt); + /* Call regardless, as some status bits might not be * signalled in IIR */ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); @@ -383,6 +394,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) if (hotplug_status) i9xx_hpd_irq_handler(dev_priv, hotplug_status); + if (iir & I915_MASTER_ERROR_INTERRUPT) + vlv_display_error_irq_handler(display, eir, dpinvgtt); + valleyview_pipestat_irq_handler(dev_priv, pipe_stats); } while (0); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index be1aab838be9..b31b26e9a685 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -475,6 +475,16 @@ #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR) +#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0) +#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4) +#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8) +#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6) +#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5) +#define VLV_ERROR_PAGE_TABLE (1 << 4) +#define VLV_ERROR_CLAIM (1 << 0) + +#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR) + #define INSTPM _MMIO(0x20c0) #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts