From patchwork Mon Feb 17 11:17:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13977620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 002B9C021A0 for ; Mon, 17 Feb 2025 11:18:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 83D0F10E412; Mon, 17 Feb 2025 11:17:58 +0000 (UTC) Received: from relay04.th.seeweb.it (relay04.th.seeweb.it [5.144.164.165]) by gabe.freedesktop.org (Postfix) with ESMTPS id A04F910E1C1 for ; Mon, 17 Feb 2025 11:17:55 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 73A8E1F8E2; Mon, 17 Feb 2025 12:17:53 +0100 (CET) From: Marijn Suijten Date: Mon, 17 Feb 2025 12:17:41 +0100 Subject: [PATCH v3 1/3] drm/msm/dsi: Use existing per-interface slice count in DSC timing MIME-Version: 1.0 Message-Id: <20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-1-913100d6103f@somainline.org> References: <20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-0-913100d6103f@somainline.org> In-Reply-To: <20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-0-913100d6103f@somainline.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Vinod Koul , Simona Vetter , Archit Taneja , Hai Li Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , Konrad Dybcio , Marijn Suijten , Jessica Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4206; i=marijn.suijten@somainline.org; h=from:subject:message-id; bh=NfyEn7E8N5j9NVYMHZI04j6J7f3aNWoj5htucqf7JL0=; b=owEBbQKS/ZANAwAIAfFi0jHH5IZ2AcsmYgBnsxrfto6m023a119CNSqHfQJogVT4e6r+qoxQh XTnh6rOAX6JAjMEAAEIAB0WIQROiwG5pb6la1/WZxbxYtIxx+SGdgUCZ7Ma3wAKCRDxYtIxx+SG dq4XD/0aJYH2AxljtqnswKsSNRoKbbEnwP41fJffxQBL6GVkDXj43SdG6Jj7a5WkFYSYJ4Tngb1 f73ahvybxu7/X5s4iJ2jGpwBnFayTOd/hhxM4YvY8yspag37RksfHT5JzMlMwKNuW7gERKWfuLf xcURlvp4GqzDc1f/Xc9gsYDXQKlod337oSA4akDZ8plm3gFGaesh3ZS4oB8L0JD04ZHFRNxB+kx JKqAaLleKYX/Ae7nwQvod4A/gREFUBLv82SNW63lAkG+GfCMLcWFJxJVWNzU1j8mOhEWQQ5mESR ni4uZYWioXQfJ+6e4YH3iX9G1KzUheoFngm/ERbjI2q6Uw6TP7WBP9DUDkdsw59ZeM8tJx998Zq B1oYTLxdUIvVkFlG/HQJ7+IGAKp/nQDIc0Piw2ELScWK+SL+bTFezNm1L/1Q/d4jDKn4faCROpT 1MY4N2l4DNv9PF9N/mzyIfIbX60joXIRcPfu5dGQAsnPbDrumUYWn4FXRLB86vsz9Bkfv3yZXDl yetAO7hIlGesHdbTPfvBRupMkePgzrekSXk0S9ONfvedjkhfsUhR3S3Ddd7YCCCqybeRseFmzH0 KORAQ7UaLGLjOlPp3Am/xRDN+DlasKvTRZdpj4tfyamdwbt8v4HCbJdre0r8ks85COV/MIjwErs Gsh4AbIOaLMfR8Q== X-Developer-Key: i=marijn.suijten@somainline.org; a=openpgp; fpr=4E8B01B9A5BEA56B5FD66716F162D231C7E48676 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" When configuring the timing of DSI hosts (interfaces) in dsi_timing_setup() all values written to registers are taking bonded-mode into account by dividing the original mode width by 2 (half the data is sent over each of the two DSI hosts), but the full width instead of the interface width is passed as hdisplay parameter to dsi_update_dsc_timing(). Currently only msm_dsc_get_slices_per_intf() is called within dsi_update_dsc_timing() with the `hdisplay` argument which clearly documents that it wants the width of a single interface (which, again, in bonded DSI mode is half the total width of the mode) resulting in all subsequent values to be completely off. However, as soon as we start to pass the halved hdisplay into dsi_update_dsc_timing() we might as well discard msm_dsc_get_slices_per_intf() since the value it calculates is already available in dsc->slice_count which is per-interface by the current design of MSM DPU/DSI implementations and their use of the DRM DSC helpers. Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Marijn Suijten --- drivers/gpu/drm/msm/dsi/dsi_host.c | 8 ++++---- drivers/gpu/drm/msm/msm_dsc_helper.h | 11 ----------- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 007311c21fdaa0462b05d53cd8a2aad0269b1727..42e100a8adca09d7b55afce0e2553e76d898744f 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -846,7 +846,7 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); } -static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) +static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode) { struct drm_dsc_config *dsc = msm_host->dsc; u32 reg, reg_ctrl, reg_ctrl2; @@ -858,7 +858,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* first calculate dsc parameters and then program * compress mode registers */ - slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); + slice_per_intf = dsc->slice_count; total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ @@ -991,7 +991,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, false, mode->hdisplay); + dsi_update_dsc_timing(msm_host, false); dsi_write(msm_host, REG_DSI_ACTIVE_H, DSI_ACTIVE_H_START(ha_start) | @@ -1012,7 +1012,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); } else { /* command mode */ if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, true, mode->hdisplay); + dsi_update_dsc_timing(msm_host, true); /* image data and 1 byte write_memory_start cmd */ if (!msm_host->dsc) diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.h b/drivers/gpu/drm/msm/msm_dsc_helper.h index b9049fe1e2790703a6f42dd7e6cd3fa5eea29389..63f95523b2cbb48f822210ac47cdd3526f231a89 100644 --- a/drivers/gpu/drm/msm/msm_dsc_helper.h +++ b/drivers/gpu/drm/msm/msm_dsc_helper.h @@ -12,17 +12,6 @@ #include #include -/** - * msm_dsc_get_slices_per_intf() - calculate number of slices per interface - * @dsc: Pointer to drm dsc config struct - * @intf_width: interface width in pixels - * Returns: Integer representing the number of slices for the given interface - */ -static inline u32 msm_dsc_get_slices_per_intf(const struct drm_dsc_config *dsc, u32 intf_width) -{ - return DIV_ROUND_UP(intf_width, dsc->slice_width); -} - /** * msm_dsc_get_bytes_per_line() - calculate bytes per line * @dsc: Pointer to drm dsc config struct From patchwork Mon Feb 17 11:17:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13977621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A425FC0219E for ; Mon, 17 Feb 2025 11:18:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 38FC110E419; Mon, 17 Feb 2025 11:17:59 +0000 (UTC) Received: from relay03.th.seeweb.it (relay03.th.seeweb.it [5.144.164.164]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9A55010E1C1 for ; Mon, 17 Feb 2025 11:17:56 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 7B5391F8B0; Mon, 17 Feb 2025 12:17:54 +0100 (CET) From: Marijn Suijten Date: Mon, 17 Feb 2025 12:17:42 +0100 Subject: [PATCH v3 2/3] drm/msm/dsi: Set PHY usescase (and mode) before registering DSI host MIME-Version: 1.0 Message-Id: <20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-2-913100d6103f@somainline.org> References: <20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-0-913100d6103f@somainline.org> In-Reply-To: <20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-0-913100d6103f@somainline.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Vinod Koul , Simona Vetter , Archit Taneja , Hai Li Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3750; i=marijn.suijten@somainline.org; h=from:subject:message-id; bh=drRnFxgg1L1HkjA8cDu1XcjU//ZbLn26xuJFrUxc9i0=; b=owEBbQKS/ZANAwAIAfFi0jHH5IZ2AcsmYgBnsxrg6BTjtoTx1KOrLJGWkv3nYFR7o9tYMTZpu dy9JlOc1ReJAjMEAAEIAB0WIQROiwG5pb6la1/WZxbxYtIxx+SGdgUCZ7Ma4AAKCRDxYtIxx+SG dvkdD/9Ix7zgahopBu6M5R/YDwxrCljO/pPcsiyk/iWcUXH4KKAt3l/JuP6kdsN4XlS7Kt9fKYs g8vKBEcTZPdTB3nki9p7IDBqRLnBhTGlclTLwrpz26xPIfDj+eYCS+EneoN7RfDGxkuQtWSKJYw oFxbysWK5GylEb//zCbDTRH+4iVK9jyKbQdg2vxZonpb2EfZ0ZmlOimFMaXUNw1QPUFcsj0ozus /kMlVhGkTm3+tQRVkMEIE91tkK58osmsxbiaEfhvNKm/wpDlfTK7jjdPmIrV+g5NoBIdZHQlE4W o7zpG0Ss+2iF6UMu4Hp+Zy2+84CI9UhEDe6FyRDbnw/FMzl/3JwDNdRQmdCCoiMJ9f4nxltRa+4 GuQkQs/i7HkAlWI4n2k0R5IVnUL43Jod90EoPc/KkcG56c92TQkHrBi9ZxFv5l5XE1rncCdvw/1 5nfUBE4cQz5qVd4uhpFqJdXVoVmA/jE+p6WyyDstlxB2GI7xV1y+tHx+GXA1TfK4BrlekU4Eb06 4OuQSbqL1aLOpVljhGF6Bh2X7haZpDxXM8+jcNpv2aLQjzyRs0uELJhKRNEdYKsVqVOyFev5ONN +PGejxHGraPwH5Xl9DXr/9TtgeCRoMIMwSKGHB+igX8RWetcuBS+dYL8M2kpbkA9E2HjRYDo2em pMaBntImu06E4cw== X-Developer-Key: i=marijn.suijten@somainline.org; a=openpgp; fpr=4E8B01B9A5BEA56B5FD66716F162D231C7E48676 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Ordering issues here cause an uninitialized (default STANDALONE) usecase to be programmed (which appears to be a MUX) in some cases when msm_dsi_host_register() is called, leading to the slave PLL in bonded-DSI mode to source from a clock parent (dsi1vco) that is off. This should seemingly not be a problem as the actual dispcc clocks from DSI1 that are muxed in the clock tree of DSI0 are way further down, this bit still seems to have an effect on them somehow and causes the right side of the panel controlled by DSI1 to not function. In an ideal world this code is refactored to no longer have such error-prone calls "across subsystems", and instead model the "PLL src" register field as a regular mux so that changing the clock parents programmatically or in DTS via `assigned-clock-parents` has the desired effect. But for the avid reader, the clocks that we *are* muxing into DSI0's tree are way further down, so if this bit turns out to be a simple mux between dsiXvco and out_div, that shouldn't have any effect as this whole tree is off anyway. Fixes: 57bf43389337 ("drm/msm/dsi: Pass down use case to PHY") Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Signed-off-by: Marijn Suijten --- drivers/gpu/drm/msm/dsi/dsi_manager.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index a210b7c9e5ca281a46fbdb226e25832719a684ea..4fabb01345aa2a6de60bee4dc0dd0b1a4245509c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -74,17 +74,35 @@ static int dsi_mgr_setup_components(int id) int ret; if (!IS_BONDED_DSI()) { + /* + * Set the usecase before calling msm_dsi_host_register(), which would + * already program the PLL source mux based on a default usecase. + */ + msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); + msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); + ret = msm_dsi_host_register(msm_dsi->host); if (ret) return ret; - - msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); - msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); } else if (other_dsi) { struct msm_dsi *master_link_dsi = IS_MASTER_DSI_LINK(id) ? msm_dsi : other_dsi; struct msm_dsi *slave_link_dsi = IS_MASTER_DSI_LINK(id) ? other_dsi : msm_dsi; + + /* + * PLL0 is to drive both DSI link clocks in bonded DSI mode. + * + * Set the usecase before calling msm_dsi_host_register(), which would + * already program the PLL source mux based on a default usecase. + */ + msm_dsi_phy_set_usecase(clk_master_dsi->phy, + MSM_DSI_PHY_MASTER); + msm_dsi_phy_set_usecase(clk_slave_dsi->phy, + MSM_DSI_PHY_SLAVE); + msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); + msm_dsi_host_set_phy_mode(other_dsi->host, other_dsi->phy); + /* Register slave host first, so that slave DSI device * has a chance to probe, and do not block the master * DSI device's probe. @@ -98,14 +116,6 @@ static int dsi_mgr_setup_components(int id) ret = msm_dsi_host_register(master_link_dsi->host); if (ret) return ret; - - /* PLL0 is to drive both 2 DSI link clocks in bonded DSI mode. */ - msm_dsi_phy_set_usecase(clk_master_dsi->phy, - MSM_DSI_PHY_MASTER); - msm_dsi_phy_set_usecase(clk_slave_dsi->phy, - MSM_DSI_PHY_SLAVE); - msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); - msm_dsi_host_set_phy_mode(other_dsi->host, other_dsi->phy); } return 0; From patchwork Mon Feb 17 11:17:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13977622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1A8CC021A0 for ; Mon, 17 Feb 2025 11:18:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8353010E41C; Mon, 17 Feb 2025 11:17:59 +0000 (UTC) Received: from m-r1.th.seeweb.it (m-r1.th.seeweb.it [5.144.164.170]) by gabe.freedesktop.org (Postfix) with ESMTPS id F09D010E32C for ; Mon, 17 Feb 2025 11:17:57 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 7C5931F8F2; Mon, 17 Feb 2025 12:17:55 +0100 (CET) From: Marijn Suijten Date: Mon, 17 Feb 2025 12:17:43 +0100 Subject: [PATCH v3 3/3] drm/msm/dpu: Remove arbitrary limit of 1 interface in DSC topology MIME-Version: 1.0 Message-Id: <20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-3-913100d6103f@somainline.org> References: <20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-0-913100d6103f@somainline.org> In-Reply-To: <20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-0-913100d6103f@somainline.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Vinod Koul , Simona Vetter , Archit Taneja , Hai Li Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , Konrad Dybcio , Marijn Suijten , Jessica Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2058; i=marijn.suijten@somainline.org; h=from:subject:message-id; bh=MgMGnmZBZiiXwg/TOFHX7DTi1si89IdnuyFW3h892yg=; b=owEBbQKS/ZANAwAIAfFi0jHH5IZ2AcsmYgBnsxrgGM6TmLIP+Y8pCQpDj7IdZUB4VzZ8riqFj a30QyrxqXOJAjMEAAEIAB0WIQROiwG5pb6la1/WZxbxYtIxx+SGdgUCZ7Ma4AAKCRDxYtIxx+SG dtN8EACFtQBw8cwzIfeyB/OhAWSC/pSEkfkYf0pCMHdtroktRTzvlw52AvGnd0yLBCTEBdnCPDt Et09anMQ9iA/Qi0jsDMDNnhXvANL6WuG8DDXlDzX6QyVWSKJWIFR3Kh8xBeLs8IQpZMAMjFVwzz 10nFpVjFuedGsh8hVVD7Qg6DPqtbzagtRcg1AIJqwuynUJawrA9yrlW9GzdtYV4p5dZYdTiBHS5 4eCHQn5l6q4XA+1WmfJVR+z5+4IA0fZB+IUmbocm1R9no8/X5l11eey6SDDNn+wW4ov5D0SLR3A 9IQdf6Ma2bG8RgmJLwFYPOGHsk9zmR6BPzUO6VX1gQ/O9cxillPLO8/Uw6UVplCdFTiO1WcoJ84 sllqEh1oNh9aerRb8iLUhPnr3bYl2XYmb2eHECTQLTBTuRol1126PIkFLUbSUXh48wzuSlXaz0S 7r/JP5zWgHYPf+yY+Y8CNCf0+b8CXwpb6cEg+XCkHD9XnWycsbaLqFvbTsltis8FzAoPvEFe+9m FRmydy7vYSeR9DqBhmvpMKjMidKc2ZiMfI/UWKzuO/EBAt97vOJVt/ypptZjfsfd5gLbWXMvz4g 17+cFQW/oYBfFth0DJMdJUTUb+oC/aKAK4rWqpTHASATUakVY8s4DlsZ26PxNqkQxjmdDG6pbDP MZoMDLeTEgEPqEg== X-Developer-Key: i=marijn.suijten@somainline.org; a=openpgp; fpr=4E8B01B9A5BEA56B5FD66716F162D231C7E48676 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" When DSC is enabled the number of interfaces is forced to be 1, and documented that it is a "power-optimal" layout to use two DSC encoders together with two Layer Mixers. However, the same layout (two DSC hard-slice encoders with two LMs) is also used when the display is fed with data over two instead of one interface (common on 4k@120Hz smartphone panels with Dual-DSI). Solve this by simply removing the num_intf = 1 assignment as the count is already calculated by computing the number of physical encoders within the virtual encoder. Fixes: 7e9cc175b159 ("drm/msm/disp/dpu1: Add support for DSC in topology") Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index d67127f67a4492f30329ee15267369ca7540288a..1b092fa45b1dadbeb06b5c086c7638556bd313dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -686,20 +686,21 @@ static struct msm_display_topology dpu_encoder_get_topology( if (dsc) { /* - * Use 2 DSC encoders and 2 layer mixers per single interface + * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces * when Display Stream Compression (DSC) is enabled, * and when enough DSC blocks are available. * This is power-optimal and can drive up to (including) 4k * screens. */ - if (dpu_kms->catalog->dsc_count >= 2) { + WARN(topology.num_intf > 2, + "DSC topology cannot support more than 2 interfaces\n"); + if (intf_count >= 2 || dpu_kms->catalog->dsc_count >= 2) { topology.num_dsc = 2; topology.num_lm = 2; } else { topology.num_dsc = 1; topology.num_lm = 1; } - topology.num_intf = 1; } return topology;