From patchwork Mon Feb 17 22:38:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13978758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E63EC021AB for ; Mon, 17 Feb 2025 22:37:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E4ECF10E2EA; Mon, 17 Feb 2025 22:37:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WOyUAFSI"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 431CD10E2EA; Mon, 17 Feb 2025 22:37:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739831850; x=1771367850; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e3W15pdFUay2X4MUqjFbksdjtZgDa/8IFND6iZsW3n4=; b=WOyUAFSIIBJ0LNNwrMIqMQ6IgVzBMc6OKfWaA5Y1aZiAbgVmPQFiMe7J DI+opsmboqngHGLTnsHpdm9M4gMA9OB4y9H7YwAqCLMMewI/0dUn02o7o lIN9vt09wVUcird4CL57/McatBk8q/ydmuBdmIlJDwIUDKUi0LxrT3Gau o7MQs/ztecWUgbvOFqpiz2tBWRCqMOfpSqFypFM7wgzjjPNVXmBbnw+6s rZtwY65cKICWjRaYruWUb5Bgt1gY4/Xsa+HkhYeCyC5CLq91AbruwvDoZ fLyzY8yE8iDEgzt1qKBYtoagAth2sV9ii/MRdb/MXTpMA0o3aDnSV78c3 w==; X-CSE-ConnectionGUID: x2C+CfPVR82uhTknuXZtQg== X-CSE-MsgGUID: teuVewk6SWCZQ/jFQiGxlQ== X-IronPort-AV: E=McAfee;i="6700,10204,11348"; a="44171140" X-IronPort-AV: E=Sophos;i="6.13,294,1732608000"; d="scan'208";a="44171140" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2025 14:37:30 -0800 X-CSE-ConnectionGUID: fThTQHpRTZ+1kgrSflZ3CQ== X-CSE-MsgGUID: 6YzBTyUBS4yR3NmF6zzZKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,294,1732608000"; d="scan'208";a="114872573" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2025 14:37:28 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: stable@vger.kernel.org, Jani Nikula Subject: [PATCH 1/2] drm/i915/dp: Fix error handling during 128b/132b link training Date: Tue, 18 Feb 2025 00:38:27 +0200 Message-ID: <20250217223828.1166093-2-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250217223828.1166093-1-imre.deak@intel.com> References: <20250217223828.1166093-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" At the end of a 128b/132b link training sequence, the HW expects the transcoder training pattern to be set to TPS2 and from that to normal mode (disabling the training pattern). Transitioning from TPS1 directly to normal mode leaves the transcoder in a stuck state, resulting in page-flip timeouts later in the modeset sequence. Atm, in case of a failure during link training, the transcoder may be still set to output the TPS1 pattern. Later the transcoder is then set from TPS1 directly to normal mode in intel_dp_stop_link_train(), leading to modeset failures later as described above. Fix this by setting the training patter to TPS2, if the link training failed at any point. Cc: stable@vger.kernel.org # v5.18+ Cc: Jani Nikula Signed-off-by: Imre Deak Acked-by: Jani Nikula --- .../gpu/drm/i915/display/intel_dp_link_training.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 3cc06c916017d..11953b03bb6aa 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1563,7 +1563,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n"); - return false; + goto out; } if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && @@ -1575,6 +1575,19 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, passed ? "passed" : "failed", crtc_state->port_clock, crtc_state->lane_count); +out: + /* + * Ensure that the training pattern does get set to TPS2 even in case + * of a failure, as is the case at the end of a passing link training + * and what is expected by the transcoder. Leaving TPS1 set (and + * disabling the link train mode in DP_TP_CTL later from TPS1 directly) + * would result in a stuck transcoder HW state and flip-done timeouts + * later in the modeset sequence. + */ + if (!passed) + intel_dp_program_link_training_pattern(intel_dp, crtc_state, + DP_PHY_DPRX, DP_TRAINING_PATTERN_2); + return passed; } From patchwork Mon Feb 17 22:38:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13978760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 027ADC021AA for ; Mon, 17 Feb 2025 22:37:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A257110E5F8; Mon, 17 Feb 2025 22:37:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ewEpHls4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9B73710E5F4; Mon, 17 Feb 2025 22:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739831852; x=1771367852; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+qqf4MokL2mM+hbu2u2ztwqSa9ICZE7XMBOg4nJ+6Jw=; b=ewEpHls4TLUHNhqhjjxbJeZhXB4N9a4LN517xrkXtj6thA6Ehm7U/Onf Dn1pFMvCJ9XeYkZBv9RDwLZ9JNSLZw+Vk8dvvIIFcgVINma5PuHzq6e+i 4mhjG3A/p84kkYf0ONdLiNjaSoB3jqI4ZMWjvT9m1UvzYe8DZTdWp/Msx 7EuF/jgsHJ7ZXaqHT9v8nAeAkv6oMAl/RQhYvdzysd/lmR79FmJYeqHs9 fA+QlKRTwyDSPfbj2h4XBOtZvOp4HguCr2M+I6BFplG23/fnKgy8SI5dk 5NEZZbxqPcALtQIubz/kurVXAlOGZSj4SjaNy8cwI3kLWwjnOaT6ntgL+ Q==; X-CSE-ConnectionGUID: KfxQ6lTRQ7WsOKEupY6uWA== X-CSE-MsgGUID: VU0N5YOSQpSLFoefnQE6Ig== X-IronPort-AV: E=McAfee;i="6700,10204,11348"; a="44171149" X-IronPort-AV: E=Sophos;i="6.13,294,1732608000"; d="scan'208";a="44171149" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2025 14:37:31 -0800 X-CSE-ConnectionGUID: 9JEQedLGRbKjfupuHwMZ6g== X-CSE-MsgGUID: 73tOt+z4S0ydvLh6uDe3Ig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,294,1732608000"; d="scan'208";a="114872588" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2025 14:37:30 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH 2/2] drm/i915/dp: Fix disabling the transcoder function in 128b/132b mode Date: Tue, 18 Feb 2025 00:38:28 +0200 Message-ID: <20250217223828.1166093-3-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250217223828.1166093-1-imre.deak@intel.com> References: <20250217223828.1166093-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During disabling the transcoder in DP 128b/132b mode (both in case of an MST master transcoder and in case of SST) the transcoder function must be first disabled without changing any other field in the register (in particular leaving the DDI port and mode select fields unchanged) and clearing the DDI port and mode select fields separately, later during the disabling sequences. Fix the sequence accordingly. Bspec: 54128, 65448, 68849 Cc: Jani Nikula Fixes: 79a6734cd56e ("drm/i915/ddi: disable trancoder port select for 128b/132b SST") Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5082f38b0a02e..7937f4de66cb4 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -681,7 +681,6 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); u32 ctl; if (DISPLAY_VER(dev_priv) >= 11) @@ -701,8 +700,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); if (DISPLAY_VER(dev_priv) >= 12) { - if (!intel_dp_mst_is_master_trans(crtc_state) || - (!is_mst && intel_dp_is_uhbr(crtc_state))) { + if (!intel_dp_mst_is_master_trans(crtc_state)) { ctl &= ~(TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); } @@ -3138,7 +3136,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, intel_dp_set_power(intel_dp, DP_SET_POWER_D3); if (DISPLAY_VER(dev_priv) >= 12) { - if (is_mst) { + if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; intel_de_rmw(dev_priv,