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Tue, 18 Feb 2025 03:44:07 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/3] clk: renesas: rzv2h-cpg: Move PLL access macros to source file Date: Tue, 18 Feb 2025 11:43:51 +0000 Message-ID: <20250218114353.406684-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218114353.406684-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250218114353.406684-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Move the `PLL_CLK_ACCESS()`, `PLL_CLK1_OFFSET()`, and `PLL_CLK2_OFFSET()` macros from `rzv2h-cpg.h` to `rzv2h-cpg.c`, as they are not intended for use by SoC-specific CPG drivers. Additionally, update `PLL_CLK1_OFFSET()` and `PLL_CLK2_OFFSET()` to use the `FIELD_GET()` macro for better readability and simplify the `PLL_CLK_ACCESS()` macro. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 4 ++++ drivers/clk/renesas/rzv2h-cpg.h | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 419dc8cd2766..1ebaefb36133 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -56,6 +56,10 @@ #define CPG_CLKSTATUS0 (0x700) +#define PLL_CLK_ACCESS(n) (!!((n) & BIT(31))) +#define PLL_CLK1_OFFSET(n) FIELD_GET(GENMASK(15, 0), (n)) +#define PLL_CLK2_OFFSET(n) (PLL_CLK1_OFFSET(n) + (0x4)) + /** * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data * diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index fd8eb985c75b..81f44b94f6d5 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -87,9 +87,6 @@ enum clk_types { /* BIT(31) indicates if CLK1/2 are accessible or not */ #define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16))) -#define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0) -#define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16)) -#define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4)) #define DEF_TYPE(_name, _id, _type...) \ { .name = _name, .id = _id, .type = _type } From patchwork Tue Feb 18 11:43:52 2025 Content-Type: text/plain; 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Tue, 18 Feb 2025 03:44:08 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/3] clk: renesas: rzv2h-cpg: Add support for enabling PLLs Date: Tue, 18 Feb 2025 11:43:52 +0000 Message-ID: <20250218114353.406684-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218114353.406684-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250218114353.406684-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Some RZ/V2H(P) SoC variants do not have a GPU, resulting in PLLGPU being disabled by default in TF-A. Add support for enabling PLL clocks in the RZ/V2H(P) CPG driver to manage this. Introduce `is_enabled` and `enable` callbacks to handle PLL state transitions. With the `enable` callback, PLLGPU will be turned ON only when the GPU node is enabled; otherwise, it will remain off. Define new macros for PLL standby and monitor registers to facilitate this process. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 57 +++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 1ebaefb36133..d7230a7e285c 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -56,9 +56,16 @@ #define CPG_CLKSTATUS0 (0x700) +#define PLL_STBY_RESETB BIT(0) +#define PLL_STBY_RESETB_WEN BIT(16) +#define PLL_MON_RESETB BIT(0) +#define PLL_MON_LOCK BIT(4) + #define PLL_CLK_ACCESS(n) (!!((n) & BIT(31))) #define PLL_CLK1_OFFSET(n) FIELD_GET(GENMASK(15, 0), (n)) #define PLL_CLK2_OFFSET(n) (PLL_CLK1_OFFSET(n) + (0x4)) +#define PLL_STBY_OFFSET(n) (PLL_CLK1_OFFSET(n) - (0x4)) +#define PLL_MON_OFFSET(n) (PLL_STBY_OFFSET(n) + (0x10)) /** * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data @@ -144,6 +151,54 @@ struct ddiv_clk { #define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div) +static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw) +{ + struct pll_clk *pll_clk = to_pll(hw); + struct rzv2h_cpg_priv *priv = pll_clk->priv; + u32 mon_offset = PLL_MON_OFFSET(pll_clk->conf); + u32 val; + + val = readl(priv->base + mon_offset); + + /* Ensure both RESETB and LOCK bits are set */ + return (val & (PLL_MON_RESETB | PLL_MON_LOCK)) == + (PLL_MON_RESETB | PLL_MON_LOCK); +} + +static int rzv2h_cpg_pll_clk_enable(struct clk_hw *hw) +{ + bool enabled = rzv2h_cpg_pll_clk_is_enabled(hw); + struct pll_clk *pll_clk = to_pll(hw); + struct rzv2h_cpg_priv *priv = pll_clk->priv; + u32 conf = pll_clk->conf; + unsigned long flags = 0; + u32 stby_offset; + u32 mon_offset; + u32 val; + int ret; + + if (enabled) + return 0; + + stby_offset = PLL_STBY_OFFSET(conf); + mon_offset = PLL_MON_OFFSET(conf); + + val = PLL_STBY_RESETB_WEN | PLL_STBY_RESETB; + spin_lock_irqsave(&priv->rmw_lock, flags); + writel(val, priv->base + stby_offset); + spin_unlock_irqrestore(&priv->rmw_lock, flags); + + /* ensure PLL is in normal mode */ + ret = readl_poll_timeout(priv->base + mon_offset, val, + (val & (PLL_MON_RESETB | PLL_MON_LOCK)) == + (PLL_MON_RESETB | PLL_MON_LOCK), 0, 250000); + if (ret) + dev_err(priv->dev, "Failed to enable PLL 0x%x/%pC\n", + stby_offset, hw->clk); + + return ret; +} + static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -165,6 +220,8 @@ static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw, } static const struct clk_ops rzv2h_cpg_pll_ops = { + .is_enabled = rzv2h_cpg_pll_clk_is_enabled, + .enable = rzv2h_cpg_pll_clk_enable, .recalc_rate = rzv2h_cpg_pll_clk_recalc_rate, }; From patchwork Tue Feb 18 11:43:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13979688 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E481723FC68; Tue, 18 Feb 2025 11:44:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 18 Feb 2025 03:44:10 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:6940:cc67:5b00:b151]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f25915146sm14997029f8f.56.2025.02.18.03.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2025 03:44:09 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/3] clk: renesas: r9a09g057: Add clock and reset entries for GE3D Date: Tue, 18 Feb 2025 11:43:53 +0000 Message-ID: <20250218114353.406684-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218114353.406684-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250218114353.406684-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add PLLGPU along with the necessary clock and reset entries for GE3D. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/r9a09g057-cpg.c | 14 ++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 3705e18f66ad..ad1ed4ea1e01 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -29,6 +29,7 @@ enum clk_ids { CLK_PLLDTY, CLK_PLLCA55, CLK_PLLVDO, + CLK_PLLGPU, /* Internal Core Clocks */ CLK_PLLCM33_DIV16, @@ -43,6 +44,7 @@ enum clk_ids { CLK_PLLVDO_CRU1, CLK_PLLVDO_CRU2, CLK_PLLVDO_CRU3, + CLK_PLLGPU_GEAR, /* Module Clocks */ MOD_CLK_BASE, @@ -83,6 +85,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), + DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLL_CONF(0x124)), /* Internal Core Clocks */ DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), @@ -101,6 +104,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4), DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4), + DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64), + /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55, @@ -219,6 +224,12 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { BUS_MSTOP(9, BIT(7))), DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, BUS_MSTOP(9, BIT(7))), + DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16, + BUS_MSTOP(3, BIT(4))), + DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, + BUS_MSTOP(3, BIT(4))), + DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, + BUS_MSTOP(3, BIT(4))), }; static const struct rzv2h_reset r9a09g057_resets[] __initconst = { @@ -263,6 +274,9 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */ DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */ DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */ + DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ + DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ + DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ }; const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 81f44b94f6d5..3d3d4839d6d5 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -43,6 +43,7 @@ struct ddiv { #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5) #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6) #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7) +#define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13) #define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15) #define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16) #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)