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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 01/15] cxl: Modify address translation callback for generic use Date: Tue, 18 Feb 2025 14:23:42 +0100 Message-ID: <20250218132356.1809075-2-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6C:EE_|SJ1PR12MB6099:EE_ X-MS-Office365-Filtering-Correlation-Id: 773e8136-65f2-4898-dc52-08dd501f9619 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: UWqFhC0ELe/Xo6k0u9uovmPfspcf1DwbfIzRVHRhRsOmmbPvOT/HKNZQnUp2NKDlQJRS10I96eI56fjN5Jkcgd5Ma0RP98puUqptPW5aiU0EKhAaAlEx2cHnym9aOVXniy0VAYGGUEAAFD+tEuWyEPvHxwhrngSKz+3PL98slInkCPF6AOY+rMsw6bnPs/I0l1dC5nYPOIKFmVgxi+b4ZyRBDbKKjoKwxM1eLHW2GLzsvaew7B+ERme2VqsUV3qb+AzCdP9QnYW7/jrM/af7ze9ITeECEXlJaaK9LbvEwpLAV8yFQW1bLhnkuYg48/r1k1F5UU2uUBUkp3+2//44NxlfoNcpOf3P5JxRa3J4JFLq+c8Y2Kr2QT6XB1dvS+Yb9j6d88ffM7LyR2c1Q5gXYCCoBdd1cCM4v0eYJXiwxMMirswwz78m7lj/F5RkuKZ0eFI5ea7MNpbd78i1a4fKhrkPcWVY91a+m+Xq8P8dJV338Gy2ecm6Wqmsw6kZB2p3HgnLSRLVbHqRNt2VI0BMIxrYPWT1sGTq15IVmZWhTQal9ozjl32HtOAfTfuA+4aHBmuRuEtlDJ9C1VNdkKFCKnaO6Mi+8+vjceyMTQp+pCmfj/0FmIzl1c+LwqtzEThPnoKwMkScahVpJIO+LpBdNooLVo5h40pnbCz4ZJIWWBvBkhW/I5EvdpGnFDIhz7ziTCoKta7ysuRqcsRYiAGQAHTitjZUEh0vcVm3O+Wx+grDnT1LG1BCmN68x/bf0BXl20nAcQOz1SK58OeV5q80Rl+2p8WMAlBkl62RI8xcK/ildF95juMaawX+JT6AsdQOIaMJo4RjjXfBhkl9xtyjzvha3NVbXPatr3ZIgweNzkZnim1If9EjhbAUMXD3jkrlHtR6IhIxrtZAZcSD4GE+/BFd78pDJ11QlcpNDz34xXmgmZDQ6b7NqMNbmINqHojNCALy0xoKMvRFE1Z+9W6diUOGkIkWnSGj/OoaridOaNMyodFY20AWIM1TclCVVTY2+i4vOiQmuApXIMWRVQ2mUu6/F7ItkyFZEyobvRiIOHqFv1dAFX1wV4kFb1mKBcsDZ34pb9xq5qpOL0jBMEC+ZxwbpzD32ri/YND3kQRA0ANpfETAfraFHO8mjc+8DSk724N/Hn9De2pMaA4bbjuiHqyVMlcua+ZUX6diDuTjzsXNZQZKkqHWz/B+wp1aePs6TudIK/1lqEUtD4ZJjy8Hz2qov+z6lt01u+r+LMNJDp8GCDQz8WlYP4B6NUaNXGXOxILDeI+7cStrThLRHhSmZSmv2RTNhXjX8BR3B+bP8y76Rcd0iS14C4Plvo78mLZ3Eus8Mxbrqxlp/ZqmHwj5z6tV95BxVQ0i3M4r2bvW1Bd2hEDsP5UUvFUjsO6dMgM/d2S2XsI4XA+gXLJTyx48AkIWrwLoBjsmOWOP4GFS6uxV04gA44rFNImK2lPQzPGeOPpUGeMiamg6jaOvr8f/mMSzQAFJ8Bo8SKMk9qe18X4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:24:34.8495 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 773e8136-65f2-4898-dc52-08dd501f9619 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6099 The root decoder address translation callback could be reused for other decoders too. For generic use of the callback, change the function interface to use a decoder argument instead of the root decoder. Note that a root decoder's HPA is equal to its SPA, but else it may be different. Thus, change the name of the function type to cxl_to_hpa_fn. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/acpi.c | 4 ++-- drivers/cxl/core/region.c | 7 +++++-- drivers/cxl/cxl.h | 5 ++--- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 93c73b163c28..48ad90025d77 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -22,9 +22,9 @@ static const guid_t acpi_cxl_qtg_id_guid = GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071, 0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52); - -static u64 cxl_xor_hpa_to_spa(struct cxl_root_decoder *cxlrd, u64 hpa) +static u64 cxl_xor_hpa_to_spa(struct cxl_decoder *cxld, u64 hpa) { + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(&cxld->dev); struct cxl_cxims_data *cximsd = cxlrd->platform_data; int hbiw = cxlrd->cxlsd.nr_targets; u64 val; diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index a56b84e7103a..c118bda93e86 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -2936,9 +2936,12 @@ u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, /* Apply the hpa_offset to the region base address */ hpa = hpa_offset + p->res->start; - /* Root decoder translation overrides typical modulo decode */ + /* + * Root decoder translation overrides typical modulo decode. + * Note that a root decoder's HPA is equal to its SPA. + */ if (cxlrd->hpa_to_spa) - hpa = cxlrd->hpa_to_spa(cxlrd, hpa); + hpa = cxlrd->hpa_to_spa(&cxlrd->cxlsd.cxld, hpa); if (hpa < p->res->start || hpa > p->res->end) { dev_dbg(&cxlr->dev, diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 50e7d878bb6f..b19ba47242c6 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -418,8 +418,7 @@ struct cxl_switch_decoder { struct cxl_dport *target[]; }; -struct cxl_root_decoder; -typedef u64 (*cxl_hpa_to_spa_fn)(struct cxl_root_decoder *cxlrd, u64 hpa); +typedef u64 (*cxl_to_hpa_fn)(struct cxl_decoder *cxld, u64 hpa); /** * struct cxl_root_decoder - Static platform CXL address decoder @@ -434,7 +433,7 @@ typedef u64 (*cxl_hpa_to_spa_fn)(struct cxl_root_decoder *cxlrd, u64 hpa); struct cxl_root_decoder { struct resource *res; atomic_t region_id; - cxl_hpa_to_spa_fn hpa_to_spa; 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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 02/15] cxl: Introduce callback to translate an HPA range from a port to its parent Date: Tue, 18 Feb 2025 14:23:43 +0100 Message-ID: <20250218132356.1809075-3-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6C:EE_|SA1PR12MB5616:EE_ X-MS-Office365-Filtering-Correlation-Id: 8eb4ee00-51d6-4d78-395f-08dd501f983e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: 2MDUzt6dHjTRB0qcyVtwjSGo1KNTVnNEiU7vzYEACwBufOGUVU/1SlCOlJp/LTWhINTQaOdgEqkuB9I3ddlpQLqYOqEunOGxKYXwE2ULK1NonJvPoaZ/8khgxgkr1V17d+8JiC3YhjRA/trk580w+LDh1JRzgTfS346FGXxeVgBJPGL1Gi2heXW678sfWPbyaOaluwTnv1DFFAcOPujXA8Pw0SBWhaWKV0+zWqBQWSFF+vrpYxUl4mWuhPVTmAAC/WKsvxvy2RZ6kKAaGWPtX/e9PayKqnLpjnw9dtSM+9F1Nz1e27Hlqdke8jlhC9Jva3V9ridXu39539zo/taTh92b2SGd0Ycp6G1AfuyRBWYoLt7c5s7RLoH+ZWq9Np+LLFBdMYL5riUGdurWISFIwzkH/4magd1/O4/8ucGco3ABi/bfiTGncsOh18Tz6rL0h1qIXH3tVrr3I4LmjFXcUtg+dT0QrA6w0V0pvzTt1Ph5IbJ2C7VXdvePr9PQeI83UQf8A3oIcSGsqHkuknuOu25j3E5SW8lFZHWWVe7fOCLnKBK7cFSrl6ulrHKi/JiIyENksRniSHdd4US6XSEex4co69MzDRBF9E4745qbjJuG84OVMIDDpBpOHTp8xpUwxB+J0MaNmCrVbTGq6lQHptCtKbVE0XtXfyanq2zVCiJOv07gT9wgAbwdfpzuk8FxmdcQ8vjrFeLONEiN6VUwYh3SZxDRdRP89P9/dqvFAmHj2aK1zNCdQyGCIB63N1a3jz6XQnD8lWaF05BD0bZ8CzBa4aA44F0SU37BM2gJS025Q1do5J1mjfYQpgo2DVx+K/nmEh+pj9CBhctTGqV6X5SCdg8e2Rl7QQO9342y3zAfXD2jBay6KDJQrLOehmvuw0eiO/Q1o2Ya6MXT0yv0fW1Q53YsuEUmbWN3u6AZBJX+9PDGGz9G+2f1HMOD+SkUvE2LtnBnC/zqYkVIQ141Ntyd3HmAgjinql0FaJm6drpVJA5o9kz67E5uaJJ3ou3Uz2zZ+8jS2YSJbtJiSRiuiBbEjmuG8I+yIijexWP6m2Kvq6flIeEbZIe62394C8JftAKd1ce78bmJGPcQRWGLIKiB5AwxeF0eetjR/aIbxI5priIfAa38LrfFr52/NFh/ABrsaNBFAb2Q3TZOk38VR3njOIb0J0NFJYaHbDlsEjmlfG/GBPVoQXCkTKjcKKEZTAwXXwqea7jCZ94QDOhRNAp0x0xw9rWzbV8SHerIGDiRYaV6MkjICzRYqRmHQY6rQNfiCkwcas+txHdSxIl+R3J02efsFir5VCgWrwTK6cwWTFjmSrILJkWJ00CPlN8KmM7b7ao5zMrmYRvL+G1nPnXMLpGuUtwIArcIdv85Ng5v/2VNQVmgIfutFuI76TL0QHkZusrMlRUOMbz27D62LNz9FjrEY6ImnZfiTv+9yZ5bWBAU1VS40D2gBtqqsYV/ecyly3jGcwm+GZpCOCD4ZHzrrADufeHiCUwjvaGxToE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:24:38.4432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8eb4ee00-51d6-4d78-395f-08dd501f983e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5616 To enable address translation, the endpoint's HPA range must be translated to each of the parent port's address ranges up to the root decoder. Traverse the decoder and port hierarchy from the endpoint up to the root port and apply platform specific translation functions to determine the next HPA range of the parent port where needed: if (cxl_port->to_hpa) hpa = cxl_port->to_hpa(cxl_decoder, hpa) The root port's HPA range is equivalent to the system's SPA range. Introduce a callback to translate an HPA range from a port to its parent. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/cxl.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index b19ba47242c6..17496784f021 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -418,6 +418,15 @@ struct cxl_switch_decoder { struct cxl_dport *target[]; }; +/** + * cxl_to_hpa_fn - type of a callback function to translate an HPA + * @cxld: cxl_decoder to translate from + * @hpa: HPA of the @cxld decoder's address range + * + * The callback translates a decoder's HPA to the next upper domain + * which is the address range of the decoder's parent port. The return + * value is the translated HPA on success or ULLONG_MAX otherwise. + */ typedef u64 (*cxl_to_hpa_fn)(struct cxl_decoder *cxld, u64 hpa); /** @@ -581,6 +590,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @to_hpa: Callback to translate a child port's decoder address to the port's HPA address range * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation ordering * @commit_end: cursor to track highest committed decoder for commit ordering @@ -602,6 +612,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + cxl_to_hpa_fn to_hpa; int nr_dports; int hdm_end; int commit_end; From patchwork Tue Feb 18 13:23:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13979820 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2071.outbound.protection.outlook.com [40.107.223.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D32202698BE; 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Tue, 18 Feb 2025 07:24:39 -0600 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso CC: , , Gregory Price , "Fabio M. De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 03/15] cxl/region: Factor out code for interleaving calculations Date: Tue, 18 Feb 2025 14:23:44 +0100 Message-ID: <20250218132356.1809075-4-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6A:EE_|SA0PR12MB7076:EE_ X-MS-Office365-Filtering-Correlation-Id: 45be2ac2-1fc1-42a4-99db-08dd501f9a88 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: K1Qw3Mv4B3NDGphkz1RRnoUKYDOFiOTdGnI2wnW1bf3msd419sx8mok5hu6V8cCSguPi3HlP5FFVYKkEjH+uyfA60x+GBNGD9hThbmF43xhJ9PVrxFRrX+J7n4+K2O12EBjn+YMY7JL2jJmBaFGnW9uAHjiPWqGP7gNQz7P+Kd8K+DKwtkiJNk+G6ngzgGc7+HAHRuP9aYTK3a/jRm6l8cUaVrgLPhjI8F1zVT8HoAm0X8WA5e58Ss924KKxZclZoVPigT8gXmvHljI3fXw9WmgplFLAb1hyU+ZclYIWfFcJJh+3dII0da25HzaGSLxyDQRssARzMYINyvRzSW6vQoaWTSdtc2wNihqSv0xBcxLBqtLVdtorBUI+a3AKD5bZjryPG5NmGneR7JsSgh13kj+Aw/QQmjuRLjQEM+Y7gYYSGX6GcbUeKwxgJ7q0lxsIt/uVIxCKs2aNxG4Di7pf/C2/zVued+P2KFbXPI1/jHjZgF3Uq215BZ22dGJ1VjA/EqoQzAMeWoUf7iMvj0UiDTlIwZHZniCStNSZIVQ+ROF+mf4UCwB3cJk4R5EBxiI8EQgfC6OAKclUTA1lhM/kRfUM6LXqwWM4mUd4fuO8t0ZXOIJBnKpNruLc6fIZmPDLACLFpzSShtY52sEIOhgDYT+mimV2nhtcxQXLdMHJak8CsAOFM70dHmkCq9WmHWF5ZNAhVm2Vjlf5mLaGFiivYKasYhQCtpXN0U9X6dOkxvCBxG3Hx5JYdl0LB3AwVd6aN+XDQQUK/0h+SOp7SQH5r6zsZA5er3Bs6aZTEbv7sDF8RhqxOda1u9wnglMVztoOnIEmTOxBwlAGvvbvs1rHx+ygc10ADuqnzWyRP9IrnmVopr/VHhxV16QT0zA9mTsaJ4UWvDZ2Dmco1Fx4qIF6RbqHtViRl91UEA5FBWt2Z/LqNh6o07FmjuxaKqhsqDrUSGEG5ebFzXicx0MI8r0bRd7qKQRKZp1qACiQx+gCn2tVFHmhlbMav8/+SizONRvbNTLRRfWX+sUo+oqsZfOMNtB/SvHNPNooHlOWQB9KDmFvwL9wKKSMPehJT7Y6hNqNJhYrssTdy8o0FE68Rq0A9Suv3peGOeTMeygvjdFdF/zT1xJT86yLS2MtzOH1e72p2zjYbmemgYFr5epYwRgiTkfBnrbVnR+nekQEPZ47ZPI7F91c3M5iNy942hgUFrShBG5Bmp1GJG8OFQOyR6DSCWAONu06wVkkrFkamOhkNTTZVFeDyBj3qhwULC5oJKjVOIb0WhzEnA4S/kKy5V7Emacz5IrqjuubxWtdQe75zRTW+QqJtMnXz5sth5B46xKnS3EFUOyhj4n0yCLybiSiBjAiFqvgdiOMQr1hj7Hmx5sYNAymmw0pEYPk/Nv2OxUKv4pa34QkA1d1zSqAQewx4963eq2osUNw0sLuVxgxg80JHfndj9QEbUsHlElrJIyrgCvUHuxqg3ey+hm3KQBBnNKrhKfM8dg3Hscft+IDsy0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:24:42.3017 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45be2ac2-1fc1-42a4-99db-08dd501f9a88 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7076 Function cxl_calc_interleave_pos() contains code to calculate the interleaving parameters of a port. Factor out that code for later reuse. Add function cxl_port_calc_interleave() for this and introduce struct cxl_interleave_context to collect all interleaving data. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 63 ++++++++++++++++++++++++++------------- 1 file changed, 43 insertions(+), 20 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index c118bda93e86..ad4a6ce37216 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1800,27 +1800,34 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range, return rc; } +struct cxl_interleave_context { + struct range *hpa_range; + int pos; +}; + /** - * cxl_calc_interleave_pos() - calculate an endpoint position in a region - * @cxled: endpoint decoder member of given region + * cxl_port_calc_interleave() - calculate interleave config of an endpoint for @port + * @port: Port the new position is calculated for. + * @ctx: Interleave context * - * The endpoint position is calculated by traversing the topology from - * the endpoint to the root decoder and iteratively applying this - * calculation: + * The endpoint position for the next port is calculated by applying + * this calculation: * * position = position * parent_ways + parent_pos; * * ...where @position is inferred from switch and root decoder target lists. * + * The endpoint's position in a region can be calculated by traversing + * the topology from the endpoint to the root decoder and iteratively + * applying the function for each port. + * * Return: position >= 0 on success * -ENXIO on failure */ -static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled) +static int cxl_port_calc_interleave(struct cxl_port *port, + struct cxl_interleave_context *ctx) { - struct cxl_port *iter, *port = cxled_to_port(cxled); - struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); - struct range *range = &cxled->cxld.hpa_range; - int parent_ways = 0, parent_pos = 0, pos = 0; + int parent_ways = 0, parent_pos = 0; int rc; /* @@ -1852,22 +1859,38 @@ static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled) * complex topologies, including those with switches. */ - /* Iterate from endpoint to root_port refining the position */ - for (iter = port; iter; iter = parent_port_of(iter)) { - if (is_cxl_root(iter)) - break; + if (is_cxl_root(port)) + return 0; - rc = find_pos_and_ways(iter, range, &parent_pos, &parent_ways); - if (rc) - return rc; + rc = find_pos_and_ways(port, ctx->hpa_range, &parent_pos, &parent_ways); + if (rc) + return rc; - pos = pos * parent_ways + parent_pos; - } + ctx->pos = ctx->pos * parent_ways + parent_pos; + + return ctx->pos; +} + +static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled) +{ + struct cxl_port *iter, *port = cxled_to_port(cxled); + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); + struct cxl_interleave_context ctx; + int pos = 0; + + ctx = (struct cxl_interleave_context) { + .hpa_range = &cxled->cxld.hpa_range, + }; + + for (iter = cxled_to_port(cxled); pos >= 0 && iter; + iter = parent_port_of(iter)) + pos = cxl_port_calc_interleave(iter, &ctx); dev_dbg(&cxlmd->dev, "decoder:%s parent:%s port:%s range:%#llx-%#llx pos:%d\n", dev_name(&cxled->cxld.dev), dev_name(cxlmd->dev.parent), - dev_name(&port->dev), range->start, range->end, pos); + dev_name(&port->dev), ctx.hpa_range->start, ctx.hpa_range->end, + ctx.pos); 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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 04/15] cxl/region: Calculate endpoint's region position during init Date: Tue, 18 Feb 2025 14:23:45 +0100 Message-ID: <20250218132356.1809075-5-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F69:EE_|SJ1PR12MB6313:EE_ X-MS-Office365-Filtering-Correlation-Id: bb1d637c-336e-4408-a2cc-08dd501f9cac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: WJy4tWtBBhXI+ICZ4ZBR3tBDeb0g2qCIU3yZE17PTrR3yeryyyKDMUQ7rwH0d/eDd0F14cDGbDhjhoDu2g+FUXLStHzYnmLq8fmat7No81N5JRZLRWopVn0FRzlL5Lj6ZRLFVCayEUp7UMbtmtdDWG1UiVdf5RB91clDLKH4W0Rc7gvrzuLFyANv4mim23OYG3IfW4Jxj2CSAwVJ9cSlv0Di6y3sKZLU5xeE4noIEFR7xJ4BQ4hZTA/mVR4QaL9OjADJxZvu3VhV/7/ImDUUiQ0c5J8vwYotLSzNBCAO8aof1r/jNx7gXUaZoXLtdLauj21dGnz2A1yUUUKaAMFEgXpLGJGzn4U+CoYLVwmN35VyECh4nXi0wVqcBf0o9CvXeQY9Lq6i/oXyXSBBN3XNEssWz/W897KsC2eVsIv3UsGJLGip3csTpqz9g4yW66+wvvpR6fmSxjatpHTwcl767A/dnI9m11p1vHMquJrA23XfXR6XRZqA2LVvQYZbUVBBlOuYFxdMuFgr134doVBhaLQQdVXSkCJggViGs5YIEggfu83Pp69KrQ8Uqo4swul+F7P/IIM8TIiLB0u/VIuikHmtyM6+Cr4WhhRdgUtPgdF1bqqBan3kGgsz88aK5G/MMTF01Rk3h+ia5p3XDudAhyddpDsF0yRbbREsOLJXwEcOHXhXCE8+2LYlhfMbdUNzkLLTsLCRSOSh9ZFiNrMWUcpD8YDpHb8L7PmXz7XgAzUb6cQise9lIqNVzqssdzG4CmXaWjoG3xvJb58aDBMstE3b08GX3ReyIYTCQj4HBBAj4koP4qV/VY4fsOTzDWW/v7i1ZRNBywRO70lspgw0mW0zBN98BlSBsFlgEcDFV26vyRf/sOXUy7+t47Dgj1OT/5YMbHnuam8xAQ86/SRl1VNJdYvBLP4PbJLaOHD9ffWppLk841T/LsMdedcrPfKfwqWBh1uRv/a9KU559VVmG+foHPY7CI41GUMD36422ZYe6JHeJmzF3hXhD3WOtScX7iePTlpTFVLhijpiezOQ5Ilrjnfv7brIaSirR4sg6anFP0FLnc0mYbpHnbQ/YrZcJST5Y65nyRvbQWUh5n2HWev46+qiMtoTVxYaXkIg05//cJLwv7/XLMk9/X8XJ6y6jkaXFuJHOAaY+wtHvVt83yQxnWh+MQrrFLyVh8m0BF25qJy5/9FcrRo2ciXafJXI/PJ6mXyKsutdRo4p1OphCO+kv56MJPsOfIhdC4z2krpgjOe3Qqkt7fA/JJga1uJa5NF/zcS0hygbJcBRf7u4uQFiZ0sckaPYk8tNMyVhHUpryWGINfLS02zCxfv9DrxYQjRVEDFS1Qguk1A7q2IhT86bcHIRlNFKGp7IYYYeWG3ACh3X7nr5u83ZF+QvmEOmfiqSoQ81s0Az3ckui+dywwW2N0AqBtIX/2fUCAWEjjghe8P3C0ea+t6a5aNxPT59xB6/bZZj0p2k/VDH2wu0v0zHADyxZIEQNX3mufpIqB0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:24:45.8777 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb1d637c-336e-4408-a2cc-08dd501f9cac X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F69.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6313 The calculation of an endpoint's position in a region traverses all ports up to the root port and determines the corresponding decoders for that particular address range. For address translation the HPA range must be recalculated between ports. In order to prepare the implementation of address translation, move code to cxl_endpoint_decoder_initialize() and reuse the existing iterator there. Signed-off-by: Robert Richter --- drivers/cxl/core/region.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index ad4a6ce37216..6f106bfa115f 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1903,7 +1903,6 @@ static int cxl_region_sort_targets(struct cxl_region *cxlr) for (i = 0; i < p->nr_targets; i++) { struct cxl_endpoint_decoder *cxled = p->targets[i]; - cxled->pos = cxl_calc_interleave_pos(cxled); /* * Record that sorting failed, but still continue to calc * cxled->pos so that follow-on code paths can reliably @@ -3264,10 +3263,22 @@ static int cxl_endpoint_decoder_initialize(struct cxl_endpoint_decoder *cxled) struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); struct cxl_port *iter = cxled_to_port(cxled); struct cxl_decoder *root, *cxld = &cxled->cxld; - struct range *hpa = &cxld->hpa_range; + struct range hpa = cxld->hpa_range; + struct cxl_interleave_context ctx; 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Tue, 18 Feb 2025 07:24:46 -0600 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso CC: , , Gregory Price , "Fabio M. De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 05/15] cxl/region: Calculate and store the SPA range of an endpoint Date: Tue, 18 Feb 2025 14:23:46 +0100 Message-ID: <20250218132356.1809075-6-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6B:EE_|MN2PR12MB4437:EE_ X-MS-Office365-Filtering-Correlation-Id: ea81596a-7be8-4c7b-0b52-08dd501f9f0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: Iz78sn5QWnLjJT3SQBInOUfWTV7lSRJnWW42AshzB9leO0yw08z4Wu5tXcetlKKkB2Ylk4eBBsdO4fS3/m1pWbEqw7B4Cl6M9E8KHpNABaOU62X2kmluUpBDyXWu1Bhv9FaSl1Ypq0Cx+5todnms+ClPVoXusu/kkVy2i2U1cxBMJHfzZnmed+aSKpSHY/2MPzOwgf+NGnHRKXGiIVGIp2Bd3L7Ywz/z3dhJ0mf/aP9XqNPuVp8UJiWNGxj8Y34S6PWAQYacsUkLsUrjkLgAEU8/tg7BvQhjEMx6spOhbAoaw9OGrb4R9dGqIQh0XtnLcWUO3+uw9XteSGdDqcEY8+R0TmOifxyIb8FeuPGmsZZFWNgVVznGQmzZKkc4lETzCoeeHcuyhEB2ASLyTz1zSGbQ3qBvRYyTKzHGcn4L0FjNTN7qTY4uH2BNYfKPM8tgMe6XeUirdRsjqHpJ9kHpCxVLFa3ZusBv862D32K0oVhKlK3AzQgoPTFvuhUNZ3Yl+4Tqu7twl98tV8fsjhb8/ntg5ObQoHDDckMBKCh9yQQI5krMAjj4ha1wC+9WOPE5JK7XWrqCkJdm5tys5Jim3xVBFgQpj6N1YdALKT34K/M3cuqnMNwgWvSM29ZpNMoHlBKikIjRoSEobiWWk+l3P9Uja6yaiuBn/72O1ZqQgJ/bGGyJZmbpgkzghIt3FriOXZ+0bDzq2rbkv21NQhMhO7ZHOoFZgKiazYOCBjbyumw+FPWI8D/KqneeRZZdc6OApCIj289jBt7UXQtEfE41LojxJd9/Z2q54vlPbpmJD83w12nqyY2HIQ9spubMvwoV9qQ4/aLDhx2CZLL7B+cKpu9jYa7gk9u6u0i2lqiN9q0ysjoYzGDmp7WLL/VnWysuIYMwZn1g8GIIeMdxpyfYKFnlZUQc95JgjVMPQL/0f/PIxRSXaq1bwNzcoABk+/FFaLAceDz2mhQWTEMymSF8oi4Hv5bzKGDSB+NpWG+gOkDgobCJvVlKjK6zKxl9g1bZscQgMBQo3/yE+6sbEo/umIxrsATz05t+GEMqj+6IUsbu5YZ4KfoQCMiwo0tHnAVoiA9JgTM5XogtJp5D2c1U81oAkQusy4rC40T7kxlYWdaQmMzJrHxba/k4+35XRsuRWgvbXi7uF7isFkzenW6BPafaIfHhbBhJYS38jn++3l7juDbY3W5ggsheYPzUB9Bim1LKdSPBf9/MQ74M8DfiXDlBh9vTvKwyA9NabCMldU2Wu2YB0mrrjZ20QAjncUCqGrohNd9A3y/ciub6Opc4GOr2+pNSmvxzwz3Kni06AJX9RrtlN2OKf90qqmF73UjMn59Y4LvUPmmOHklLovelIKsZMKGvtdu4sEpyb+jcsNsTvhQes+mi7uewDny5+c50clltGPlCwE70v9PiNy1GrYmEf8po7JXB7itihgPTU/2Febom6XZXtY4Xd/JwtU0lSSuAIAx7vnlYm1Gmtx242CysvHgXD+hkkUWFcBD7S08= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:24:49.8740 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea81596a-7be8-4c7b-0b52-08dd501f9f0c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4437 To find the correct region and root port of an endpoint of a system needing address translation, the endpoint's HPA range must be translated to each of the parent port address ranges up to the root decoder. Calculate the SPA range using the newly introduced callback function port->to_hpa() that translates the decoder's HPA range to its parent port's HPA range of the next outer memory domain. Introduce the helper function cxl_port_calc_hpa() for this to calculate address ranges using the low-level port->to_hpa() callbacks. Determine the root port SPA range by iterating all the ports up to the root. Store the endpoint's SPA range for later use. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 81 ++++++++++++++++++++++++++++++++------- drivers/cxl/cxl.h | 1 + 2 files changed, 68 insertions(+), 14 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 6f106bfa115f..d898c9f51113 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -832,6 +832,44 @@ static int match_free_decoder(struct device *dev, const void *data) return 1; } +static int cxl_port_calc_hpa(struct cxl_port *port, struct cxl_decoder *cxld, + struct range *hpa_range) +{ + struct range hpa = *hpa_range; + u64 len = range_len(&hpa); + + if (!port->to_hpa) + return 0; + + /* Translate HPA to the next upper domain. */ + hpa.start = port->to_hpa(cxld, hpa.start); + hpa.end = port->to_hpa(cxld, hpa.end); + + if (hpa.start == ULLONG_MAX || hpa.end == ULLONG_MAX) { + dev_warn(&port->dev, + "CXL address translation: HPA range invalid: %#llx-%#llx:%#llx-%#llx(%s)\n", + hpa.start, hpa.end, hpa_range->start, + hpa_range->end, dev_name(&cxld->dev)); + return -ENXIO; + } + + if (range_len(&hpa) != len * cxld->interleave_ways) { + dev_warn(&port->dev, + "CXL address translation: HPA range not contiguous: %#llx-%#llx:%#llx-%#llx(%s)\n", + hpa.start, hpa.end, hpa_range->start, + hpa_range->end, dev_name(&cxld->dev)); + return -ENXIO; + } + + if (hpa.start == hpa_range->start && hpa.end == hpa_range->end) + return 0; + + *hpa_range = hpa; + + /* Return 1 if modified. */ + return 1; +} + static int match_auto_decoder(struct device *dev, const void *data) { const struct cxl_region_params *p = data; @@ -1882,6 +1920,11 @@ static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled) .hpa_range = &cxled->cxld.hpa_range, }; + /* + * Address translation is only supported for auto-discovery of + * decoders. There is no need to support address translation + * here. That is, do not recalculate ctx.hpa_range here. + */ for (iter = cxled_to_port(cxled); pos >= 0 && iter; iter = parent_port_of(iter)) pos = cxl_port_calc_interleave(iter, &ctx); @@ -3262,7 +3305,8 @@ static int cxl_endpoint_decoder_initialize(struct cxl_endpoint_decoder *cxled) { struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); struct cxl_port *iter = cxled_to_port(cxled); - struct cxl_decoder *root, *cxld = &cxled->cxld; + struct cxl_port *parent = parent_port_of(iter); + struct cxl_decoder *cxld = &cxled->cxld; struct range hpa = cxld->hpa_range; struct cxl_interleave_context ctx; int rc; @@ -3271,25 +3315,33 @@ static int cxl_endpoint_decoder_initialize(struct cxl_endpoint_decoder *cxled) .hpa_range = &hpa, }; - while (iter && !is_cxl_root(iter)) { + if (!iter || !parent) + return -ENXIO; + + while (iter && parent) { + /* Translate HPA to the next upper memory domain. */ + rc = cxl_port_calc_hpa(parent, cxld, &hpa); + if (rc < 0) + return rc; + /* Convert interleave settings to next port upstream. */ rc = cxl_port_calc_interleave(iter, &ctx); if (rc < 0) return rc; - iter = parent_port_of(iter); - } + iter = parent; + parent = parent_port_of(iter); - if (!iter) - return -ENXIO; + if (!parent || parent->to_hpa) + cxld = cxl_port_find_switch_decoder(iter, &hpa); - root = cxl_port_find_switch_decoder(iter, hpa); - if (!root) { - dev_err(cxlmd->dev.parent, - "%s:%s no CXL window for range %#llx:%#llx\n", - dev_name(&cxlmd->dev), dev_name(&cxld->dev), - cxld->hpa_range.start, cxld->hpa_range.end); - return -ENXIO; + if (!cxld) { + dev_err(cxlmd->dev.parent, + "%s:%s no CXL window for range %#llx:%#llx\n", + dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), + hpa.start, hpa.end); + return -ENXIO; + } } dev_dbg(cxld->dev.parent, @@ -3297,7 +3349,8 @@ static int cxl_endpoint_decoder_initialize(struct cxl_endpoint_decoder *cxled) dev_name(&cxled->cxld.dev), dev_name(&cxld->dev), hpa.start, hpa.end, ctx.pos); - cxled->cxlrd = to_cxl_root_decoder(&root->dev); + cxled->cxlrd = to_cxl_root_decoder(&cxld->dev); + cxled->spa_range = hpa; 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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 06/15] cxl/region: Use endpoint's HPA range to find the port's decoder Date: Tue, 18 Feb 2025 14:23:47 +0100 Message-ID: <20250218132356.1809075-7-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F68:EE_|BY5PR12MB4052:EE_ X-MS-Office365-Filtering-Correlation-Id: 0b23a6e4-985f-490b-0144-08dd501fa128 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: emNtCuR62L0ZG1UxHpDuYfmKJESTqxEFE8pBEINir6pQZxzV6u+sbx2gYOqi/BWEcWxgdUY0M1L1MUbvhVKLS7SturrY3TYuaRbZ6eoQhODyslxAbCzpZ3eYFE+lyZg0MJPx9T5nVGICZZ/58YkHH+bqkPbGk59d3sTcyVd42xHqMOkKcbSvfbOV3JPsdpPJ7GUhJxGg5Z3ESS2cGLPV40/hyQd4ie54Agohroou3fhPZbD+auatYl1CF2zIusyCysqQnTRGeCUvhlmn33W+QP8a9HLmMQn4OjCdlguJ8ZNkqETSDeN6hS7vAq9zUn/KwS2QZ7M2QLXR1dzAYBK7Z9OVBYsdu+zeMQbWLvnKVP4OjQJ3gXIXhRHTMEeAmHHmaZ4H+5W7sWKrF2r3XAec9RHPUXyDyLA2rBK4FtQn4jWU5xNjkqafKx7Px8CogcwNh+AT9sCJvMywDZqneZ9bgrunnT6cg0yoRxGEhzcXikthrHs4WYiq3nROcyHL+TPPzE3g4NnT8ideebD4atg4pp2YtxwFWKkHWdZCQdyaxdopn+O2yQAXbZ5U4XDnDuKG3zOKpOhTmqeVcKyigJ5iPrMOHyi4dS3pp7AX6uDukidur7hdxSYMj66xFoNHHlaELOCntTmpZm2ULjSfFf9hj9xF1QtvtoxmlAGeSQFlDkt2euMQxPlsULDZ9q1ueEE5NaG2w/veNoObFFScv9zDrluoBMzpQM6aWES5GUjNWDlReGqYufJOS42QeaCCXQrCRgg97wzPK8Oj4V6vd26MzxZgxp8kSM3wC6RX4TenyUP3/hlnNW80o2IXs7E6zpy8fOPOtgn6VSSX+YPqx+IYQuYh0YT2x+hQ8EKvBFasnsrWbSIFPwBtsEp8hs8JQkHZuxHeklDUJZMtoyctEqq3OHfXMarB/GQQvziCytzsWWTHjhA5B5MfWyK3q3uShTYwsr33gQHTXhiuvt09ZssBYduvgdU2vxayb479qR22tFEksF+JXts2fFIWEdnmyRYjm7afgjK8Wl7aKa+mAvX5w/fmY3Q4ls6L0Lb/+bTydqQ6ENVP7FkpH/LX3X1aS+cW7E1cG959q8+xj/iKLGsynD3ubK2y8M/VmGlIwTFEpf7ktWQ/6sI9tuNz6FVqAusTS9EkJdU/l/rnqQwXw6oEbvaI3HV9E/mgHgGHlvZb7X7zdt+6XxC9dF9fow8IzXhC0RhRJP7npnPRlthwD01635elu6rS1UIX34FlJm0PFJ9ic2l3QjXvWmQKoluQVuFiY4zb5/B/Anw1uaC8RHO9Q5YkODJo19rU8DDH89z7GgJ4+ATq/kxyaMiuvweZx6dvNKLvrCj7wsH74dmENOn2+lplyCgJCvtdoCoqf0f3A3WWApfe0gMO0wZJzznHlZCeZyBcGeC1kd+j4FxWO/bOo4Ysthmf/XRFI4f2fsIon/p78Ag/3rzwX+o1mB+vc6tsdZ1Yodsi7TgWsg6BkTfeULDxGoKMmY98GCThRHW/1p0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:24:53.4127 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b23a6e4-985f-490b-0144-08dd501fa128 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F68.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4052 For the implementation of address translation it might not be possible to determine the root decoder in the early enumeration state since the SPA range is still unknown. Instead, the endpoint's HPA range is known and from there the topology can be traversed up to the root port while the memory range is adjusted from one memory domain to the next up to the root port. In a first step, use endpoint's HPA range to find the port's decoder. Without address translation HPA == SPA, so the endpoint's HPA range can be used since it is the same as the root decoder's. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index d898c9f51113..5048511f9de5 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -872,9 +872,8 @@ static int cxl_port_calc_hpa(struct cxl_port *port, struct cxl_decoder *cxld, static int match_auto_decoder(struct device *dev, const void *data) { - const struct cxl_region_params *p = data; + const struct range *r, *hpa = data; struct cxl_decoder *cxld; - struct range *r; if (!is_switch_decoder(dev)) return 0; @@ -882,7 +881,7 @@ static int match_auto_decoder(struct device *dev, const void *data) cxld = to_cxl_decoder(dev); r = &cxld->hpa_range; - if (p->res && p->res->start == r->start && p->res->end == r->end) + if (hpa && hpa->start == r->start && hpa->end == r->end) return 1; return 0; @@ -906,7 +905,7 @@ cxl_find_decoder_early(struct cxl_port *port, return &cxled->cxld; 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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 07/15] cxl/region: Use translated HPA ranges to find the port's decoder Date: Tue, 18 Feb 2025 14:23:48 +0100 Message-ID: <20250218132356.1809075-8-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|SJ0PR12MB6853:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f6cdeab-767c-4ff3-f67c-08dd501fa35a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: xMh+SdTfkbWLaGwIbtM6uDzZwUqIcpQv5SlfqYVd6bhYtklCXo9hweaKykONbiT8QHC5c5l6luU8K0y0QHXCIgBCw//mUq9xuIIjTOaSM7FrmQdsRNGRp86TWvuPIMoMiYuLsF6CFDLvqDP84fBO311vN2XJtc0wdMiIfGYCaxgZWG4LndVKfYiQuryeSi47/o+ee4/K3zBJNLnBQwnTCnpP2fcAVkcwqzQa4lL5Gxom2r0JpTvwbge+mUiBMYJXLzphDrRB7TpEe3fiGxyN0gz/4M7t/CNC/qHUH5EYpjV8XMYVnFi7bS+NSGiPEjTrUzGkeq1/rNB2JNQGXTvUml3j6CpaEuF71OsnkBiPFVcK0PIGCXApTJyR4Fhp27aWReBp4HgrI68mjVaobtgH3Ze2AocD0CUUaM5iHG6HzAxvP5+pZ2Fb+jf24E0ChltowAB7VgnK6xp4FFGgeY5s0WO4HbHz7ANS1MIt1DHewbA1hlvu1Ar3h6iMd5ZPw/UStfCLAV/2E+6Jpw7Ry1MdiJ/RxJkiXSRXzNMl0PAa61vMMp9kh09D+m9OO9fe6AuZdHntZdoXKxTUqeEi572IU9zbetMT89pJqxlgIlZspWRjPA4BUWdGgYf/sRDehNkNIWjqz0iCQlS6QbaQT8pJ5B4IaA7Nx7WIpKVTGNLNGvwR29MCgJdSTr1wN7xWUh1IV6qP7JQS3vxwFPt+hj5D5QlvPRBdUOmNAuMpQIDtL4iHW5XFyUWOYxBJI29stKMXCqteNbYRjkzOI/wY1PaFx+uft+hhjf+mJovIg+UYLBshh+d5vZ90g7i2/is9tKYdYnpVlypAnvn5OqbhZ2gr8p+79oASkNEiStmL1Z80OlsFXMJfVB4/y77ZftT69vVGN2BRMWD06QrgF3Y84Sy8t1IhwRuoXdGQlMwIiQCSIqTUz/6mZ+GvIYLFSfMGx7b0ieZQPWlfwH9abR6MNjT7RM/H0wY0AgrDl7WSrlEvdSTV2h7zPJFz2aebUXjHdPyKQliDnC4xdjRLjEQBgvnmOfABqqWOD+/zBmEwMmBnq67a+iA72hDD+TT3qc7BdSm8uYR2t8UPKCqD3e4gsjPL4506Q3c9/BLZL76H2KOpc0MD3Rr8LGEWgFqMnuYK8JPJcC1irSqVyWFAhwP9c2K47ByfmhrftyzC3PRK9u7lFCvxMUs8kbdiGcG/17B+VdBqsDDekS/pbrWGEhuNvSHylgEk406FDi7sgjU5ln8VF50VRs4MsAgqtCAP03mlbgUFqmxA8Rnpe1q1+GxxEOJrVwd7jZE0nyGbJp3UPpq1sQNa41uhPl6U8AFBCSLLAv/Try7CA2vzxx09TDbOkm3tQSJuKeyAOIARyfQprnatpKaqsiC/jqUv0JyjijH3Ra0hGNT7xiaeZB/OU7v/iwowwNL/fRGm9sOmReJFNjOidN99h/0OC4XOLdVNevFuW+9mK6TUksQ3MMpfKxq6DyXOpJcVDBjr7Mp6orTCOsjFX/g= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:24:57.1021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f6cdeab-767c-4ff3-f67c-08dd501fa35a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6853 This is the second step to find the port's decoder with address translation enabled. The translated HPA range must be used to find a decoder. The port's HPA range is determined by applying address translation when crossing memory domains for the HPA range to each port while traversing the topology from the endpoint up to the port. Introduce a function cxl_find_auto_decoder() that calculates the port's translated address range to determine the corresponding decoder. Use the existing helper function cxl_port_calc_hpa() for HPA range calculation. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 60 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 5048511f9de5..6d5ede5b4c43 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -887,6 +887,63 @@ static int match_auto_decoder(struct device *dev, const void *data) return 0; } +static struct device * +cxl_find_auto_decoder(struct cxl_port *port, struct cxl_endpoint_decoder *cxled, + struct cxl_region *cxlr) +{ + struct cxl_port *parent, *iter = cxled_to_port(cxled); + struct cxl_decoder *cxld = &cxled->cxld; + struct range hpa = cxld->hpa_range; + struct cxl_region_ref *rr; + + while (iter != port) { + parent = parent_port_of(iter); + if (!parent) { + dev_warn(&port->dev, + "port not a parent of endpoint decoder %s\n", + dev_name(&cxled->cxld.dev)); + return NULL; + } + + if (!parent->to_hpa) { + iter = parent; + continue; + } + + /* Lower domain decoders are already attached. */ + rr = cxl_rr_load(iter, cxlr); + cxld = rr ? rr->decoder : NULL; + if (!cxld) { + dev_warn(&iter->dev, + "no decoder found for region %s\n", + dev_name(&cxlr->dev)); + return NULL; + } + + /* Check switch decoder range. */ + if (cxld != &cxled->cxld && + !match_auto_decoder(&cxld->dev, &hpa)) { + dev_warn(&iter->dev, + "decoder %s out of range %#llx-%#llx:%#llx-%#llx(%s)\n", + dev_name(&cxld->dev), cxld->hpa_range.start, + cxld->hpa_range.end, hpa.start, hpa.end, + dev_name(&cxled->cxld.dev)); + return NULL; + } + + if (cxl_port_calc_hpa(parent, cxld, &hpa) < 0) + return NULL; + + iter = parent; + } + + dev_dbg(cxld->dev.parent, "%s: range: %#llx-%#llx iw: %d ig: %d\n", + dev_name(&cxld->dev), hpa.start, hpa.end, + cxld->interleave_ways, cxld->interleave_granularity); + + return device_find_child(&port->dev, &hpa, match_auto_decoder); +} + /* * Use cxl_find_decoder_early() only during region setup in the early * setup stage. Once a port is attached to a region, the region @@ -905,8 +962,7 @@ cxl_find_decoder_early(struct cxl_port *port, return &cxled->cxld; if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) - dev = device_find_child(&port->dev, &cxled->cxld.hpa_range, - match_auto_decoder); + dev = cxl_find_auto_decoder(port, cxled, cxlr); else dev = device_find_child(&port->dev, NULL, match_free_decoder); if (!dev) From patchwork Tue Feb 18 13:23:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13979825 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2048.outbound.protection.outlook.com [40.107.220.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 419412698B4; Tue, 18 Feb 2025 13:25:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.48 ARC-Seal: i=2; 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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 08/15] cxl/region: Use the endpoint's SPA range to find a region Date: Tue, 18 Feb 2025 14:23:49 +0100 Message-ID: <20250218132356.1809075-9-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6D:EE_|DM4PR12MB6325:EE_ X-MS-Office365-Filtering-Correlation-Id: 91b485be-534b-4767-a577-08dd501fa589 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: NpHHNeKB/9Pu8b/i6Hhoza4qgOgbhi4Uh72EaLviS5QXbYaKI1omNKRLCU+dPgemA+sk+ayjovQXoor4uuHATh56w44dRLELCWhXSSgdV+JlURPvuRboiNp6dVHhRSrTVdqj07xLtUsCO9cHcbsr9yJ3KqWxYkO1FketkkBqkfNAUHvCaB2gaI3zy2gOqpIw8f2kyTaD4KHgJHxgA8m5mgLPuQ/kqwKmHQimsQCozSk0ho3TlKakLtPXLODfqh8EsxqvX7tb0dr96QkkIrz08IA50x5qmwqHfUn8H2zXr9J8DZsVsMoQsbYnWG9OWIRJplfNEqE3zB5VDjOSUd3njIQTLnZFJGB5BMEF6QGXSPgwHXGui+pdsKaxBYUJhzhSzP3DH5ExG9xE1JG4Scuwm7Y8a2T8X0XMPTrWqZMX16HM1R71Gf7kkv57Dw90pGQsLU/4p51OiNuf0zXOK77r4+5Nfk+WcYgFtBqrJ96nMdoM/262pVNXpYkW2i5OdzpmI3faCVPImwCXmTvveH7WdOPiUbbKiD/yHijEgObj/RAgIgko3HMc+3S2VfehecmJaEWaXGmNFAUBsksCQXedta8xz/JJxgnNw+mWg2O7MGy33lP7padpGpYyudOHoixwY9PyFGKZQSsDgbUlS8TAPRpzFj/JbT3H2HXWd9mJ3G5rURxlksWbStOMXvRpLcsEAcwTnn2LjyZHkrI9WoIfMbTmkjxlvNALyzyT9V9MeVs1n9QZ0bTLf5uMQK9GdzIJ8IeOr8cS883praXKl6o3kdXvk4p1auS0vACs+rO/nn3lVtEVhywgM93kFVhuiQf6yjWICAIl4G5FJ9x8DRYNC5gcyEiCTawSNdS6X9P/MJ2J7/jieOFk/YTBhegkGaR4Qoipc5U74l1OyIGmZGDE863VH+71gXoGuOjsLufyIKKfcK13kTyBI3kSbIonZNGdgntKlpubuLsmFhD5yN73CdMJx5ZPOvP+3QkAMbJ3SecJylzrOPyAOS3OnhTFGOc/SVjQV/iiDQ01DvZnKPZSuCtuFfApIxGZ9CSacMjacc1ZAP+2bxakGFxk50rVzCKFmKWX6uuuaY9j7KK1BcCc22sVI+XDjkAAYnuuLFjjBiAhdrsIvVPKAEYELPJmxrIW1BWPyzMXkUhbXG1dQyJc1Cys8GmpI3ZXPYfbC/lcnRvq5oNStEPKr77oQlYILRwB3kz5+ym5JFV7pBltsTD6CX7zXfoqz/4uS9SJKCbefnJK529dFgCzNg2BQWvXBzCQfMOaCK4Mnq3rvEXbYIpunahk3wUlFg3P0qLZKOkJELR9ajFjvrf5HaiVA7s1ipcUA9TqUm7QHBePd7fFohnYniVX3jjEtnV5B2m5h5sY/5T+d7//8E4jNuHgXaZKSxvq1nRE28wbHbxqA5gGL3+Q4KVf7IWXVS/7zXQOEWPherB6JVcioB+893VAPJUNEFQJZcVIx7V3ErbsmzlYPjprPJpbbTKFrldDD8fAOfX8q+s= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:25:00.7479 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91b485be-534b-4767-a577-08dd501fa589 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6325 To find the correct region and root port of an endpoint of a system needing address translation, the endpoint's HPA range must be translated to each of the parent port address ranges up to the root decoder. Use the calculated SPA range of an endpoint to find the endpoint's region. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 6d5ede5b4c43..ffe6038249ed 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3535,7 +3535,6 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, static int cxl_endpoint_decoder_add(struct cxl_endpoint_decoder *cxled) { - struct range *hpa = &cxled->cxld.hpa_range; struct cxl_root_decoder *cxlrd = cxled->cxlrd; struct cxl_region_params *p; struct cxl_region *cxlr; @@ -3547,7 +3546,7 @@ static int cxl_endpoint_decoder_add(struct cxl_endpoint_decoder *cxled) * one does the construction and the others add to that. */ mutex_lock(&cxlrd->range_lock); - cxlr = cxl_find_region_by_range(cxlrd, hpa); + cxlr = cxl_find_region_by_range(cxlrd, &cxled->spa_range); if (!cxlr) cxlr = construct_region(cxlrd, cxled); mutex_unlock(&cxlrd->range_lock); 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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 09/15] cxl/region: Use the endpoint's SPA range to create a region Date: Tue, 18 Feb 2025 14:23:50 +0100 Message-ID: <20250218132356.1809075-10-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6F:EE_|SJ2PR12MB8690:EE_ X-MS-Office365-Filtering-Correlation-Id: f63f9f71-7f63-4462-be3a-08dd501fa7c0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: Gz6qVFb5wiwJZBVRvwto2qHVuYFswcp+Iay0HTHKwosKX1AvDQpm6lPA6fiMOvwUpMGEGtErazCMCL28NPeSdGhyPQvfBqstGdpJoNF1wYFqmt6Y5jyIx/xrmKdDRoFzXiUHf2t+bPPlvYS4D2SZANxhivIXqvK4xZpJsQXl965+F4PEzGlt6L1L87oymCUmjhrfRMrYLfWwyW7b3gvyMIZCWJjW2C0a6kBp6i3AmTYzvRAaXoR/0iKhdwatoAg42sLrqqoSE3ymYPqXVjFyszrkpH0SK9RFWN0IvjxpTq6ugwzRXIvDxaqy7Tm/lzeScXAokPB5zv04otskEIqdTToAt3LC7DuAm8yKB25nwTKkc+HE/W0k235DcEp099pjVzRcOe9AZRCoTWu5FTP3VA4nhTqtiOPo0lMpCEJoXWCYMBk5OhJDkbXaL4+rCu6lUFOh6Svd6BWyqPwLG/v9aonGRoxAlGNoEyBISSRBzcPBWKnLVLV5o0K7PHBV/5R9cNKyCFKV0C40tU0/KTq1JNs4VbNXsjhwnk4tirXPSbfFdYP1wRhGdVsCRSjz7PrSPBghwOxM541rjkB5aykParqHeyw8rmGw7sEZxjLq+sqGwd31KWac4hlNwwMbF9PvIQxPXo0KuM/PXybDVjjYmKdJr+vGJTzApW01HrQR2I/MjeGrzibfzlnYimpv+kBUT9A/hDvW+J0VdwUhQy0Lo+y9Qw1lVEn1c5uwVzVb/G3fuwPzU2aD+NpeT5WYT4XkTg95pzVfqOjx06ldRCuVNEGIvXGeIb0xwj5Qi6vN1jaOiMrAMrlYr9Kn3iLqc0UCSrZej2qqrXS29vWIPWmZD2MoRTbLYMcbBii655Tr0HY6WECA7hvtmYmPiiqTfyb1UYmPNW6QXVxfPliCnsT836D112wg+UGIWgye4yu3B2ThMRnPdEzTrArhmizBRSg4/XkbCoOe3kqfiqn8ja02O80iaSOcr7wvGfl9rCAcNvkYhJ7ucS0n+/QoBhRNfEfxbevBfXHo4gz0vdarY9hsKUpUkPrKZwuvAX/rYPGRPLrADec0uw1zTyIG0rrE+1R0VD5n+kJyHigPrZRQGLgrblMCM5gxzgMeVvkOo9aF3EkbHTuLJV7hSGam7kiyZBtWUI+b2Jot2rYyIvr3ZRSWv9fnbtq6mJFZqJk6PZCF4YaZjYMIUoUsEm1uRQV9BPdE0uPThzKFtMBYJDpzre+H7+QgHXbSvNN1nxHm0s45EN9E1PTwqjUFhXkkvPdn50KvsnvakcGOWKcBrtgWQ/nrUq65hMFkVmj8UpCWU/7UkVQCkfZfOhATC4dQlZNE7cVFFAlE06qrTYQn4uZ2f9BRZ2bP43fFWh0GKoK7AvqVtVfiV5zDOkpM+JvTPkSZ0QcdUtJ8ROLRCcejcO0R4tbJcDUvqmHtrPkceY3ITix0jDVEqovQMQ+jt0hEFGJ4K7YxT1IKOGgiINm9KPMn03MBE+CLEVYhbRNWl7FvNu6dXFY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:25:04.4800 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f63f9f71-7f63-4462-be3a-08dd501fa7c0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8690 To create a region, SPA ranges must be used. With address translation the endpoint's HPA range is not the same as the SPA range. Use the previously calculated SPA range instead. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index ffe6038249ed..6e0434eee6df 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3445,14 +3445,14 @@ cxl_find_region_by_range(struct cxl_root_decoder *cxlrd, struct range *hpa) return to_cxl_region(region_dev); } -/* Establish an empty region covering the given HPA range */ +/* Establish an empty region covering the given SPA range */ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, struct cxl_endpoint_decoder *cxled) { struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); struct cxl_port *port = cxlrd_to_port(cxlrd); struct cxl_dev_state *cxlds = cxlmd->cxlds; - struct range *hpa = &cxled->cxld.hpa_range; + struct range *spa = &cxled->spa_range; int rc, part = READ_ONCE(cxled->part); struct cxl_region_params *p; struct cxl_region *cxlr; @@ -3493,7 +3493,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, goto err; } - *res = DEFINE_RES_MEM_NAMED(hpa->start, range_len(hpa), + *res = DEFINE_RES_MEM_NAMED(spa->start, range_len(spa), dev_name(&cxlr->dev)); rc = insert_resource(cxlrd->res, res); if (rc) { From patchwork Tue Feb 18 13:23:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13979827 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2045.outbound.protection.outlook.com [40.107.93.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07669269AE5; Tue, 18 Feb 2025 13:25:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.45 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739885113; 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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters to create a region Date: Tue, 18 Feb 2025 14:23:51 +0100 Message-ID: <20250218132356.1809075-11-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6D:EE_|SN7PR12MB6741:EE_ X-MS-Office365-Filtering-Correlation-Id: f78bab60-0709-4954-fa3f-08dd501faa0d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: 4EsrNdpZsEH3rJCf8A1PMwPMrWtokBN+V9T6c0y+7oge7CTN30Y0HdQuZw2pK2uEe3jqwfLVy99pbhYrjZLxnZarDchtUERi1NWHkUeiCRhsCbsBlel1rrD/oyLKmmVFXzeIIzvlEDD4TbAcjm+bIg7PgP1a+NDR7BdwKOT/bHU1ayXMpSRc1HpUIWVm8VDJm6YjZP2A7zQ9lHdrZZCSm41ndv+MDe07reqTeqUmCMIpAOHeLppQTIo6wXKlzYFEpHmiBxH7PKFKQTButCY3dh7bslAddBS/f7ihbOi49TMlp43MR2sJ3BR+ARcILppWL9IlxBEkBtsA8i09ki3yO8OcomYeaAfZdWDvoRsYHGzK8pPnCMSHz+2r7dhJle38ZsdeYEqdMWRZtwDcuq3so6HwPdXzQkEglkkWzE8B+5EHx2FlVkxnEGWH4tvwzTFzlktvwIq2p6L6pE7Fp9qpNUHfAguaZRN/nbVVeOHrlNm8Vb0twJ+gbsTNc5k50Fjzbm1t7/zF2+fd8DWr/yPYgHmXJuZZTpPF+i702fkFzR5sga6zXDof9va74BWak4o/cfGFScWUio8xngkEZ4hnDBTWlU7Lu41mX4AVlqdMpqNvAhK4XvJIDSwwwLeZKDq5WpssIyIlLpZ1mRQsn3sdlDryOLInNePnz5ccfeyr84oDk+oWBqyu6MOlK9ZwOzs/rQMG/tixr1rYtKZCbIO1w+TNIwHyZ2f7j5ZB5ElcHg4uFcbA2Xa3JzEnHhtPVYdnsBch5Hwy90YCSrFF+1lSdwfmkLTSQGlKMBuwkoD1net3UZ5nWX1DWE98b/+c0oe6YPaKjxUbFHrUxwbOR7ln4mU4+58z0lDsgIPEcHBRaXoC582ajEXKojoaJqLkHDQCKvlHLfS9f/q0gygCE58vCeLqR4OsweHJOA0daJBqO0OBP8IGafJOmrj4bvuXeLAJBE8I45tyMJ2rIC/h5x5EDUPqT7AbHhnA30KLcjGAcA4Fy5Ltq7LV44Esg+v7eXoE/qHuaBhFbHcuV89AYR3Ews9hwVc+s76C6dllIi0QPkSVccFFwyWhX/H+Puottco9U0Vp/MTEMmrPPBwBm9ifkKWVTgN86VbiQNlP6WWqnc4sn4ItIlGpDreuG88IkKp3zdQHAsScpnmLAJy3aQX+zxlj1IixtZOlyNCdI78cwBNiK/LE/RZNlDj4a3c3nsfxPGjEu4GohGPZqagJXitszCU1quzD7Z2eGH3X/szV8tGWqloS7nlvTv27LriZYPI6jqasYlEigFEI6/Naxg+27vrxjrTT+jsnaKUcSgorHj2j6PepCWNlr6ireLvqRoeYBRNO0XDkmPdWbdAS07dyYjL2fOLJjHeyzTvaOwMfZ0LzJOx6FwZW3OmBF6Te05VepWjeOi7H5FvRPEcYcJ3gPM+OjjDtQnEeisNHpdWkFqUsXS9s2m5+TYdvuEzfgy/8HJl1QDcdDuUeorgLhBQllyos6oGXdKhAZS7O2w//apc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:25:08.3260 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f78bab60-0709-4954-fa3f-08dd501faa0d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6741 Endpoints requiring address translation might not be aware of the system's interleaving configuration. Instead, interleaving can be configured on an upper memory domain (from an endpoint view) and thus is not visible to the endpoint. For region creation this might cause an invalid interleaving config that does not match the CFMWS entries. Use the interleaving configuration of the root decoders to create a region which bases on CFMWS entries. This always matches the system's interleaving configuration and is independent of the underlying memory topology. Signed-off-by: Robert Richter --- drivers/cxl/core/region.c | 39 ++++++++++++++++++++++++++++++++++----- drivers/cxl/cxl.h | 2 ++ 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 6e0434eee6df..3afcc9ca06ae 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1749,6 +1749,15 @@ static int cxl_region_validate_position(struct cxl_region *cxlr, } } + if (p->interleave_ways != cxled->interleave_ways || + p->interleave_granularity != cxled->interleave_granularity ) { + dev_dbg(&cxlr->dev, "interleaving config mismatch with %s: ways: %d:%d granularity: %d:%d\n", + dev_name(&cxled->cxld.dev), p->interleave_ways, + cxled->interleave_ways, p->interleave_granularity, + cxled->interleave_granularity); + return -ENXIO; + } + return 0; } @@ -1852,7 +1861,7 @@ static int match_switch_decoder_by_range(struct device *dev, } static int find_pos_and_ways(struct cxl_port *port, struct range *range, - int *pos, int *ways) + int *pos, int *ways, int *granularity) { struct cxl_switch_decoder *cxlsd; struct cxl_port *parent; @@ -1873,6 +1882,7 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range, } cxlsd = to_cxl_switch_decoder(dev); *ways = cxlsd->cxld.interleave_ways; + *granularity = cxlsd->cxld.interleave_granularity; for (int i = 0; i < *ways; i++) { if (cxlsd->target[i] == port->parent_dport) { @@ -1896,6 +1906,8 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range, struct cxl_interleave_context { struct range *hpa_range; int pos; + int interleave_ways; + int interleave_granularity; }; /** @@ -1914,13 +1926,17 @@ struct cxl_interleave_context { * the topology from the endpoint to the root decoder and iteratively * applying the function for each port. * + * Calculation of interleaving ways: + * + * interleave_ways = interleave_ways * parent_ways; + * * Return: position >= 0 on success * -ENXIO on failure */ static int cxl_port_calc_interleave(struct cxl_port *port, struct cxl_interleave_context *ctx) { - int parent_ways = 0, parent_pos = 0; + int parent_ways = 0, parent_pos = 0, parent_granularity = 0; int rc; /* @@ -1955,12 +1971,23 @@ static int cxl_port_calc_interleave(struct cxl_port *port, if (is_cxl_root(port)) return 0; - rc = find_pos_and_ways(port, ctx->hpa_range, &parent_pos, &parent_ways); + rc = find_pos_and_ways(port, ctx->hpa_range, &parent_pos, &parent_ways, + &parent_granularity); if (rc) return rc; ctx->pos = ctx->pos * parent_ways + parent_pos; + if (ctx->interleave_ways) + ctx->interleave_ways *= parent_ways; + else + ctx->interleave_ways = parent_ways; + + if (ctx->interleave_granularity) + ctx->interleave_granularity *= ctx->interleave_ways; + else + ctx->interleave_granularity = parent_granularity; + return ctx->pos; } @@ -3407,6 +3434,8 @@ static int cxl_endpoint_decoder_initialize(struct cxl_endpoint_decoder *cxled) cxled->cxlrd = to_cxl_root_decoder(&cxld->dev); cxled->spa_range = hpa; cxled->pos = ctx.pos; + cxled->interleave_ways = ctx.interleave_ways; + cxled->interleave_granularity = ctx.interleave_granularity; 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Tue, 18 Feb 2025 07:25:09 -0600 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso CC: , , Gregory Price , "Fabio M. De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 11/15] cxl/region: Use the endpoint's SPA range to check a region Date: Tue, 18 Feb 2025 14:23:52 +0100 Message-ID: <20250218132356.1809075-12-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6F:EE_|DS0PR12MB6583:EE_ X-MS-Office365-Filtering-Correlation-Id: 52d0d0db-ee0b-445a-1240-08dd501fac45 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: NnRF1XAvhp9NSgEcBhawj/mX7xBHAJN/IwAbK6L1sOQOy4lwn8bXSzw/mAZTfDYiktTmptfxKd2BjOjqGmVX1e8tusdYxuUQTl2mC4ijXyB2KwKeAW6c0IfMQVhkBhG+3ERwX9cI1JZ86b5apyEYaquEJWSUsu5NoPSleglOTv+hKBt351qgz7LmuoKNIcloNcDaSvHIHS639jgG8I/aYeYu6gXMshyqCtddwXAIsJDXxWDNHWRzE7EvjStVyxqSErba4pmBXJWOoCRk/yRgsHXAR6yY8TK0qxysxvuCjEg2jbuMdfEOtPhhkEOu7tS2EOblaMCoA/sstge1Cw76PoVWoMxzdMJTGcML/VJWbMDUcZo7o+Bd9ltz5iuOhczFzn+APU9jMGJMIudtEwB7Pg3nY1KpLI43W+djdp1gmnz5w6sxLJtuwK67Ju9UJvfTOOhL6M2ZnQv7zNceWuXs1/5WOOkxe9iMfIg/MvtWPcP2gM3dpa7oedXJFJBq9oj/LTx8XnWH2hmrdAlvndYd1xOL1rEQWFLiJ0ANWa80Ksxqommu6FHPLGh6COTmUqtjGRiJvbzDnp0gjC2Y+jFG2AgswnUU8krzwI/ihQNViP2ehzKFTWX1YB+9mjtGcw4cEIN9m5Y5J8643I2SSHSIt+OHM6MBLXzJJigrGZsf+GGoUnw5gmalv7K70QXAe7Lp1Mm8REvEryAXB70+uX0V39MklqDxG4nQ1VRYZI8WXYdEQW6v/2hkZJ08Foy+gCu8CGCtX/y+RQyRzg56k8S8jLbLSNNFcNO7iZyNowrG+4lzmBisd14XtXaO0zaQk0fmgavewAWoL4Nlyg1sQedq4eUL3WNKtGNTBsc3mXlab4YOthaTPHPDMS1j04YHl/OFyJGxXrIcL9DA4tohuJLp1YwLoBk3lb8kbft2cw23y+O3sfJ4lu3VEgFCh3ISm9LFwQJeci8fH5mo4erksC34t9KGrnLLUhT5u4pShHcdPCK6wGfhgZUNMkuH1zU1ymzR3cOXCbxvB47FOCX/+wV0iVeEnmHnq3zJQ1/0mSCECfGLNxai79z0FFTVgfagY1zS+elEr+nxxFHk9gOA1R2DFEdED0QvH8A1AB7HT+Ns3naOFeGZ6MuYOj0t6wggKXKCsQqiDtiFSm6MLM8ZGVO8wJde0LtVMv3Zol93h5bwCcRuOiy8Yv21es30zkDSHy152kOj2vRd6CHeotdICKER/zdV8P2HKNgqYVx2no1wV+v2u6urdL1cF62rZkF0uZNgDJxGTIwQbtW8Crth1gNmZ9ri6jV3FWsoBdaeJBeIvzbtp/0WXFwg9EbxgPvFA42sdsEX7i1aXmoSdYgsXacWliN8Wg+Nix30IvAv4ylwS5O/Io9PnPv5A6nIAP+nyu7hwtseqZRZkZ+4OoknfQt/HcffcK90ayORfnDcHJwxyL+aiI6+ubyOua9YkxTTXdr1t1dIL4benrH664UxkbcgUZKpVAzS5Z1lSV17yOijwMs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:25:12.0582 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52d0d0db-ee0b-445a-1240-08dd501fac45 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6583 Endpoints or switches requiring address translation might not be aware of the system's interleaving configuration. Then, the configured endpoint's address range might not match the expected range. In contrast, the SPA range of an endpoint is calculated applying platform specific address translation. That range is correct and can be used to check a region range. Adjust the region range check and use the endpoint's SPA range to check it. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 3afcc9ca06ae..2ca24565757a 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1531,22 +1531,26 @@ static int cxl_port_setup_targets(struct cxl_port *port, if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) { if (cxld->interleave_ways != iw || cxld->interleave_granularity != ig || - cxld->hpa_range.start != p->res->start || - cxld->hpa_range.end != p->res->end || + cxled->spa_range.start != p->res->start || + cxled->spa_range.end != p->res->end || ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)) { dev_err(&cxlr->dev, "%s:%s %s expected iw: %d ig: %d %pr\n", dev_name(port->uport_dev), dev_name(&port->dev), __func__, iw, ig, p->res); dev_err(&cxlr->dev, - "%s:%s %s got iw: %d ig: %d state: %s %#llx:%#llx\n", + "%s:%s %s got iw: %d ig: %d state: %s %#llx-%#llx:%#llx-%#llx(%s):%#llx-%#llx(%s)\n", dev_name(port->uport_dev), dev_name(&port->dev), __func__, cxld->interleave_ways, cxld->interleave_granularity, (cxld->flags & CXL_DECODER_F_ENABLE) ? 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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 12/15] cxl/region: Lock decoders that need address translation Date: Tue, 18 Feb 2025 14:23:53 +0100 Message-ID: <20250218132356.1809075-13-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6C:EE_|DS5PPF922753E5F:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ab2aa52-e6fe-454b-d465-08dd501fae63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: XNsWv3mDl6c4hnH803oz6fNguMMwQfcwepBcNZvB7tr9h48vD0lTOEmzWK63any8bI9ur8CV8wTmamoQRLZthKiz/6/b5rfmo7/tQ7GEaC21z/1BMCIb37ciIBfx4EaVG5ji+gRk8uYMs/UoLTDNKRHqBJqWIDV3GtqF5BrtK6cZPSpOGXAAOnGq+kz6QOnhlMPbGNnKXHx+6gw35b1LkrLLaRtr1BB4GjIHSWwPbX17Wa5JTDKqqQty0zIW743GySPjCG+YqpOSZ+CiVPJQgrZ/yLeNoLOqgnhVUCPFTmoCxFZZzxSU2C2fc4TrYNf9ZFxkDW92dZTvyQMxznktqL05W53jsUGYS1474V8hJK1Bya1B1nnKZh2zZ8jiKYuBIodAYPgig2baqhgMX/gqbMbpUMx1cLW4l7ZPNGDr/++6Fpb18r0+hGwf0djg5ITAc0LDyBWsWt9cYqy4cp+BOBew4nHN4Q6J9K8LTjbQpcVfLpeEcV+8SgmV532+w8hWYI2r74PkHFkoPbKcLZDLNKSMFTq2Zo2fk3xqKHz1IYDQWlGW1xwM6xQf/u9Um42QntbljYM7LESV4LOtvZ/IGSJ4TR0FzUJQt9tNm5dXcBboumzWWzW2An/9L6fhAmLl6rav+x1Adj+fkqWn7y/9UW2BpRe5Dy/xkmBYzr9bwbU/ToYqLusamw1Jie/8WKdj4uyBYObB6o2pRFvb9s/jAbIPXv+K8Ywksg1Zj/ycivWOf3VGridhsLyispkppMEf95ZwNyS0ACqNQYncYADKSY7pY7IDdokYNRZDn4TDbBl5lX4RBdlw9Hoc6an7sJ20eSMxtIrrWHhJZAhUZbrXJwLpFAgx+UmdOV5P12EDV8Lch2vublE+Zuhrg0aey3v8pJkbtyx3ouW4BMhRL+EG0hpy+T3E4ZKxFbEJ+DrPsAcrN558U0cQd/vO4M5qec1Q+lNqUqYX5FuU5/QcJp0V2AaDmGOBsiTAEtKMVkDvF+b9kVb9H1s6L6P0Mm1owatQRoc+CP9ubL1ScrCHzMPUuebQSmEW/pCguDBpLPHVDYq0n8Nd1Ak6Nyoqm2fBJZnEw+TTronlKZPSx7kiizoHvmidWC0PsBe0iA10/B0D34gZDeYzxIwiFsrh4sB7rkftk1yp9iYvQWwkSr0vdXZTkIa+z1zwNSJb14YInv26L7co5VqHNhkFnTfd8zelBLlgYs6lMtA/pwQflOEpUs63eJ82qBWOY+sN1rB5mKK62VOpsCVu4PM97MeUItnZNanqS63ooN1e6sLWZ5/QG6one+FciT9G0k1LKkpzBT88aVTvgkc1vE93dkwFWTvhoNzPs066jp8U3Z6OwyF90q98POXFyFrk2i+NEHeuX0NofjrKTDgyY17yS/N62hn5CI6sxj5iG8nwsUwHsLbp8Bmxg0VT+S496i4YA8hF90chNlCS/aFdQA9UGHjHKN2eI+4Q36+KWBZFgf5n6kChCXrLxNBS2KskebuVAUe8qCCkj+o= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:25:15.5996 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ab2aa52-e6fe-454b-d465-08dd501fae63 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF922753E5F There is only support to translate from the endpoint to its parent port, but not in the opposite direction from the parent to the endpoint. Thus, the endpoint address range cannot be determined and setup manually. If the parent implements the ->to_hpa() callback and needs address translation, forbid reprogramming of the decoders and lock them. Signed-off-by: Robert Richter --- drivers/cxl/core/region.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 2ca24565757a..dab059ee26ef 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3410,6 +3410,17 @@ static int cxl_endpoint_decoder_initialize(struct cxl_endpoint_decoder *cxled) if (rc < 0) return rc; + /* + * There is only support to translate from the endpoint to its + * parent port, but not in the opposite direction from the + * parent to the endpoint. Thus, the endpoint address range + * cannot be determined and setup manually. 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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 13/15] cxl/x86: Prepare for architectural platform setup Date: Tue, 18 Feb 2025 14:23:54 +0100 Message-ID: <20250218132356.1809075-14-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F68:EE_|CH3PR12MB9432:EE_ X-MS-Office365-Filtering-Correlation-Id: a9632fd2-e973-402a-977c-08dd501fb112 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: 0RLuPwYnNzZw6Gob5nWZeWPgZe+oHbtMUBp3/QTDh3leGex2CGOoIBICUz29VGE84hDLo99zE2EtEOb4RFc6iitfLZusc8HhhOLUxF7ONAHR6kC4ma+yGOJ/VfSuiUEPV9xVu4LqFxAv1BgafmJk/Fhgp1U8/4VyQctaW21CqP3dgGZjtWrNN3KqvMZR03AjYGPLpA9iZ81f+VIwhGxsXL0lHhul/VhrlfNfnXFG36lxYNZZMxcDzU0xdxX8zFgjeNgMoWVKfkq35ax6NeUH9Y6MnpYRy7Cp5XBijqj5gaLgBWXiPO0ZTE2p+v0kG5BLYw7yzky+QuwLAn722iojckTJRuZ3mAxDETFEcCr1sca9l3jWcEFTblG6jj6u9i2Cz7EanieXt/qucIlyPW15i+JBRasjWoIUchal6ds9v0kVEsOHeBQGxrv5yATu1qAOFtkFT0wfxFeX2FZpiAN2R2ru+4P+pAW89UKg8jwRRWw83pwkLKq7sAo1vAdIzjK+/0WiZvh6baQ0Eqmp6ly7FqBN4Wm6piusgrkAkzgdFGmfWydy+JOmaomILubjq0H0YRb6deD2BMBWwK9reCa8dTvMpDbRtJppMUZ0NIGNBnRirRF1SD9JC1eNwNzh44O7Fcg/XHrWRzwGA1UncWFnAhv8IsLWucX0RbkC4dLZCck+D7axzOD4bxdm1NprnadG0VG7wyP9YtRAnoBROyoK/wUwkiWeHUFBH1od4MW0lqDwteHve1WHeAH0K+zKglJRsw6/jpIpLcMEiZg/O2ftDzPzvItjoYTTu1BvUDIu8JJgvTuOE0lbfrXXqbhhjwKQGjCjFmLc6xOI9EACkVL7kZx1Ss4eavTcwSyWj90TvKCh66S30AlEgZm6kj8wyiCBXJGrfLfVMg2/6kLcM/OKff/Y9HDAZj31g0kmwo87i1bn+calDOZHiDMHJ+mUkjqPU3ySBUX2pyEOP9vXUG7gKyy/YXcedIneBHydFmoA0zvHMzMcjCDf6YTbKqy49YPsFZjlx4e4MSB10p98vPTvtVyYNFtazG+cOnN5SgisOcDFgmWkB3B9eBb3VOtGn4GI1FmyYxbFrfCo/suDhQmY9ppLwYIkPikE7s8ph4gQfw7WS9A0pmBbhR12rdwrQwHtWpN9vBlgGyQhncWqT6q4dsjOpEauhzbwX+HqdgqDk3s4Z1yQwBpeLyXnaJsEfHk4jrURytGc5/Xjo3yCc9EmdmyCT8d6Mbjb4ZDRUyxw/dGZBl2GDli+2XkIpJa+E1FXtKO+2mTWHSkfYMhQd2aokDspWlOGZkzv6UnI3iG6VeS9Dqy1andcta0sHSRfWAYwfL9xyaHTFffltWhmeytc5k6xsGhR6QmcTBVFdw2t4gFiyEHXjmj1yfwmWaf1f6PI9s/W34KxhU4AJAGCFO7iwLg1BiE7FDc0h6poVf5nDwoaof+MehEnrZOhw9+qQ0HLYiu24Tc76O3n4JrA5pGIvlknkBiYyuGHHvo+BREIIO0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:25:20.1159 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9632fd2-e973-402a-977c-08dd501fb112 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F68.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9432 In preparation of an architectural, vendor and platform specific port setup, add a function arch_cxl_port_platform_setup() that can be used to handle and implement architecture and platform specific code. Signed-off-by: Robert Richter Reviewed-by: Gregory Price --- drivers/cxl/core/Makefile | 2 ++ drivers/cxl/core/core.h | 1 + drivers/cxl/core/port.c | 4 ++++ drivers/cxl/core/x86/common.c | 12 ++++++++++++ 4 files changed, 19 insertions(+) create mode 100644 drivers/cxl/core/x86/common.c diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 9259bcc6773c..db1d16d39037 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -16,3 +16,5 @@ cxl_core-y += pmu.o cxl_core-y += cdat.o cxl_core-$(CONFIG_TRACING) += trace.o cxl_core-$(CONFIG_CXL_REGION) += region.o + +cxl_core-$(CONFIG_X86) += x86/common.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index a20ea2b7d1a4..e2955f91fd98 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -118,5 +118,6 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, struct access_coordinate *c); int cxl_gpf_port_setup(struct device *dport_dev, struct cxl_port *port); +void arch_cxl_port_platform_setup(struct cxl_port *port); #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index d19930c009ce..e94671ea8455 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -841,6 +841,8 @@ static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport) &cxl_einj_inject_fops); } +void __weak arch_cxl_port_platform_setup(struct cxl_port *port) { } + static int cxl_port_add(struct cxl_port *port, resource_size_t component_reg_phys, struct cxl_dport *parent_dport) @@ -878,6 +880,8 @@ static int cxl_port_add(struct cxl_port *port, return rc; } + arch_cxl_port_platform_setup(port); + rc = device_add(dev); if (rc) return rc; diff --git a/drivers/cxl/core/x86/common.c b/drivers/cxl/core/x86/common.c new file mode 100644 index 000000000000..eeb9bdadb26d --- /dev/null +++ b/drivers/cxl/core/x86/common.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include + +#include "../core.h" + +void arch_cxl_port_platform_setup(struct cxl_port *port) +{ +} From patchwork Tue Feb 18 13:23:55 2025 Content-Type: text/plain; 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De Francesco" Subject: [PATCH v2 14/15] cxl/amd: Enable Zen5 address translation using ACPI PRMT Date: Tue, 18 Feb 2025 14:23:55 +0100 Message-ID: <20250218132356.1809075-15-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6A:EE_|SA0PR12MB4400:EE_ X-MS-Office365-Filtering-Correlation-Id: fb8d9539-87a3-4d0c-be09-08dd501fb441 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|7416014|1800799024|13003099007; X-Microsoft-Antispam-Message-Info: =?utf-8?q?Lea9E3YpUVmsRSxgsTjOTyP9WX+CsM2?= =?utf-8?q?e6HZWvODavTTM958Fb7twwbRlSOlKv4ZKqarznd7sWt7+IPo55F9u0dzBYdPDU80h?= =?utf-8?q?WS9cyQKIgOn6tWa8mKuzlND26e0cb+IUqe00WtqOCl4CmQMijzt+TIWwCNGAmBlEG?= =?utf-8?q?ygTv99c9OxMFj36/fbq8ofOr8P9DsUObuXxaaka8x9WtOGX7kN78qBUZCsMKaVSMy?= =?utf-8?q?/quisLgeoisX55t7YHf1ejPlZ/KBPv6Alv6X2vty9EC4kI5TgXE1lRy6oRjJscRXk?= =?utf-8?q?+4k2oUCFybvTt/bILyE/7C1CKDTlN5G/Lag59OuOaWJu3f4jV+w3juOBfNAoxfcVO?= =?utf-8?q?lyDCJe5u1cMm2Ogb6fEadn30kIN6IP83BUEzollkBUpcDfaO11jSCOGnv+BMThI2W?= =?utf-8?q?Moh9JxxEnYCbqoSxsGwyqqzBM+0FuW/rwtamk9qoE+7iI4PcLAmTh8W7LrKW7rE8I?= =?utf-8?q?qxmBSFI/w3OB5pHsgKr4fi8SuYhUOvdDIDJ+4nxadsiadXyezHoA2kDQFweh8fbSM?= =?utf-8?q?+SYV/wt7sG6nNEdhg+D37Ckm61VdfwYxNDc6WGrKvFJmQw0DN98LYA9t/uAusoIyK?= =?utf-8?q?sjw0g39hbOSgd/QKlGYoVFRCmJWiiMg+lG8zT36vYapOSwnpDDz0nzOBnQ3ZUNn/K?= =?utf-8?q?lJFIzsqybzho8jseLUmWrZ1Ij82B7d5PE9wKiK9xTFRgvbGNOGnqdA0SU9dWah8uC?= =?utf-8?q?VVQNkawAFzf9DeTy0TOhKSHZenZ/dv0ba+PpyjZbY6/8q7oIs/sOE+OOT02PGslXh?= =?utf-8?q?gq2awAOnBi1BsQbqGDbl96JhozCRkfU4OjYGXqJl2mu6bbtE3yZxdInVDaofy56r7?= =?utf-8?q?cP72oyLTXLqeexlLWR1MZyeJtdRjTGSzPcfYQuNuNaA+FA27rbO6HUTybdD5d/7JK?= =?utf-8?q?I9V4fGRGA6sQkJNDGjavG4SzzUIRxDMImuRNFC9M6cQHSVFXVrfOOi03Jv8DP0/mt?= =?utf-8?q?lEo/n29GQVih9S+Sv4F+2WAcJiFnd7mibjG9lVQhK7xJNoAOHzgIpfPeJjlDR/uVH?= =?utf-8?q?ZOMdXcd8JvLiBTOyzqRwQBc8i3DxIgM/lU/uBE5TRJeBoYOcsC36NOHoJ1SKPFxtW?= =?utf-8?q?FreBTPjqyOYjLLrRHJaznSa7yng2JmOF+eX/0B4Co4Jf7zLVZwMMGo1vw93TPx5PD?= =?utf-8?q?jpK2lMxbY9kf0gmwP39l9IOh8N005InOzDKWr2DyyWhRLbXY7wlZkiC8LTbMZAnRL?= =?utf-8?q?4idITIkzo9SU4h2UC/FcTB6Ct9jSHcbLRV9rOFWeDOxGNlM/nUsOZGQAOHX5kc3au?= =?utf-8?q?WhgW1RtBVmxaUKeQVNWomCUycu11WcZi3glCIGJvtttCfEGxAWGDOhUTCP2Zrtwvg?= =?utf-8?q?cWEjIzKYVJRFUSN5ahXG9pOI8ju47OH0pVYNJWTUsX9eZgDq8KPUYCjAmu42ur8Kt?= =?utf-8?q?oPypsrb54PsQmJCuUoChkR59M1J3I7IxcpXEzmGAT0h8rL29PL6cAY=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(7416014)(1800799024)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:25:25.4425 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb8d9539-87a3-4d0c-be09-08dd501fb441 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4400 Add AMD platform specific Zen5 support for address translation. Zen5 systems may be configured to use 'Normalized addresses'. Then, CXL endpoints use their own physical address space and are programmed passthrough (DPA == HPA), the number of interleaving ways for the endpoint is set to one. The Host Physical Addresses (HPAs) need to be translated from the endpoint to its CXL host bridge. The HPA of a CXL host bridge is equivalent to the System Physical Address (SPA). ACPI Platform Runtime Mechanism (PRM) is used to translate the CXL Device Physical Address (DPA) to its System Physical Address. This is documented in: AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh ACPI v6.5 Porting Guide, Publication # 58088 https://www.amd.com/en/search/documentation/hub.html To implement AMD Zen5 address translation the following steps are needed: Apply platform specific changes to each port where necessary using platform detection and the existing architectural framework. Add a function cxl_port_setup_amd() to implement AMD platform specific code. Use Kbuild and Kconfig options respectively to enable the code depending on architecture and platform options. Handle architecture specifics in arch_cxl_port_platform_setup() and create a new file core/x86/amd.c for this. Introduce a function cxl_zen5_init() to handle Zen5 specific enablement. Zen5 platforms are detected using the PCIe vendor and device ID of the corresponding CXL root port. There is a check for ACPI PRMT CXL address translation support. Apply cxl_zen5_to_hpa() as cxl_port->to_hpa() callback to Zen5 CXL host bridges to enable platform specific address translation. Use ACPI PRM DPA-to-SPA translation to determine an endpoint's interleaving configuration and base address during the early initialization process. This is used to determine an endpoint's SPA range and to check the address translation setup. The configuration can be determined calling the PRM for specific HPAs given. The resulting SPAs are used to calculate interleaving parameters of the host bridge and root port. The maximum granularity (chunk size) is 16k, minimum is 256. Use the following calculation for the given HPAs: ways = hpa_len(SZ_16K) / SZ_16K gran = (hpa_len(SZ_16K) - hpa_len(SZ_16K - SZ_256) - SZ_256) / (ways - 1) pos = (hpa_len(SZ_16K) - ways * SZ_16K) / gran Before the endpoint is attached to a region the translation is checked for reasonable values. Signed-off-by: Robert Richter --- drivers/cxl/Kconfig | 4 + drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 3 + drivers/cxl/core/region.c | 25 +++- drivers/cxl/core/x86/amd.c | 259 ++++++++++++++++++++++++++++++++++ drivers/cxl/core/x86/common.c | 2 + 6 files changed, 293 insertions(+), 1 deletion(-) create mode 100644 drivers/cxl/core/x86/amd.c diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 876469e23f7a..e576028dd983 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -146,4 +146,8 @@ config CXL_REGION_INVALIDATION_TEST If unsure, or if this kernel is meant for production environments, say N. +config CXL_AMD + def_bool y + depends on AMD_NB + endif diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index db1d16d39037..cfe41b8edfd3 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -18,3 +18,4 @@ cxl_core-$(CONFIG_TRACING) += trace.o cxl_core-$(CONFIG_CXL_REGION) += region.o cxl_core-$(CONFIG_X86) += x86/common.o +cxl_core-$(CONFIG_CXL_AMD) += x86/amd.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index e2955f91fd98..d5c94e8cea42 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -119,5 +119,8 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, int cxl_gpf_port_setup(struct device *dport_dev, struct cxl_port *port); void arch_cxl_port_platform_setup(struct cxl_port *port); +#if defined(CONFIG_X86) +void cxl_port_setup_amd(struct cxl_port *port); +#endif #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index dab059ee26ef..b6806e67c62a 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -837,10 +837,24 @@ static int cxl_port_calc_hpa(struct cxl_port *port, struct cxl_decoder *cxld, { struct range hpa = *hpa_range; u64 len = range_len(&hpa); + int bits; if (!port->to_hpa) return 0; + /* + * Check range and length alignment of 256 MB for the + * interleaved address range. With max. 16-way interleaving + * applied this is at least 16 KB. + */ + + if (!len || hpa_range->start & (SZ_16K - 1) || len & (SZ_16K - 1)) { + dev_warn(&port->dev, + "HPA range not aligned or multiple of 16 kB: %#llx-%#llx(%s)\n", + hpa_range->start, hpa_range->end, dev_name(&cxld->dev)); + return -ENXIO; + } + /* Translate HPA to the next upper domain. */ hpa.start = port->to_hpa(cxld, hpa.start); hpa.end = port->to_hpa(cxld, hpa.end); @@ -853,7 +867,16 @@ static int cxl_port_calc_hpa(struct cxl_port *port, struct cxl_decoder *cxld, return -ENXIO; } - if (range_len(&hpa) != len * cxld->interleave_ways) { + /* + * Apply min and max interleaving addresses to the range. + * Determine the interleave ways and expand the 16 KB range + * by the power-of-2 part it. + */ + bits = range_len(&hpa) > len ? __ffs(range_len(&hpa) / len) : 0; + hpa.start &= ~((SZ_16K << bits) - 1); + hpa.end |= (SZ_16K << bits) - 1; + + if (range_len(&hpa) % len) { dev_warn(&port->dev, "CXL address translation: HPA range not contiguous: %#llx-%#llx:%#llx-%#llx(%s)\n", hpa.start, hpa.end, hpa_range->start, diff --git a/drivers/cxl/core/x86/amd.c b/drivers/cxl/core/x86/amd.c new file mode 100644 index 000000000000..483c92c18054 --- /dev/null +++ b/drivers/cxl/core/x86/amd.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include + +#include +#include "../core.h" + +#define PCI_DEVICE_ID_AMD_ZEN5_ROOT 0x153e + +static const struct pci_device_id zen5_root_port_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ZEN5_ROOT) }, + {}, +}; + +static int is_zen5_root_port(struct device *dev, void *unused) +{ + if (!dev_is_pci(dev)) + return 0; + + return !!pci_match_id(zen5_root_port_ids, to_pci_dev(dev)); +} + +static bool is_zen5(struct cxl_port *port) +{ + if (!IS_ENABLED(CONFIG_ACPI_PRMT)) + return false; + + /* To get the CXL root port, find the CXL host bridge first. */ + if (is_cxl_root(port) || + !port->host_bridge || + !is_cxl_root(to_cxl_port(port->dev.parent))) + return false; + + return !!device_for_each_child(port->host_bridge, NULL, + is_zen5_root_port); +} + +/* + * PRM Address Translation - CXL DPA to System Physical Address + * + * Reference: + * + * AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh + * ACPI v6.5 Porting Guide, Publication # 58088 + */ + +static const guid_t prm_cxl_dpa_spa_guid = + GUID_INIT(0xee41b397, 0x25d4, 0x452c, 0xad, 0x54, 0x48, 0xc6, 0xe3, + 0x48, 0x0b, 0x94); + +struct prm_cxl_dpa_spa_data { + u64 dpa; + u8 reserved; + u8 devfn; + u8 bus; + u8 segment; + void *out; +} __packed; + +static u64 prm_cxl_dpa_spa(struct pci_dev *pci_dev, u64 dpa) +{ + struct prm_cxl_dpa_spa_data data; + u64 spa; + int rc; + + data = (struct prm_cxl_dpa_spa_data) { + .dpa = dpa, + .devfn = pci_dev->devfn, + .bus = pci_dev->bus->number, + .segment = pci_domain_nr(pci_dev->bus), + .out = &spa, + }; + + rc = acpi_call_prm_handler(prm_cxl_dpa_spa_guid, &data); + if (rc) { + pci_dbg(pci_dev, "failed to get SPA for %#llx: %d\n", dpa, rc); + return ULLONG_MAX; + } + + pci_dbg(pci_dev, "PRM address translation: DPA -> SPA: %#llx -> %#llx\n", dpa, spa); + + return spa; +} + +/* Bits used for interleaving. */ +#define SPA_INTERLEAVING_BITS GENMASK_ULL(14, 8) + +static u64 cxl_zen5_to_hpa(struct cxl_decoder *cxld, u64 hpa) +{ + struct cxl_memdev *cxlmd; + struct pci_dev *pci_dev; + struct cxl_port *port; + u64 base, spa, spa2, len, len2, offset, granularity, gran_mask; + int ways, pos, ways_bits, gran_bits; + + /* + * Nothing to do if base is non-zero and Normalized Addressing + * is disabled. + */ + if (cxld->hpa_range.start) + return hpa; + + /* Only translate from endpoint to its parent port. */ + if (!is_endpoint_decoder(&cxld->dev)) + return hpa; + + /* + * Endpoints are programmed passthrough in Normalized + * Addressing mode. + */ + if (cxld->interleave_ways != 1) { + dev_dbg(&cxld->dev, "unexpected interleaving config: ways: %d granularity: %d\n", + cxld->interleave_ways, cxld->interleave_granularity); + return ULLONG_MAX; + } + + if (hpa > cxld->hpa_range.end) { + dev_dbg(&cxld->dev, "hpa addr %#llx out of range %#llx-%#llx\n", + hpa, cxld->hpa_range.start, cxld->hpa_range.end); + return ULLONG_MAX; + } + + port = to_cxl_port(cxld->dev.parent); + cxlmd = port ? to_cxl_memdev(port->uport_dev) : NULL; + if (!port || !dev_is_pci(cxlmd->dev.parent)) { + dev_dbg(&cxld->dev, "No endpoint found: %s, range %#llx-%#llx\n", + dev_name(cxld->dev.parent), cxld->hpa_range.start, + cxld->hpa_range.end); + return ULLONG_MAX; + } + pci_dev = to_pci_dev(cxlmd->dev.parent); + + /* + * If the decoder is already attached we are past the decoder + * initialization, do not determine the address mapping and + * just return here. + */ + if (cxld->region) + return prm_cxl_dpa_spa(pci_dev, hpa); + + /* + * Determine the interleaving config. Maximum granularity + * (chunk size) is 16k, minimum is 256. Calculated with: + * + * ways = hpa_len(SZ_16K) / SZ_16K + * gran = (hpa_len(SZ_16K) - hpa_len(SZ_16K - SZ_256) - SZ_256) + * / (ways - 1) + * pos = (hpa_len(SZ_16K) - ways * SZ_16K) / gran + */ + + base = prm_cxl_dpa_spa(pci_dev, 0); + spa = prm_cxl_dpa_spa(pci_dev, SZ_16K); + spa2 = prm_cxl_dpa_spa(pci_dev, SZ_16K - SZ_256); + + /* Includes checks to avoid div by zero */ + if (!base || base == ULLONG_MAX || spa == ULLONG_MAX || + spa2 == ULLONG_MAX || spa < base + SZ_16K || spa2 <= base || + (spa > base + SZ_16K && spa - spa2 < SZ_256 * 2)) { + dev_dbg(&cxld->dev, "Error translating HPA: base: %#llx spa: %#llx spa2: %#llx\n", + base, spa, spa2); + return ULLONG_MAX; + } + + len = spa - base; + len2 = spa2 - base; + + /* offset = pos * granularity */ + if (len == SZ_16K && len2 == SZ_16K - SZ_256) { + ways = 1; + offset = 0; + granularity = SZ_256; + pos = 0; + ways_bits = 0; + gran_bits = 8; + } else { + ways = len / SZ_16K; + offset = spa & (SZ_16K - 1); + granularity = (len - len2 - SZ_256) / (ways - 1); + ways_bits = __ffs(ways); + gran_bits = __ffs(granularity); + pos = offset >> gran_bits; + } + + /* + * Check the mapping: Number of ways is power of 2 or a + * multiple of 3 ways (len == ways * SZ_16K), granularitys is + * power of 2. + */ + if (len & ~(3ULL << (ways_bits + 14)) || + granularity != 1 << gran_bits || offset != pos << gran_bits) { + dev_dbg(&cxld->dev, "Error determining address mapping: base: %#llx spa: %#llx spa2: %#llx ways: %d pos: %d granularity: %llu\n", + base, spa, spa2, ways, pos, granularity); + return ULLONG_MAX; + } + + spa = prm_cxl_dpa_spa(pci_dev, hpa); + + /* + * Check SPA using a PRM call for the closest DPA calculated + * for the HPA. If the HPA matches a different interleaving + * position other than the decoder's, determine its offset to + * adjust the SPA. + */ + + gran_mask = GENMASK_ULL(gran_bits, 0); + spa2 = base + (hpa & ~gran_mask) * ways + (hpa & gran_mask); + base = base - pos * granularity; + + dev_dbg(&cxld->dev, + "address mapping found for %s (hpa -> spa): %#llx -> %#llx (%#llx+%#llx) ways: %d pos: %d granularity: %llu\n", + pci_name(pci_dev), hpa, spa, base, spa - base, ways, pos, + granularity); + + + if ((spa ^ spa2) & ~SPA_INTERLEAVING_BITS) { + dev_dbg(&cxld->dev, "SPA calculation failed: %#llx:%#llx\n", + spa, spa2); + return ULLONG_MAX; + } + + return spa; +} + +static void cxl_zen5_init(struct cxl_port *port) +{ + u64 spa; + struct prm_cxl_dpa_spa_data data = { .out = &spa, }; + int rc; + + if (!is_zen5(port)) + return; + + /* Check kernel and firmware support */ + rc = acpi_call_prm_handler(prm_cxl_dpa_spa_guid, &data); + + if (rc == -EOPNOTSUPP) { + pr_warn_once("ACPI PRMT: PRM address translation not supported by kernel\n"); + return; + } + + if (rc == -ENODEV) { + pr_warn_once("ACPI PRMT: PRM address translation not supported by firmware\n"); + return; + } + + port->to_hpa = cxl_zen5_to_hpa; + + dev_dbg(port->host_bridge, "PRM address translation enabled for %s.\n", + dev_name(&port->dev)); +} + +void cxl_port_setup_amd(struct cxl_port *port) +{ + cxl_zen5_init(port); +} diff --git a/drivers/cxl/core/x86/common.c b/drivers/cxl/core/x86/common.c index eeb9bdadb26d..7ccd68b035e6 100644 --- a/drivers/cxl/core/x86/common.c +++ b/drivers/cxl/core/x86/common.c @@ -9,4 +9,6 @@ void arch_cxl_port_platform_setup(struct cxl_port *port) { + if (IS_ENABLED(CONFIG_CXL_AMD)) + cxl_port_setup_amd(port); } From patchwork Tue Feb 18 13:23:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13979831 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2069.outbound.protection.outlook.com [40.107.93.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D0F1269806; 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Tue, 18 Feb 2025 07:25:26 -0600 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso CC: , , Gregory Price , "Fabio M. De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v2 15/15] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Date: Tue, 18 Feb 2025 14:23:56 +0100 Message-ID: <20250218132356.1809075-16-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com> References: <20250218132356.1809075-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6A:EE_|CH3PR12MB8283:EE_ X-MS-Office365-Filtering-Correlation-Id: b720c0bf-fe3e-4ecb-56a5-08dd501fb661 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: h2vpT3+ejypB583dVb/LngeKNtiTQitrWAE/XDdDio1eRGIgKFVsuHdS6Av/cO69ZB1Lth3VMC09/31ysgYShyESetdWU+TcLYB/0slGbvaUOVeGy33t+VgYTwgcbkz2IwW0dR8edsaJCr05WeJyoSM3ON+k/wkutX5QWPbmN16gZGUqQf26dP4E6pVRkY7aH0Y5K3HFu1/rHoYFt4iAeMntvgw4LERb7WCytHIr/9iSVtsAl+dhUTiKsSGxBqyW1P0LS1VXxRgHjwrxyNl82aXJh7Gt2LTdnhmL2sHSSudYsagXfEH20AYpmumxFseuTNlNHOnpUHgSY+JRMcut5tOmnjVYzBo6jCFgx4jvmhL43GjFyK5hzy8D8ULihiYmfRT+10EJjcPO8DmrlXTcz4XgrSR7rTMh5ioGIi1eqgcAeO0SSF2s8rB0DqnvlcdF7uU5VcqCX+Znt2DLQKnK3PEJGgUM2+kg7rkCYm07NpKNM82A3bBX0Z1iPZP08X8xbNr9Y52neCObgF9dVYRsQo2pjNbUy2abDi6i+BwtUKR5Tl3YLLcRqMd4nb4XYpUII1Jd03+U4ibUMZMzKa3N1qz7WK3pBVzla/auEkxORALbEdTLnTZUINMaM/XBZvEK/DEScw9x/gozr/MATB3YAtvcJIN0Xf0hE2X8gRjPX5scFn5bJ1gxo6tOK1/0U0CeYvdNR1FHENqRWMJoKt/zjVvYhd/dLMstIhEBKDxXNhgPOG1DKEcDAAco5kQ6zkGpJkN5WeZBKqxkRqLyoe/+1DVwvYG37bqjzpu7TsA9MvlZ9ycKCCzUmz6bJUUVDDWAbjRxehYZjbngjeImmjwiAKF+24/cTKbADDggFnl51MQivB4TbnbQPJDd/khd1ebbpzvWowBojidQJ+IqhObADSxdbwGLo0ExlifwClvZcL7FlxObGz7L0x6hInrj2B3OXrN59iJbnv2B7m4nUdShsyx9kgCF44EwGT9+UrRQCHX+pWKpUnA7TwnA+KV/4HewThc890aRO0Oxn/p4qYBjRWDQdmGuzGHXqlxR/FcfIAVgOHBYZ8ac/t550Cg7groIc2XjbXDG2JlaHocPsr2rfDQSLtQPeXLOdNtzigRv3e9rHFb0u76o/cxf8AkW6q1B3m1xTl3R3rziDo4pDZMOYZnkLlEbq6rKYzvwkajeIC0FEWPy+fMwVdSb1983cdohTFsb6HwMc8UzAVTSKXJ0soDx+PQojvOhaQujqfZI0NSbyO5GdaT28Dm9Hzvvvo0CODq9GAaA/NxABplQwiuEZuwsd5c6ljHlXZQRLVTbO9/hnSCU2ECPfOU1Y8flEHiLj7si98uCUNjErgqlv0gAaJcoJSQzIG+NE8GYU99qJzKDz2bNF0MXn2kc8Tx6wsOfuktSFTOKQBSVi2JgLO74dOX/DNK0A/M9L9+5bAN+4Hk8Dfq6u/iyHEWwF7JZFa16lcWg5z/tgpg6wXiV2ogBZYSRDdGyXkcZct7YUV/dtO0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 13:25:29.0050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b720c0bf-fe3e-4ecb-56a5-08dd501fb661 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8283 Adding a maintainer's entry for AMD platform specific CXL support. Cc: Terry Bowman Signed-off-by: Robert Richter --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 896a307fa065..12eca796fadf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5842,6 +5842,13 @@ F: include/cxl/ F: include/uapi/linux/cxl_mem.h F: tools/testing/cxl/ +COMPUTE EXPRESS LINK - AMD (CXL_AMD) +M: Robert Richter +M: Terry Bowman +L: linux-cxl@vger.kernel.org +S: Maintained +F: drivers/cxl/core/x86/amd.c + COMPUTE EXPRESS LINK PMU (CPMU) M: Jonathan Cameron L: linux-cxl@vger.kernel.org