From patchwork Tue Feb 18 14:36:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13980090 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEBE826AA94; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739889418; cv=none; b=Je2xI8yv9X6fW22w+myjeeg1gPbTt15Fx5nKDoq1Yq+reiUTzVAKvHZpJVcIkqd/eERA5vMQ0LJWgmJKBnYWnHpZJQbHeiLSdu7V32Dpb8VpFIypE7RtSNb56nzI/6kJeSGn9rPqDyIWyk63rQFZvRlz70DNliLtkDk64svBOpo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739889418; c=relaxed/simple; bh=o4GSDwcgCMz6AI4qFmm6hqFIO8SQo/fCcVqaBA7mmiA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hDxeQmHDnkZt6MHaYQpUnnxGAkreKkdBg7xmxTy5HpdwDJ9xNLP+qcu/mObu28aiyHUHTjeNBtB8DnYXTtH9qF8HlrdbWFjb2nQ9nBFU8+GQ+GiZCVPFqfTFxfQDGYv7QjWyvPHvs/bgieeQIlx/WBw99E36z6n9TqSEsjYtjeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TnaEI9PN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TnaEI9PN" Received: by smtp.kernel.org (Postfix) with ESMTPS id 42349C4CEE6; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739889418; bh=o4GSDwcgCMz6AI4qFmm6hqFIO8SQo/fCcVqaBA7mmiA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TnaEI9PNS6TDXzIPducf6m7rFu5FiYShedTbFhQZN5UbBqQqzjIqcU13fDgVoSafu imVxDSeAkxrcmzB4bGtEHn3hV9Cp4EnZBP66WaxvBwMM6TEi/dHOEeQHfRTQldeJaK IYLv+tPSpYSmXgZ6J7PMwniTFcsc2kHMF7hVysuzQFBrk5cjLm0z8x+UJ8d3P5s0vR ON7uOcZnSaPLdgt0l4pMT+z36dI2FtUpZlZm5f4B88SECkVHX2mAza/x6q5SOseKJR oyGYVUwsOGcKaH7E6sI2MxKGzQduY3KE6rtGEinVF+YOxR/8wVSf7rrHQExrXB0gDi +3eck03/JPvVw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BB4CC021AD; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 18 Feb 2025 20:06:40 +0530 Subject: [PATCH 1/4] perf/dwc_pcie: Move common DWC struct definitions to 'pcie-dwc.h' Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250218-pcie-qcom-ptm-v1-1-16d7e480d73e@linaro.org> References: <20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org> In-Reply-To: <20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org> To: Shuai Xue , Jing Zhang , Will Deacon , Mark Rutland , Jingoo Han , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring Cc: Shradha Todi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3403; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=6d2Yb8pZtN0A+yfWOqcZ9eUeZfdnTNPaYMX4prFPOcU=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBntJsHNIhzToT44AY+uhNUlCsCN6bOgu98Qogla 8fEUJTYaTeJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ7SbBwAKCRBVnxHm/pHO 9WZ0B/9Nin9btaLnESIchxC1r4blWqXKP9BhZLaYFCxr61YM/Ph8gTp0V8EHuv2b7Va1fr0QWky 5PGPDx8LXDlVdLyoPq0tz0t1jnv6USht1n+8SCWYLUAwUfMNU2iXopohMhcY3flFWFgGmOqatQq MC5k05B6r4WatPiN/s1AIbo8QlGoAp/nPJsgttnQrtWvKcuA84LYi01Hg0XZBt7fuTzr3hyY8nY 7Yys0rTVKtBQn6s6eCcPu7I7fBpcgpfuHAAjHfpsPry7KpQxAK8KweQ+1xrzA2Iu6GzKJ90T2Ib Mpp00V379HiuU/qgoo7PcgX/ik+4LfjwG993avYaYGYGEue5 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Since these are common to all Desginware PCIe IPs, move them to a new header, 'pcie-dwc.h' so that other drivers could make use of them. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 1 + drivers/perf/dwc_pcie_pmu.c | 23 ++--------------------- include/linux/pcie-dwc.h | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 37 insertions(+), 21 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 896a307fa065..b4d09d52a750 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18123,6 +18123,7 @@ S: Maintained F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml F: drivers/pci/controller/dwc/*designware* +F: include/linux/pcie-dwc.h PCI DRIVER FOR TI DRA7XX/J721E M: Vignesh Raghavendra diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c index cccecae9823f..05b37ea7cf16 100644 --- a/drivers/perf/dwc_pcie_pmu.c +++ b/drivers/perf/dwc_pcie_pmu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -99,26 +100,6 @@ struct dwc_pcie_dev_info { struct list_head dev_node; }; -struct dwc_pcie_pmu_vsec_id { - u16 vendor_id; - u16 vsec_id; - u8 vsec_rev; -}; - -/* - * VSEC IDs are allocated by the vendor, so a given ID may mean different - * things to different vendors. See PCIe r6.0, sec 7.9.5.2. - */ -static const struct dwc_pcie_pmu_vsec_id dwc_pcie_pmu_vsec_ids[] = { - { .vendor_id = PCI_VENDOR_ID_ALIBABA, - .vsec_id = 0x02, .vsec_rev = 0x4 }, - { .vendor_id = PCI_VENDOR_ID_AMPERE, - .vsec_id = 0x02, .vsec_rev = 0x4 }, - { .vendor_id = PCI_VENDOR_ID_QCOM, - .vsec_id = 0x02, .vsec_rev = 0x4 }, - {} /* terminator */ -}; - static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -529,7 +510,7 @@ static void dwc_pcie_unregister_pmu(void *data) static u16 dwc_pcie_des_cap(struct pci_dev *pdev) { - const struct dwc_pcie_pmu_vsec_id *vid; + const struct dwc_pcie_vsec_id *vid; u16 vsec; u32 val; diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h new file mode 100644 index 000000000000..261ae11d75a4 --- /dev/null +++ b/include/linux/pcie-dwc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021-2023 Alibaba Inc. + * + * Copyright 2025 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#ifndef LINUX_PCIE_DWC_H +#define LINUX_PCIE_DWC_H + +#include + +struct dwc_pcie_vsec_id { + u16 vendor_id; + u16 vsec_id; + u8 vsec_rev; +}; + +/* + * VSEC IDs are allocated by the vendor, so a given ID may mean different + * things to different vendors. See PCIe r6.0, sec 7.9.5.2. + */ +static const struct dwc_pcie_vsec_id dwc_pcie_pmu_vsec_ids[] = { + { .vendor_id = PCI_VENDOR_ID_ALIBABA, + .vsec_id = 0x02, .vsec_rev = 0x4 }, + { .vendor_id = PCI_VENDOR_ID_AMPERE, + .vsec_id = 0x02, .vsec_rev = 0x4 }, + { .vendor_id = PCI_VENDOR_ID_QCOM, + .vsec_id = 0x02, .vsec_rev = 0x4 }, + {} /* terminator */ +}; + +#endif /* LINUX_PCIE_DWC_H */ From patchwork Tue Feb 18 14:36:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13980089 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEC5326AA96; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739889418; cv=none; b=Zey7h+uNC8T3C5zEDjTZsO0qgGF7uEbCU4DrKG6WQg3Q0THhXSXB/YlwCVRoS2hXH6njOgWJ2Fvu/c5q1qtZ7C1kOrbGEDYYplD8uHLTUuHJsueD+g42avON4cvz0NKrPeQsnerTz051OUFQCyFEpATHFM9+DTBkGZ9Gdpfng+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739889418; c=relaxed/simple; bh=tFuYQ9hrj4YzCLAMjMj9Ggo3laAOabX9PZWDshZl04U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EFXnmVVa3MrpttjA1S5OKPtOcoVafV64hZBHCD3I9v51Oj5Tr8LJcq+YKSSu3n42+8d3h9aFFR7gPzHPoh+zY/y/PO9NQOI4Xjk2SN+YT+CO/vsuyLte+vtgKmVO0J4lKLEagEZXZ4/4CvS4ykkpZvO9rEGI/D3MwXR4W9Cm+y0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pszX8grx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pszX8grx" Received: by smtp.kernel.org (Postfix) with ESMTPS id 55A12C4CEE8; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739889418; bh=tFuYQ9hrj4YzCLAMjMj9Ggo3laAOabX9PZWDshZl04U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pszX8grxihp/7mTiGj9O8pz8rQ1k+07jvdS3INYrRoh3U7bORJ2SZveFgjEDgsj9V AfWNvBbizaM0LQEk573CsQmsAGfj+C0RnwlEmlIdXaPqP2wF/6Mp3DjZYgpf3svsnZ Suiw0HbXZnizmOjbzFXPkmoKFxXIrDTMcMhZv728dgt85VRxHWLPpBSTTdkjw0hwqL Gn5xKdSdhB/AvWVhLXHJOnHXfXdKSj53j5hEpVm7q7Okcgp+Ug2XLEdP/pisusgxJj v2p31cmm7uaPUtQ9QOKhShu72VB7/NaJemVat4qLlChbNXfPYRIId03b1IohDKQVWl WaGD/oCyZLZIg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40353C021AF; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 18 Feb 2025 20:06:41 +0530 Subject: [PATCH 2/4] PCI: dwc: Add helper to find the Vendor Specific Extended Capability (VSEC) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250218-pcie-qcom-ptm-v1-2-16d7e480d73e@linaro.org> References: <20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org> In-Reply-To: <20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org> To: Shuai Xue , Jing Zhang , Will Deacon , Mark Rutland , Jingoo Han , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring Cc: Shradha Todi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2145; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=M9WJthaTZXknfPb3HtwggK+nN0/yT7ulurjEGVuJfkQ=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBntJsHXKdWE8O15AQDIQdT7u8m2BaEWqY5eK3Yl IKQcIeh2riJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ7SbBwAKCRBVnxHm/pHO 9XHjCACSV0ixZHMt4QHkcF/ELFQt95Op2JM1tNpLmUbnyo2ApXOsLFfNkA7/nsPnqeWXQuziAsk SqQHgeFy27PnZoYMJBmsWnAeveButQMxWOEWuvVLBeGGEiBV1EH0gCzJMnmjifXjjir2UECSk3p /3nFFGK+gDqJdVFOtCPl3C1dlgdS+xYRQjni0GF/nE/iAtk4qdA4yqZTcjQoovF/P/mJTb+RxJV uto/1ekr1p0Zb3djsHB+RHTSPhF/K7rxOnEk6XxAzos83BHAbq9Q6++d2X1nw5msgEK5Pk+spJh qtsgWY/9PikvilTHIsvk4nSQo8wB6A+sK1i+1PK32qkFxHC+ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam dw_pcie_find_vsec_capability() is used by upcoming DWC APIs to find the VSEC capabilities like PTM, RAS etc... Co-developed-by: Shradha Todi Signed-off-by: Shradha Todi Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware.c | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 145e7f579072..a7c0671c6715 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -283,6 +284,45 @@ u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); +static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, + u16 vsec_id) +{ + u16 vsec = 0; + u32 header; + + if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) + return 0; + + while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec, + PCI_EXT_CAP_ID_VNDR))) { + header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); + if (PCI_VNDR_HEADER_ID(header) == vsec_id) + return vsec; + } + + return 0; +} + +static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, + const struct dwc_pcie_vsec_id *vsec_ids) +{ + const struct dwc_pcie_vsec_id *vid; + u16 vsec; + u32 header; + + for (vid = vsec_ids; vid->vendor_id; vid++) { + vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id, + vid->vsec_id); + if (vsec) { + header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); + if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev) + return vsec; + } + } + + return 0; +} + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { From patchwork Tue Feb 18 14:36:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13980086 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEA79269D0C; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WR1AOBvU" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6B148C4AF0C; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739889418; bh=XvXJ1MQzZf8WxpV47LK31HmkCLpKbYI67sP8fyugYhg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WR1AOBvU62L8mEO2I+7eZI9gdzc7wzHtWF8rZpJj/bBw7dEKac093v+Qyq7O+KAIO 4FndUZ4/MSroaLq9epWCYD3iS9akQkKxm2NJsLLy/ReXoddpAzHkuGgWbtwUI+fHsU O5iCiosREJ1ZUQSUzvtnty0WZr/cXSGe0AggSWRU1KRCK66TfMK1nR62CkWzddx39c aEDXYWJGmU2LXOZwYvT5ImGEzAb1enmC8LKohLzk0YS+obcjAwjGlK3KyT5D/5Eyfy c+kbvPGo16c0XszRieHCgfOW/vViRw8EmStZEAxlCSH9/9PqUyT0t0ABYccG9MKd1f AerMrl+GLQY+w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5688FC021AA; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 18 Feb 2025 20:06:42 +0530 Subject: [PATCH 3/4] PCI: dwc: Add sysfs support for PTM Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250218-pcie-qcom-ptm-v1-3-16d7e480d73e@linaro.org> References: <20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org> In-Reply-To: <20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org> To: Shuai Xue , Jing Zhang , Will Deacon , Mark Rutland , Jingoo Han , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring Cc: Shradha Todi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=18987; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=5we3kVgHWg7M829Zle66KXOdTLPGMfu81moqV1JyCok=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBntJsH1hJHIthERT3CmHc7DQfD24GuSgnn+YKwl QFloS1dmIuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ7SbBwAKCRBVnxHm/pHO 9bfTB/4z8ICBL4dTx6r5zP2lqPDngG11R9h1mGrYDdE0evxxnhKo/KR0YzvLC5tpz6KsJfyb39N Cky7bgtkL6PvLeHpv5eTdNOQ0qPfEM8xsySnDo+Uzt8S2SItrzaw036GDRfirPN7p+hE0KIwazw ddJsVeRebV7+kEynVOsI5o9csVAllEtg0S0PKkOW6dQXAhmxraD32/BEd2NuaVMmSn3ONa7ANFW 17lCNcUj4UjQTCQniDfCfeE4nAffXTA6VLJl3A1yaI6OZOpXNjWg8manT2M8wKbsGuRu9JbZ2PV xQxLeoHJzFywJ9sBrnhGhFN0NImcN9sWxtsSdr5UFDYu9Vpn X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Precision Time Management (PTM) mechanism defined in PCIe spec r6.0, sec 6.22 allows precise coordination of timing information across multiple components in a PCIe hierarchy with independent local time clocks. While the PTM support itself is indicated by the presence of PTM Extended Capability structure, Synopsys Designware IPs expose the PTM context (timing information) through Vendor Specific Extended Capability (VSEC) registers. Hence, add the sysfs support to expose the PTM context information to userspace from both PCIe RC and EP controllers. Below PTM context are exposed through sysfs: PCIe RC ======= 1. PTM Local clock 2. PTM T2 timestamp 3. PTM T3 timestamp 4. PTM Context valid PCIe EP ======= 1. PTM Local clock 2. PTM T1 timestamp 3. PTM T4 timestamp 4. PTM Master clock 5. PTM Context update Signed-off-by: Manivannan Sadhasivam --- Documentation/ABI/testing/sysfs-platform-dwc-pcie | 70 ++++++ MAINTAINERS | 1 + drivers/pci/controller/dwc/Makefile | 2 +- drivers/pci/controller/dwc/pcie-designware-ep.c | 3 + drivers/pci/controller/dwc/pcie-designware-host.c | 4 + drivers/pci/controller/dwc/pcie-designware-sysfs.c | 278 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.c | 6 + drivers/pci/controller/dwc/pcie-designware.h | 22 ++ include/linux/pcie-dwc.h | 8 + 9 files changed, 393 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-platform-dwc-pcie b/Documentation/ABI/testing/sysfs-platform-dwc-pcie new file mode 100644 index 000000000000..6b429108cd09 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-dwc-pcie @@ -0,0 +1,70 @@ +What: /sys/devices/platform/*/dwc/ptm/ptm_local_clock +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM local clock in nanoseconds. Applicable for both Root + Complex and Endpoint mode. + +What: /sys/devices/platform/*/dwc/ptm/ptm_master_clock +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM master clock in nanoseconds. Applicable only for + Endpoint mode. + +What: /sys/devices/platform/*/dwc/ptm/ptm_t1 +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM T1 timestamp in nanoseconds. Applicable only for + Endpoint mode. + +What: /sys/devices/platform/*/dwc/ptm/ptm_t2 +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM T2 timestamp in nanoseconds. Applicable only for + Root Complex mode. + +What: /sys/devices/platform/*/dwc/ptm/ptm_t3 +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM T3 timestamp in nanoseconds. Applicable only for + Root Complex mode. + +What: /sys/devices/platform/*/dwc/ptm/ptm_t4 +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RO) PTM T4 timestamp in nanoseconds. Applicable only for + Endpoint mode. + +What: /sys/devices/platform/*/dwc/ptm/ptm_context_update +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RW) Control the PTM context update mode. Applicable only for + Endpoint mode. + + Following values are supported: + + * auto = PTM context auto update trigger for every 10ms + + * manual = PTM context manual update. Writing 'manual' to this + file triggers PTM context update (default) + +What: /sys/devices/platform/*/dwc/ptm/ptm_context_valid +Date: February 2025 +Contact: Manivannan Sadhasivam +Description: + (RW) Control the PTM context validity (local clock timing). + Applicable only for Root Complex mode. PTM context is + invalidated by hardware if the Root Complex enters low power + mode or changes link frequency. + + Following values are supported: + + * 0 = PTM context invalid (default) + + * 1 = PTM context valid diff --git a/MAINTAINERS b/MAINTAINERS index b4d09d52a750..1c3e21cfbc6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18120,6 +18120,7 @@ M: Jingoo Han M: Manivannan Sadhasivam L: linux-pci@vger.kernel.org S: Maintained +F: Documentation/ABI/testing/sysfs-platform-dwc-pcie F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml F: drivers/pci/controller/dwc/*designware* diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index a8308d9ea986..3a962971249d 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_DW) += pcie-designware.o +obj-$(CONFIG_PCIE_DW) += pcie-designware.o pcie-designware-sysfs.o obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 8e07d432e74f..4bb7fd5d2fb0 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -666,6 +666,7 @@ void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + pcie_designware_sysfs_exit(pci); dw_pcie_edma_remove(pci); } EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup); @@ -837,6 +838,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) dw_pcie_ep_init_non_sticky_registers(pci); + pcie_designware_sysfs_init(pci, DW_PCIE_EP_TYPE); + return 0; err_remove_edma: diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index ffaded8f2df7..bd3195de923c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -548,6 +548,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->post_init) pp->ops->post_init(pp); + pcie_designware_sysfs_init(pci, DW_PCIE_RC_TYPE); + return 0; err_stop_link: @@ -572,6 +574,8 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + pcie_designware_sysfs_exit(pci); + pci_stop_root_bus(pp->bridge->bus); pci_remove_root_bus(pp->bridge->bus); diff --git a/drivers/pci/controller/dwc/pcie-designware-sysfs.c b/drivers/pci/controller/dwc/pcie-designware-sysfs.c new file mode 100644 index 000000000000..1ba41163cf58 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-designware-sysfs.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include + +#include "pcie-designware.h" + +static ssize_t ptm_context_update_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + u32 val; + + if (sysfs_streq(buf, "auto")) { + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + val |= PTM_REQ_AUTO_UPDATE_ENABLED; + dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); + } else if (sysfs_streq(buf, "manual")) { + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + val &= ~PTM_REQ_AUTO_UPDATE_ENABLED; + val |= PTM_REQ_START_UPDATE; + dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); + } else { + return -EINVAL; + } + + return count; +} + +static ssize_t ptm_context_update_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + u32 val; + + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + if (FIELD_GET(PTM_REQ_AUTO_UPDATE_ENABLED, val)) + return sysfs_emit(buf, "auto\n"); + + /* + * PTM_REQ_START_UPDATE is a self clearing register bit. So if + * PTM_REQ_AUTO_UPDATE_ENABLED is not set, then it implies that + * manual update is used. + */ + return sysfs_emit(buf, "manual\n"); +} + +static ssize_t ptm_context_valid_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + unsigned long arg; + u32 val; + + if (kstrtoul(buf, 0, &arg) < 0) + return -EINVAL; + + if (!!arg) { + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + val |= PTM_RES_CCONTEXT_VALID; + dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); + } else { + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + val &= ~PTM_RES_CCONTEXT_VALID; + dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); + } + + return count; +} + +static ssize_t ptm_context_valid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + u32 val; + + val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); + + return sysfs_emit(buf, "%u\n", !!FIELD_GET(PTM_RES_CCONTEXT_VALID, val)); +} + +static ssize_t ptm_local_clock_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_LOCAL_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_LOCAL_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_LOCAL_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t ptm_master_clock_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_MASTER_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_MASTER_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_MASTER_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t ptm_t1_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t ptm_t2_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t ptm_t3_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static ssize_t ptm_t4_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + u32 msb, lsb; + + do { + msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB); + lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_LSB); + } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB)); + + return sysfs_emit(buf, "%llu\n", ((u64) msb) << 32 | lsb); +} + +static DEVICE_ATTR_RW(ptm_context_update); +static DEVICE_ATTR_RW(ptm_context_valid); +static DEVICE_ATTR_RO(ptm_local_clock); +static DEVICE_ATTR_RO(ptm_master_clock); +static DEVICE_ATTR_RO(ptm_t1); +static DEVICE_ATTR_RO(ptm_t2); +static DEVICE_ATTR_RO(ptm_t3); +static DEVICE_ATTR_RO(ptm_t4); + +static struct attribute *ptm_attrs[] = { + &dev_attr_ptm_context_update.attr, + &dev_attr_ptm_context_valid.attr, + &dev_attr_ptm_local_clock.attr, + &dev_attr_ptm_master_clock.attr, + &dev_attr_ptm_t1.attr, + &dev_attr_ptm_t2.attr, + &dev_attr_ptm_t3.attr, + &dev_attr_ptm_t4.attr, + NULL +}; + +static umode_t ptm_attr_visible(struct kobject *kobj, struct attribute *attr, + int n) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct dw_pcie *pci = dev_get_drvdata(dev); + + /* RC only needs local, t2 and t3 clocks and context_valid */ + if ((attr == &dev_attr_ptm_t1.attr && pci->mode == DW_PCIE_RC_TYPE) || + (attr == &dev_attr_ptm_t4.attr && pci->mode == DW_PCIE_RC_TYPE) || + (attr == &dev_attr_ptm_master_clock.attr && pci->mode == DW_PCIE_RC_TYPE) || + (attr == &dev_attr_ptm_context_update.attr && pci->mode == DW_PCIE_RC_TYPE)) + return 0; + + /* EP only needs local, master, t1, and t4 clocks and context_update */ + if ((attr == &dev_attr_ptm_t2.attr && pci->mode == DW_PCIE_EP_TYPE) || + (attr == &dev_attr_ptm_t3.attr && pci->mode == DW_PCIE_EP_TYPE) || + (attr == &dev_attr_ptm_context_valid.attr && pci->mode == DW_PCIE_EP_TYPE)) + return 0; + + return attr->mode; +} + +static const struct attribute_group ptm_attr_group = { + .name = "ptm", + .attrs = ptm_attrs, + .is_visible = ptm_attr_visible, +}; + +static const struct attribute_group *dwc_pcie_attr_groups[] = { + &ptm_attr_group, + NULL, +}; + +static void pcie_designware_sysfs_release(struct device *dev) +{ + kfree(dev); +} + +void pcie_designware_sysfs_init(struct dw_pcie *pci, + enum dw_pcie_device_mode mode) +{ + struct device *dev; + int ret; + + /* Check for capabilities before creating sysfs attrbutes */ + ret = dw_pcie_find_ptm_capability(pci); + if (!ret) { + dev_dbg(pci->dev, "PTM capability not present\n"); + return; + } + + pci->ptm_vsec_offset = ret; + pci->mode = mode; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return; + + device_initialize(dev); + dev->groups = dwc_pcie_attr_groups; + dev->release = pcie_designware_sysfs_release; + dev->parent = pci->dev; + dev_set_drvdata(dev, pci); + + ret = dev_set_name(dev, "dwc"); + if (ret) + goto err_free; + + ret = device_add(dev); + if (ret) + goto err_free; + + pci->sysfs_dev = dev; + + return; + +err_free: + put_device(dev); +} + +void pcie_designware_sysfs_exit(struct dw_pcie *pci) +{ + if (pci->sysfs_dev) + device_unregister(pci->sysfs_dev); +} diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index a7c0671c6715..30825ec0648e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -323,6 +323,12 @@ static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, return 0; } +u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci) +{ + return dw_pcie_find_vsec_capability(pci, dwc_pcie_ptm_vsec_ids); +} +EXPORT_SYMBOL_GPL(dw_pcie_find_ptm_capability); + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 501d9ddfea16..7d3cbdce37c8 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -260,6 +260,21 @@ #define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc +/* PTM register definitions */ +#define PTM_RES_REQ_CTRL 0x8 +#define PTM_RES_CCONTEXT_VALID BIT(0) +#define PTM_REQ_AUTO_UPDATE_ENABLED BIT(0) +#define PTM_REQ_START_UPDATE BIT(1) + +#define PTM_LOCAL_LSB 0x10 +#define PTM_LOCAL_MSB 0x14 +#define PTM_T1_T2_LSB 0x18 +#define PTM_T1_T2_MSB 0x1c +#define PTM_T3_T4_LSB 0x28 +#define PTM_T3_T4_MSB 0x2c +#define PTM_MASTER_LSB 0x38 +#define PTM_MASTER_MSB 0x3c + /* * The default address offset between dbi_base and atu_base. Root controller * drivers are not required to initialize atu_base if the offset matches this @@ -439,6 +454,7 @@ struct dw_pcie_ops { struct dw_pcie { struct device *dev; + struct device *sysfs_dev; void __iomem *dbi_base; resource_size_t dbi_phys_addr; void __iomem *dbi_base2; @@ -464,6 +480,8 @@ struct dw_pcie { struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS]; struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; + u16 ptm_vsec_offset; + enum dw_pcie_device_mode mode; bool suspended; }; @@ -478,6 +496,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); +u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); @@ -499,6 +518,9 @@ void dw_pcie_setup(struct dw_pcie *pci); void dw_pcie_iatu_detect(struct dw_pcie *pci); int dw_pcie_edma_detect(struct dw_pcie *pci); void dw_pcie_edma_remove(struct dw_pcie *pci); +void pcie_designware_sysfs_init(struct dw_pcie *pci, + enum dw_pcie_device_mode mode); +void pcie_designware_sysfs_exit(struct dw_pcie *pci); static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) { diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h index 261ae11d75a4..13835896290a 100644 --- a/include/linux/pcie-dwc.h +++ b/include/linux/pcie-dwc.h @@ -31,4 +31,12 @@ static const struct dwc_pcie_vsec_id dwc_pcie_pmu_vsec_ids[] = { {} /* terminator */ }; +static const struct dwc_pcie_vsec_id dwc_pcie_ptm_vsec_ids[] = { + { .vendor_id = PCI_VENDOR_ID_QCOM, /* EP */ + .vsec_id = 0x03, .vsec_rev = 0x1 }, + { .vendor_id = PCI_VENDOR_ID_QCOM, /* RC */ + .vsec_id = 0x04, .vsec_rev = 0x1 }, + { } +}; + #endif /* LINUX_PCIE_DWC_H */ From patchwork Tue Feb 18 14:36:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13980088 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEB0826AA8D; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mi1FAJjd" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7882BC4CEEC; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739889418; bh=96dzHbNUlonjbIF4OjJogOraBYUUAqyVClMsMXe91/E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mi1FAJjdE5tCGT+xgGO+2PtN+j4OMI4wQjoObwvkV+7oSqqLTI9nt/kXTO9ajuliB W2DfOFP4siqKsKWg4IeVTVFVbLPJ/WoifbO7m8VcwmYUPuTLsCOHm0YgMLEfdYt859 odnppm7yEz+HFsZJz+B5cQZQv6lZdMNw6r7GXqK8OprqJrfmWvLlJN+ancb+33hKZC rz+S67v0YrRRukViKCmg9n2FYz0r0i77dwaBsm19YU/tKDcrUxYLFdHAKcSBx6RhZa N/m7NjSYWHK5gYT6varQ3sF+UPFvLFbzTU9WY8jho2OJMqlHhIjFbzf0zGbBDfJe6A aZ4uQXgkWheNw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E8F5C02198; Tue, 18 Feb 2025 14:36:58 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 18 Feb 2025 20:06:43 +0530 Subject: [PATCH 4/4] PCI: qcom-ep: Mask PTM_UPDATING interrupt Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250218-pcie-qcom-ptm-v1-4-16d7e480d73e@linaro.org> References: <20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org> In-Reply-To: <20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org> To: Shuai Xue , Jing Zhang , Will Deacon , Mark Rutland , Jingoo Han , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring Cc: Shradha Todi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1708; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=X8FrHGG/Y5bqtzA78r7NFQEcJV50dm29EwABf+RgvWo=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBntJsHhjGbHY6Q7I/y/ze6vd3blhN1A0HrKeF+F yr/ctlRT0KJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZ7SbBwAKCRBVnxHm/pHO 9UzoCACPUS9F6y/oWa2xHAIMf40x74TmzYyirduM/fPhPjn597iCw0IwZxVLOEI3IRYlnVT1RDo mcd10VKMQ8VlNnJ6x6frBvsGlur7q3MQUIsXcV+THeCgIKy3OgtpFTtTK6bhZn37Zrd+x0PcNpV y1yl7ZfgaYktanFCAigjXnpuMsmP+tuxXilWIwARjnCON+sVJ9qVyGaa6yRoUR/YCWUbQmLTM2H PAbIM1OB/mBew1IK24SX65V+vKmT3MjdFlhSMmcrLDugije2FR0DUSTUqffXehJjYmMZ1OHV+eR MxuVOFB27w1mdmz7fWLLwKEMcOgDestH4kocGjtFMi3tE/8U X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam When PTM is enabled, PTM_UPDATING interrupt will be fired for each PTM context update, which will be once every 10ms in the case of auto context update. Since the interrupt is not strictly needed for making use of PTM, mask it to avoid the overhead of processing it. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index c08f64d7a825..940edb7be1b9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -60,6 +60,7 @@ #define PARF_DEVICE_TYPE 0x1000 #define PARF_BDF_TO_SID_CFG 0x2c00 #define PARF_INT_ALL_5_MASK 0x2dcc +#define PARF_INT_ALL_3_MASK 0x2e18 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ #define PARF_INT_ALL_LINK_DOWN BIT(1) @@ -132,6 +133,9 @@ /* PARF_INT_ALL_5_MASK fields */ #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0) +/* PARF_INT_ALL_3_MASK fields */ +#define PARF_INT_ALL_3_PTM_UPDATING BIT(4) + /* ELBI registers */ #define ELBI_SYS_STTS 0x08 #define ELBI_CS2_ENABLE 0xa4 @@ -497,6 +501,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK); } + val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_3_MASK); + val &= ~PARF_INT_ALL_3_PTM_UPDATING; + writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_3_MASK); + ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep); if (ret) { dev_err(dev, "Failed to complete initialization: %d\n", ret);