From patchwork Tue Feb 18 19:08:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980616 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A00112356CD; Tue, 18 Feb 2025 19:08:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905732; cv=none; b=e/xDt5p9KUZhAK57OkyTsKZvlNYFEhv9zpz20+QqTLN/uWBtoIdfixjUHJDZi6TEyHyb/qE/b62bQCuY7E6I2AR5srWvgF1aH7PAU9qcCRUMklWylgeN/MAhYHV1PoMcHmeyB5t5KbAit768EfbE5ZRGQjll17vhQba1HlToH94= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905732; c=relaxed/simple; bh=DMjuuDJSJxfHSpL4ibtc9T2fw/bT7ago7AntzlFc7a4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mOIJOu5hMZp6vGpUEUaQAlSjeEgGODtSzm6fFGGeD/TeBU2Kw7+1wy8OJWUNmP+acQE7cHZ/CCdGFmcBBA/ByAcgFzbQPUAFsDd8+VL7kDRUozT7riWcYKCuPXV4pR4N9iQIlS5VDZrtcnmT37tbO2du1edDP/SfJQWnwLQLxyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZH8wlFKF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZH8wlFKF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 382ECC4CEEE; Tue, 18 Feb 2025 19:08:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905732; bh=DMjuuDJSJxfHSpL4ibtc9T2fw/bT7ago7AntzlFc7a4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZH8wlFKFCRZY2HzMn/arg9iCsYq5y02ehcyFMgQZ6qNk7youVReyUIq1JCPgZR0BH yCP+u0a1bhCSUIJHpOwyuSEMa3AZBVgV63kAZiQxvGKWMttn/OSKaOzaHYd96jYY0G QXvMUOs5uzEV/cTiAB/7EkrpCLrysLNpefGjvhPIeZXwUMU6byPHoKUsGHA/cshDcS SbdUfNkhEyX2CBvZQoFOcM98Sp5R7F5HaPjL9RXWKlqV1jT9wchkQzo1YP20zjl3Sh MGn/wtWKkIQhm0iNLmErRxZnj6NwgMwQ7uIH09xolonqwSalPD2BbJHV8wCo9GCzJR GpQ+ivCLvVNpg== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan , Bagas Sanjaya Subject: [PATCH v8 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation Date: Tue, 18 Feb 2025 13:08:10 -0600 Message-ID: <20250218190822.1039982-2-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduce a new documentation file, `amd_hfi.rst`, which delves into the implementation details of the AMD Hardware Feedback Interface and its associated driver, `amd_hfi`. This documentation describes how the driver provides hint to the OS scheduling which depends on the capability of core performance and efficiency ranking data. This documentation describes * The design of the driver * How the driver provides hints to the OS scheduling * How the driver interfaces with the kernel for efficiency ranking data. Reviewed-by: Bagas Sanjaya Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- Documentation/arch/x86/amd-hfi.rst | 127 +++++++++++++++++++++++++++++ Documentation/arch/x86/index.rst | 1 + 2 files changed, 128 insertions(+) create mode 100644 Documentation/arch/x86/amd-hfi.rst diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/amd-hfi.rst new file mode 100644 index 0000000000000..5d204688470e3 --- /dev/null +++ b/Documentation/arch/x86/amd-hfi.rst @@ -0,0 +1,127 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================================================== +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform +====================================================================== + +:Copyright: 2024 Advanced Micro Devices, Inc. All Rights Reserved. + +:Author: Perry Yuan +:Author: Mario Limonciello + +Overview +-------- + +AMD Heterogeneous Core implementations are comprised of more than one +architectural class and CPUs are comprised of cores of various efficiency and +power capabilities: performance-oriented *classic cores* and power-efficient +*dense cores*. As such, power management strategies must be designed to +accommodate the complexities introduced by incorporating different core types. +Heterogeneous systems can also extend to more than two architectural classes as +well. The purpose of the scheduling feedback mechanism is to provide +information to the operating system scheduler in real time such that the +scheduler can direct threads to the optimal core. + +The goal of AMD's heterogeneous architecture is to attain power benefit by sending +background thread to the dense cores while sending high priority threads to the classic +cores. From a performance perspective, sending background threads to dense cores can free +up power headroom and allow the classic cores to optimally service demanding threads. +Furthermore, the area optimized nature of the dense cores allows for an increasing +number of physical cores. This improved core density will have positive multithreaded +performance impact. + +AMD Heterogeneous Core Driver +----------------------------- + +The ``amd_hfi`` driver delivers the operating system a performance and energy efficiency +capability data for each CPU in the system. The scheduler can use the ranking data +from the HFI driver to make task placement decisions. + +Thread Classification and Ranking Table Interaction +---------------------------------------------------- + +The thread classification is used to select into a ranking table that describes +an efficiency and performance ranking for each classification. + +Threads are classified during runtime into enumerated classes. The classes represent +thread performance/power characteristics that may benefit from special scheduling behaviors. +The below table depicts an example of thread classification and a preference where a given thread +should be scheduled based on its thread class. The real time thread classification is consumed +by the operating system and is used to inform the scheduler of where the thread should be placed. + +Thread Classification Example Table +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ++----------+----------------+-------------------------------+---------------------+---------+ +| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter | ++----------+----------------+-------------------------------+---------------------+---------+ +| 0 | Default | Performant | Highest | | ++----------+----------------+-------------------------------+---------------------+---------+ +| 1 | Non-scalable | Efficient | Lowest | PMCx1A1 | ++----------+----------------+-------------------------------+---------------------+---------+ +| 2 | I/O bound | Efficient | Lowest | PMCx044 | ++----------+----------------+-------------------------------+---------------------+---------+ + +Thread classification is performed by the hardware each time that the thread is switched out. +Threads that don't meet any hardware specified criteria will be classified as "default". + +AMD Hardware Feedback Interface +-------------------------------- + +The Hardware Feedback Interface provides to the operating system information +about the performance and energy efficiency of each CPU in the system. Each +capability is given as a unit-less quantity in the range [0-255]. A higher +performance value indicates higher performance capability, and a higher +efficiency value indicates more efficiency. Energy efficiency and performance +are reported in separate capabilities in the shared memory based ranking table. + +These capabilities may change at runtime as a result of changes in the +operating conditions of the system or the action of external factors. +Power Management FW is responsible for detecting events that would require +a reordering of the performance and efficiency ranking. Table updates would +happen relatively infrequently and occur on the time scale of seconds or more. + +The following events trigger a table update: + * Thermal Stress Events + * Silent Compute + * Extreme Low Battery Scenarios + +The kernel or a userspace policy daemon can use these capabilities to modify +task placement decisions. For instance, if either the performance or energy +capabilities of a given logical processor becomes zero, it is an indication that +the hardware recommends to the operating system to not schedule any tasks on +that processor for performance or energy efficiency reasons, respectively. + +Implementation details for Linux +-------------------------------- + +The implementation of threads scheduling consists of the following steps: + +1. A thread is spawned and scheduled to the ideal core using the default + heterogeneous scheduling policy. +2. The processor profiles thread execution and assigns an enumerated classification ID. + This classification is communicated to the OS via logical processor scope MSR. +3. During the thread context switch out the operating system consumes the workload(WL) + classification which resides in a logical processor scope MSR. +4. The OS triggers the hardware to clear its history by writing to an MSR, + after consuming the WL classification and before switching in the new thread. +5. If due to the classification, ranking table, and processor availability, + the thread is not on its ideal processor, the OS will then consider scheduling + the thread on its ideal processor (if available). + +Ranking Table +------------- +The ranking table is a shared memory region that is used to communicate the +performance and energy efficiency capabilities of each CPU in the system. + +The ranking table design includes rankings for each APIC ID in the system and +rankings both for performance and efficiency for each workload classification. + +.. kernel-doc:: drivers/platform/x86/amd/hfi/hfi.c + :doc: amd_shmem_info + +Ranking Table update +--------------------------- +The power management firmware issues an platform interrupt after updating the ranking +table and is ready for the operating system to consume it. CPUs receive such interrupt +and read new ranking table from shared memory which PCCT table has provided, then +``amd_hfi`` driver parse the new table to provide new consume data for scheduling decisions. diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/index.rst index 8ac64d7de4dc9..56f2923f52597 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -43,3 +43,4 @@ x86-specific Documentation features elf_auxvec xstate + amd-hfi From patchwork Tue Feb 18 19:08:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980617 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AABD726FDAE; Tue, 18 Feb 2025 19:08:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905734; cv=none; b=ooRQ2ojgmL+ksK/KraQf/2N+K8ZMvObn4/2yr6hz16tMG6U8/3I01FEw3w2g1sdA5dAvbKvjrEVsMbkRAbIVdryzydelq0Ryn9FGSiFjl7Ef06EHXcgTsPsZf6W4jrfiEuyJXkzLsUzfEQtTQWVSCjjNWON8kMaPdmj5DMnJPcM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905734; c=relaxed/simple; bh=9qaXcaBCFsKmd+V7XAdrwxOKh1ZrVcJwI/csElZRrAM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Uyn5oMMYei7JJMwghs9vtsVkuw7u6HArqjz2SScf3P8JNe1w2yKXedzVOpx8+DwyOEUXqV7caufg/ahgVZ5p8tZPoOgvX9421TCTu7eXpNwqBNxjXDC9Ec6jbj3lWnpvaCsEcLRvilD0RaS+YzIf1XnmZrgsNB10o9kMjREKFfk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=skXq7J+4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="skXq7J+4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55DF2C4CEE4; Tue, 18 Feb 2025 19:08:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905734; bh=9qaXcaBCFsKmd+V7XAdrwxOKh1ZrVcJwI/csElZRrAM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=skXq7J+4D5ECdBf+r2sCIi7s8l85kK9m5GWbJNb9130USnBCV8aohAIP6VDhFV0Yp JLo2R+bdCG9JKJU5DSitQp8p3LJH4M9v10oAF2rBs9OP25+fPRSJDMWspnCyaWhRi6 zGwpseTiOgcZ7WXDmZuhYG0lL+pEjv0gXHxj70NRtk/JknuWqA0TF24G2bkhvgHDvC HgoOUrasPQFn87xMuEmUI7fO24/L/nUKE96Xbpuv1loiT8eXFS+2G6nF9uI+VJHT/g mexnB+rADzNK5ehtK+LiYZaaKWxshc7lvcWwKn3CGURxLtMUhC0WaiWLM0WHt2VbhS QHyvumJY1pWvQ== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v8 02/13] MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Date: Tue, 18 Feb 2025 13:08:11 -0600 Message-ID: <20250218190822.1039982-3-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Introduce the `amd_hfi` driver into the MAINTAINERS file. The driver will support AMD Heterogeneous Core design which provides hardware feedback to the OS scheduler. Moving forward, Mario will be responsible for the maintenance and Perry will assist on review of patches related to this driver. Signed-off-by: Mario Limonciello --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index efee40ea589f7..2c85c16d82770 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1098,6 +1098,15 @@ F: arch/x86/include/asm/amd_hsmp.h F: arch/x86/include/uapi/asm/amd_hsmp.h F: drivers/platform/x86/amd/hsmp/ +AMD HETERO CORE HARDWARE FEEDBACK DRIVER +M: Mario Limonciello +R: Perry Yuan +L: platform-driver-x86@vger.kernel.org +S: Supported +B: https://gitlab.freedesktop.org/drm/amd/-/issues +F: Documentation/arch/x86/amd-hfi.rst +F: drivers/platform/x86/amd/hfi/ + AMD IOMMU (AMD-VI) M: Joerg Roedel R: Suravee Suthikulpanit From patchwork Tue Feb 18 19:08:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980618 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2646271294; Tue, 18 Feb 2025 19:08:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905736; cv=none; b=t2aunY5Q9UUFHwI14AVx6y6RsSHyujSvKhtjSEOZdV1JWzQdwS4E8oediUcEyqPsVwVjJjERZ6jegm9LcVdxiWCycFnG6MHozsoea6WieNfS80DP6zQO1V/LcSif7YljvlzJ1bwDFu7ndHflltDCYlI5AH6i5shWG3xfC7d+HGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905736; c=relaxed/simple; bh=rLFz3Ld5AzSqmno+C7ltDttN21W0DB+vJuD4uskXVzM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DrKLcXkqyL76ETP7sWC+2hGsN4eCccitBfjA3v8kZDMFZKyy7uIvDaec553eF7i0+dOHDdMehZZY8Ujt1qdDiB9xNBAScALowG735Bir6kJf4g4PZHNqGLbRkop8VnbUuA7BDVhPYUodxKgblRFQISx25gez7oLPJjF4D7VCiCk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Z1muFOCi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z1muFOCi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 63982C4CEE2; Tue, 18 Feb 2025 19:08:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905736; bh=rLFz3Ld5AzSqmno+C7ltDttN21W0DB+vJuD4uskXVzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z1muFOCiAfjE2G5d5vhAVWYaoK2Zcjx+oIKI3TeRx859dFRE06AHciLOjP8y8IE7q G2kaybqdgi87AABycGCMsLhy2sVa6hWtfIJHd/tWNsT97TG8PLl3WX/B3UVxnPHhoX XPAs3o0M3Q0FJZLOOiFWbtWn8rYAZXPlM2jAPMHmCfcYu9FQJNkhHDqO6dbf/6PBG0 svBuVZIpIIxVkeggvFLPLMZsOOQodiYMap9azVWADdmkbuV9EfwSaWig1c3FiIRBFv /Rh4wkWAkvjLDbiIGmrlVVGlXlp+Qoa1NLvx9yv7pgTpRbUhDSXr3nwhudWvBwbrxz rDg8SQhP9jSaQ== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v8 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Tue, 18 Feb 2025 13:08:12 -0600 Message-ID: <20250218190822.1039982-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 72765b2fe0d87..c84930610c7e6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -716,6 +716,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e From patchwork Tue Feb 18 19:08:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980619 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F41C3272926; Tue, 18 Feb 2025 19:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905739; cv=none; b=HZT5IlIvp5P5KjnOrEXIQUlJE86U2zwwRNJmPoPzuHq2QoU4dknc5PSJlPEk4/aBPjf9KmF9Ww5DxlatGxM5/Wd+FdccFfUVYdr5Qgh/f7XSGzQyOt+xhMP1hAK25RXyA8Pv9/06702oCgYB3lL7FqPRbCoDv6gZCU9RPhfEYp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905739; c=relaxed/simple; bh=uwwTkTGlwUrQLWFB8Pyu0IEyDwGC6eMfN5MTKok5eqM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Fjj1Di/20hje+zdP2LWhpwfAGWTtOILZpKJ3bg2lGsOHn1EjVhGkjP6X34uEpA6Xt8mWy4WYJS8ZiIJV57vYbL/445gq6Zv9XTm3wq0Ksh+OXDg/bNaQ1ihONQbZ7c8TRdYJlsPtF/excIeZXCR072ebUSZg823AETu3mKU604Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BF2QN15l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BF2QN15l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 837ABC4CEEE; Tue, 18 Feb 2025 19:08:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905738; bh=uwwTkTGlwUrQLWFB8Pyu0IEyDwGC6eMfN5MTKok5eqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BF2QN15lofAQwOE2YhxCEQXO1stwlle8Lzn9p5g2/USeH4atSqpsiIJuiwkmO2g3/ cFzVcjPAnug1bKkimmoB5obfwhSbrWrv+SKDUssrCRPCqeS3tqCCc5FYVrt+l7OOQR GOB3Cg5xADlgjQU0Qfb2ClMc3YIlxDKjnn0y6KE3DX3l6U2xDcUp+S53nL5LhiVrJ3 0WlcukFoBROwQ2qyLL5I97mbXKnIGZJmBjHZFpIKufH4fNnKXRnupj4NUBWzbi9IOt Y9r7xDTV60xmY7ZrcQy4ce/sVMWlPwmPGZfO6Jvns7UvFYoTGio98pm717rZBhg8sl Xo31PrYkAFLQg== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan , Shyam Sundar S K Subject: [PATCH v8 04/13] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver Date: Tue, 18 Feb 2025 13:08:13 -0600 Message-ID: <20250218190822.1039982-5-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan The AMD Heterogeneous core design and Hardware Feedback Interface (HFI) provide behavioral classification and a dynamically updated ranking table for the scheduler to use when choosing cores for tasks. There are two CPU core types defined: `Classic Core` and `Dense Core`. "Classic" cores are the standard performance cores, while "Dense" cores are optimized for area and efficiency. Heterogeneous compute refers to CPU implementations that are comprised of more than one architectural class, each with two capabilities. This means each CPU reports two separate capabilities: "perf" and "eff". Each capability lists all core ranking numbers between 0 and 255, where a higher number represents a higher capability. Heterogeneous systems can also extend to more than two architectural classes. The purpose of the scheduling feedback mechanism is to provide information to the operating system scheduler in real time, allowing the scheduler to direct threads to the optimal core during task scheduling. All core ranking data are provided by the PMFW via a shared memory ranking table, which the driver reads and uses to update core capabilities to the scheduler. When the hardware updates the table, it generates a platform interrupt to notify the OS to read the new ranking table. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Reviewed-by: Gautham R. Shenoy Reviewed-by: Shyam Sundar S K Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v8: * s,devm_kzalloc,devm_kcalloc, * fold newlines from patch 5 into this patch * Drop ->cpu member, push to later patch * s,for_each_present_cpu,for_each_possible_cpu, v7: * Adjust Kconfig to 80 characters --- drivers/platform/x86/amd/Kconfig | 1 + drivers/platform/x86/amd/Makefile | 1 + drivers/platform/x86/amd/hfi/Kconfig | 20 ++++ drivers/platform/x86/amd/hfi/Makefile | 7 ++ drivers/platform/x86/amd/hfi/hfi.c | 162 ++++++++++++++++++++++++++ 5 files changed, 191 insertions(+) create mode 100644 drivers/platform/x86/amd/hfi/Kconfig create mode 100644 drivers/platform/x86/amd/hfi/Makefile create mode 100644 drivers/platform/x86/amd/hfi/hfi.c diff --git a/drivers/platform/x86/amd/Kconfig b/drivers/platform/x86/amd/Kconfig index c3e086ea64fc6..589d61ebf726b 100644 --- a/drivers/platform/x86/amd/Kconfig +++ b/drivers/platform/x86/amd/Kconfig @@ -6,6 +6,7 @@ source "drivers/platform/x86/amd/hsmp/Kconfig" source "drivers/platform/x86/amd/pmf/Kconfig" source "drivers/platform/x86/amd/pmc/Kconfig" +source "drivers/platform/x86/amd/hfi/Kconfig" config AMD_3D_VCACHE tristate "AMD 3D V-Cache Performance Optimizer Driver" diff --git a/drivers/platform/x86/amd/Makefile b/drivers/platform/x86/amd/Makefile index 56f62fc9c97b4..c50e93c3334cf 100644 --- a/drivers/platform/x86/amd/Makefile +++ b/drivers/platform/x86/amd/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_AMD_PMC) += pmc/ obj-$(CONFIG_AMD_HSMP) += hsmp/ obj-$(CONFIG_AMD_PMF) += pmf/ obj-$(CONFIG_AMD_WBRF) += wbrf.o +obj-$(CONFIG_AMD_HFI) += hfi/ diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig new file mode 100644 index 0000000000000..532939eb08a6a --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# AMD Hardware Feedback Interface Driver +# + +config AMD_HFI + bool "AMD Hetero Core Hardware Feedback Driver" + depends on ACPI + depends on CPU_SUP_AMD + help + Select this option to enable the AMD Heterogeneous Core Hardware + Feedback Interface. If selected, hardware provides runtime thread + classification guidance to the operating system on the performance and + energy efficiency capabilities of each heterogeneous CPU core. These + capabilities may vary due to the inherent differences in the core types + and can also change as a result of variations in the operating + conditions of the system such as power and thermal limits. If selected, + the kernel relays updates in heterogeneous CPUs' capabilities to + userspace, allowing for more optimal task scheduling and resource + allocation, leveraging the diverse set of cores available. diff --git a/drivers/platform/x86/amd/hfi/Makefile b/drivers/platform/x86/amd/hfi/Makefile new file mode 100644 index 0000000000000..672c6ac106e95 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# AMD Hardware Feedback Interface Driver +# + +obj-$(CONFIG_AMD_HFI) += amd_hfi.o +amd_hfi-objs := hfi.o diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c new file mode 100644 index 0000000000000..426f7e520b76c --- /dev/null +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Hardware Feedback Interface Driver + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved. + * + * Authors: Perry Yuan + * Mario Limonciello + */ + +#define pr_fmt(fmt) "amd-hfi: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AMD_HFI_DRIVER "amd_hfi" + +#define AMD_HETERO_CPUID_27 0x80000027 + +static struct platform_device *device; + +struct amd_hfi_data { + const char *name; + struct device *dev; + struct mutex lock; +}; + +struct amd_hfi_classes { + u32 perf; + u32 eff; +}; + +/** + * struct amd_hfi_cpuinfo - HFI workload class info per CPU + * @cpu: cpu index + * @class_index: workload class ID index + * @nr_class: max number of workload class supported + * @amd_hfi_classes: current cpu workload class ranking data + * + * Parameters of a logical processor linked with hardware feedback class + */ +struct amd_hfi_cpuinfo { + int cpu; + s16 class_index; + u8 nr_class; + struct amd_hfi_classes *amd_hfi_classes; +}; + +static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; + +static int amd_hfi_alloc_class_data(struct platform_device *pdev) +{ + struct amd_hfi_cpuinfo *hfi_cpuinfo; + struct device *dev = &pdev->dev; + int idx; + int nr_class_id; + + nr_class_id = cpuid_eax(AMD_HETERO_CPUID_27); + if (nr_class_id < 0 || nr_class_id > 255) { + dev_err(dev, "failed to get number of supported classes: %d\n", + nr_class_id); + return -EINVAL; + } + + for_each_possible_cpu(idx) { + struct amd_hfi_classes *classes; + + classes = devm_kcalloc(dev, + nr_class_id, + sizeof(struct amd_hfi_classes), + GFP_KERNEL); + if (!classes) + return -ENOMEM; + hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, idx); + hfi_cpuinfo->amd_hfi_classes = classes; + hfi_cpuinfo->nr_class = nr_class_id; + } + + return 0; +} + +static const struct acpi_device_id amd_hfi_platform_match[] = { + {"AMDI0104", 0}, + { } +}; +MODULE_DEVICE_TABLE(acpi, amd_hfi_platform_match); + +static int amd_hfi_probe(struct platform_device *pdev) +{ + struct amd_hfi_data *amd_hfi_data; + int ret; + + if (!acpi_match_device(amd_hfi_platform_match, &pdev->dev)) + return -ENODEV; + + amd_hfi_data = devm_kzalloc(&pdev->dev, sizeof(*amd_hfi_data), GFP_KERNEL); + if (!amd_hfi_data) + return -ENOMEM; + + amd_hfi_data->dev = &pdev->dev; + ret = devm_mutex_init(&pdev->dev, &amd_hfi_data->lock); + if (ret) + return ret; + platform_set_drvdata(pdev, amd_hfi_data); + + ret = amd_hfi_alloc_class_data(pdev); + if (ret) + return ret; + + return 0; +} + +static struct platform_driver amd_hfi_driver = { + .driver = { + .name = AMD_HFI_DRIVER, + .owner = THIS_MODULE, + .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), + }, + .probe = amd_hfi_probe, +}; + +static int __init amd_hfi_init(void) +{ + int ret; + + if (acpi_disabled || + !cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES) || + !cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + return -ENODEV; + + device = platform_device_register_simple(AMD_HFI_DRIVER, -1, NULL, 0); + if (IS_ERR(device)) { + pr_err("unable to register HFI platform device\n"); + return PTR_ERR(device); + } + + ret = platform_driver_register(&amd_hfi_driver); + if (ret) + pr_err("failed to register HFI driver\n"); + + return ret; +} + +static __exit void amd_hfi_exit(void) +{ + platform_device_unregister(device); + platform_driver_unregister(&amd_hfi_driver); +} +module_init(amd_hfi_init); +module_exit(amd_hfi_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AMD Hardware Feedback Interface Driver"); From patchwork Tue Feb 18 19:08:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980620 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3536E274258; Tue, 18 Feb 2025 19:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 18 Feb 2025 19:08:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905740; bh=6sI0GRW/qnQOu2y/XnVKfxVu+sKklHKajvLwOtU484E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ArCDJ5eQc22nv4zcxRxmpRnL0kttAAZBudyEvitqJBcBzuhXX+L4F5lhZDcolI/zO k69rzejJ2hcxXEvOnsXS5ty5w8MgRrB3Ez24CnsVt/VMp+znGLG6/tPe+QTCaeAGru /Ay/HBjnTsIZlDSK/W/5zxRxFq7oKyNL9RbOwnsi4nsKBMoJ+9oMHg1Yfnp55E34fi 3OErkO/AtU4T9EQ/jOVIHMO+QFdg7BxofSwYZ06HshCLCuOc2vcoWkOD5YcBe+inek B8BtEjfJxR5VyJanGq139MMqDiprT6bB5RmFyKIO1AD377gDLSaZzIwKnQWpT9Wx2N d5qUasYiYFeVA== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v8 05/13] platform/x86: hfi: parse CPU core ranking data from shared memory Date: Tue, 18 Feb 2025 13:08:14 -0600 Message-ID: <20250218190822.1039982-6-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan When `amd_hfi` driver is loaded, it will use PCCT subspace type 4 table to retrieve the shared memory address which contains the CPU core ranking table. This table includes a header that specifies the number of ranking data entries to be parsed and rank each CPU core with the Performance and Energy Efficiency capability as implemented by the CPU power management firmware. Once the table has been parsed, each CPU is assigned a ranking score within its class. Subsequently, when the scheduler selects cores, it chooses from the ranking list based on the assigned scores in each class, thereby ensuring the optimal selection of CPU cores according to their predefined classifications and priorities. Reviewed-by: Ilpo Järvinen Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v3: * Reverse xmas tree order in amd_hfi_fill_metadata() * s,for_each_present_cpu,for_each_possible_cpu, v2: * Drop __packed --- drivers/platform/x86/amd/hfi/hfi.c | 194 +++++++++++++++++++++++++++++ 1 file changed, 194 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 426f7e520b76c..7ab7ae0ec72ca 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -18,22 +18,72 @@ #include #include #include +#include #include +#include #include #include +#include +#include + +#include + +#include +#include #define AMD_HFI_DRIVER "amd_hfi" +#define AMD_HFI_MAILBOX_COUNT 1 +#define AMD_HETERO_RANKING_TABLE_VER 2 #define AMD_HETERO_CPUID_27 0x80000027 static struct platform_device *device; +/** + * struct amd_shmem_info - Shared memory table for AMD HFI + * + * @header: The PCCT table header including signature, length flags and command. + * @version_number: Version number of the table + * @n_logical_processors: Number of logical processors + * @n_capabilities: Number of ranking dimensions (performance, efficiency, etc) + * @table_update_context: Command being sent over the subspace + * @n_bitmaps: Number of 32-bit bitmaps to enumerate all the APIC IDs + * This is based on the maximum APIC ID enumerated in the system + * @reserved: 24 bit spare + * @table_data: Bit Map(s) of enabled logical processors + * Followed by the ranking data for each logical processor + */ +struct amd_shmem_info { + struct acpi_pcct_ext_pcc_shared_memory header; + u32 version_number :8, + n_logical_processors :8, + n_capabilities :8, + table_update_context :8; + u32 n_bitmaps :8, + reserved :24; + u32 table_data[]; +}; + struct amd_hfi_data { const char *name; struct device *dev; struct mutex lock; + + /* PCCT table related*/ + struct pcc_mbox_chan *pcc_chan; + void __iomem *pcc_comm_addr; + struct acpi_subtable_header *pcct_entry; + struct amd_shmem_info *shmem; }; +/** + * struct amd_hfi_classes - HFI class capabilities per CPU + * @perf: Performance capability + * @eff: Power efficiency capability + * + * Capabilities of a logical processor in the ranking table. These capabilities + * are unitless and specific to each HFI class. + */ struct amd_hfi_classes { u32 perf; u32 eff; @@ -42,21 +92,103 @@ struct amd_hfi_classes { /** * struct amd_hfi_cpuinfo - HFI workload class info per CPU * @cpu: cpu index + * @apic_id: apic id of the current cpu * @class_index: workload class ID index * @nr_class: max number of workload class supported + * @ipcc_scores: ipcc scores for each class * @amd_hfi_classes: current cpu workload class ranking data * * Parameters of a logical processor linked with hardware feedback class */ struct amd_hfi_cpuinfo { int cpu; + u32 apic_id; s16 class_index; u8 nr_class; + int *ipcc_scores; struct amd_hfi_classes *amd_hfi_classes; }; static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static int find_cpu_index_by_apicid(unsigned int target_apicid) +{ + int cpu_index; + + for_each_possible_cpu(cpu_index) { + struct cpuinfo_x86 *info = &cpu_data(cpu_index); + + if (info->topo.apicid == target_apicid) { + pr_debug("match APIC id %d for CPU index: %d\n", + info->topo.apicid, cpu_index); + return cpu_index; + } + } + + return -ENODEV; +} + +static int amd_hfi_fill_metadata(struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext = + (struct acpi_pcct_ext_pcc_slave *)amd_hfi_data->pcct_entry; + void __iomem *pcc_comm_addr; + + pcc_comm_addr = acpi_os_ioremap(amd_hfi_data->pcc_chan->shmem_base_addr, + amd_hfi_data->pcc_chan->shmem_size); + if (!pcc_comm_addr) { + pr_err("failed to ioremap PCC common region mem\n"); + return -ENOMEM; + } + + memcpy_fromio(amd_hfi_data->shmem, pcc_comm_addr, pcct_ext->length); + iounmap(pcc_comm_addr); + + if (amd_hfi_data->shmem->header.signature != PCC_SIGNATURE) { + pr_err("invalid signature in shared memory\n"); + return -EINVAL; + } + if (amd_hfi_data->shmem->version_number != AMD_HETERO_RANKING_TABLE_VER) { + pr_err("invalid version %d\n", amd_hfi_data->shmem->version_number); + return -EINVAL; + } + + for (unsigned int i = 0; i < amd_hfi_data->shmem->n_bitmaps; i++) { + u32 bitmap = amd_hfi_data->shmem->table_data[i]; + + for (unsigned int j = 0; j < BITS_PER_TYPE(u32); j++) { + int apic_id = i * BITS_PER_TYPE(u32) + j; + struct amd_hfi_cpuinfo *info; + int cpu_index; + + if (!(bitmap & BIT(j))) + continue; + + cpu_index = find_cpu_index_by_apicid(apic_id); + if (cpu_index < 0) { + pr_warn("APIC ID %d not found\n", apic_id); + continue; + } + + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + info->apic_id = apic_id; + + /* Fill the ranking data for each logical processor */ + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + for (unsigned int k = 0; k < info->nr_class; k++) { + u32 *table = amd_hfi_data->shmem->table_data + + amd_hfi_data->shmem->n_bitmaps + + i * info->nr_class; + + info->amd_hfi_classes[k].eff = table[apic_id + 2 * k]; + info->amd_hfi_classes[k].perf = table[apic_id + 2 * k + 1]; + } + } + } + + return 0; +} + static int amd_hfi_alloc_class_data(struct platform_device *pdev) { struct amd_hfi_cpuinfo *hfi_cpuinfo; @@ -73,6 +205,7 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) for_each_possible_cpu(idx) { struct amd_hfi_classes *classes; + int *ipcc_scores; classes = devm_kcalloc(dev, nr_class_id, @@ -80,14 +213,71 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) GFP_KERNEL); if (!classes) return -ENOMEM; + ipcc_scores = devm_kcalloc(dev, nr_class_id, sizeof(int), GFP_KERNEL); + if (!ipcc_scores) + return -ENOMEM; hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, idx); hfi_cpuinfo->amd_hfi_classes = classes; + hfi_cpuinfo->ipcc_scores = ipcc_scores; hfi_cpuinfo->nr_class = nr_class_id; } return 0; } +static int amd_hfi_metadata_parser(struct platform_device *pdev, + struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext; + struct acpi_subtable_header *pcct_entry; + struct mbox_chan *pcc_mbox_channels; + struct acpi_table_header *pcct_tbl; + struct pcc_mbox_chan *pcc_chan; + acpi_status status; + int ret; + + pcc_mbox_channels = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_mbox_channels), GFP_KERNEL); + if (!pcc_mbox_channels) + return -ENOMEM; + + pcc_chan = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_chan), GFP_KERNEL); + if (!pcc_chan) + return -ENOMEM; + + status = acpi_get_table(ACPI_SIG_PCCT, 0, &pcct_tbl); + if (ACPI_FAILURE(status) || !pcct_tbl) + return -ENODEV; + + /* get pointer to the first PCC subspace entry */ + pcct_entry = (struct acpi_subtable_header *) ( + (unsigned long)pcct_tbl + sizeof(struct acpi_table_pcct)); + + pcc_chan->mchan = &pcc_mbox_channels[0]; + + amd_hfi_data->pcc_chan = pcc_chan; + amd_hfi_data->pcct_entry = pcct_entry; + pcct_ext = (struct acpi_pcct_ext_pcc_slave *)pcct_entry; + + if (pcct_ext->length <= 0) + return -EINVAL; + + amd_hfi_data->shmem = devm_kzalloc(amd_hfi_data->dev, pcct_ext->length, GFP_KERNEL); + if (!amd_hfi_data->shmem) + return -ENOMEM; + + pcc_chan->shmem_base_addr = pcct_ext->base_address; + pcc_chan->shmem_size = pcct_ext->length; + + /* parse the shared memory info from the pcct table */ + ret = amd_hfi_fill_metadata(amd_hfi_data); + + acpi_put_table(pcct_tbl); + + return ret; +} + static const struct acpi_device_id amd_hfi_platform_match[] = { {"AMDI0104", 0}, { } @@ -116,6 +306,10 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + ret = amd_hfi_metadata_parser(pdev, amd_hfi_data); + if (ret) + return ret; + return 0; } From patchwork Tue Feb 18 19:08:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980621 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9A2F274278; Tue, 18 Feb 2025 19:09:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905743; cv=none; b=YLBrPLTExHdbUuK73rrTnaTqFSvai8xaFii00v6C/4uHEDIPpZuzc+wcOHFd7SkpwF2NkMratAsTH6/Vs7AcxoKszcYpbGhd4YRd1A2E42ev33DyEh8v5O++El8LpJizOeNt+1FpwBYGSd5jXq562UN1Zj/CR8RMYhoS06dPMS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v8 06/13] platform/x86: hfi: init per-cpu scores for each class Date: Tue, 18 Feb 2025 13:08:15 -0600 Message-ID: <20250218190822.1039982-7-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Initialize per cpu score `amd_hfi_ipcc_scores` which store energy score and performance score data for each class. `Classic core` and `Dense core` are ranked according to those values as energy efficiency capability or performance capability. OS scheduler will pick cores from the ranking list on each class ID for the thread which provide the class id got from hardware feedback interface. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v8: * s,for_each_present_cpu,for_each_possible_cpu, v7: * Drop mutex, move to proper patch --- drivers/platform/x86/amd/hfi/hfi.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 7ab7ae0ec72ca..e1550f4463275 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -225,6 +225,31 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) return 0; } +static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) +{ + for (int i = 0; i < hfi_cpuinfo->nr_class; i++) + WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], + hfi_cpuinfo->amd_hfi_classes[i].perf); + + return 0; +} + +static int update_hfi_ipcc_scores(void) +{ + int cpu; + int ret; + + for_each_possible_cpu(cpu) { + struct amd_hfi_cpuinfo *hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + + ret = amd_set_hfi_ipcc_score(hfi_cpuinfo, cpu); + if (ret) + return ret; + } + + return 0; +} + static int amd_hfi_metadata_parser(struct platform_device *pdev, struct amd_hfi_data *amd_hfi_data) { @@ -310,6 +335,10 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + ret = update_hfi_ipcc_scores(); + if (ret) + return ret; + return 0; } From patchwork Tue Feb 18 19:08:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980622 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7938927FE93; Tue, 18 Feb 2025 19:09:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905745; cv=none; b=s3gsLujkix8v2QG+POAJRZ15wBzvN/qDSgVGT8FKL233b8K3R3UL0GtcQpcKZnlhPMHfRUEY5iLS/oqu018x+aDPSAcWycKO4ZkcWTlp5vxzZYhyf8vC9VN8TOLQ1PM2wtwZtbQduysVq04AoHZcrkU+paEUXhhRVbDQCqlmuKA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905745; c=relaxed/simple; bh=NW4jI8S9kyv7yhHK+FBK7ulW71BFY6SYyH+TwLYifC8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JsjwJauQulwaQSzcSvVcSgo3D/P4WRB6tiql/hN4q02JSui9qL6+B41DLUQV1zKe2rY9oPN0UNWgplpuZIB01OGAwAEcH2TomSsXM8s7MvZWAybxfjQoYx/eLOfa9ZFdckGuE31L3kr60nW8fDAmJmshZVi1qZX2YThQN6TtJ4k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=opmt2psK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="opmt2psK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0488EC4CEEE; Tue, 18 Feb 2025 19:09:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905744; bh=NW4jI8S9kyv7yhHK+FBK7ulW71BFY6SYyH+TwLYifC8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=opmt2psKA8U/evmb3visAYm3ODRvf7E+eM9ra214p5Gf65zxsZe7fa0tVEv55PsjU /iuxOff9tOnQLtBGG5IeKXFT/RgHGf8xY5jYCIg3Vln4cYn+NbJWYzcy98YujZr04V t+PyivpXOVGjXag9WoUZbd1k/KvFjAKEgdeyzxVZYLWIh5cvlz8PEMi0Qht6UQjVvN luQ8+3/cd5QQQ3lhKSvkClZLfrCSAhTiAiTfhT2MR8XmYxcyYmw4oGddeMXCIC9Dl9 gKJFF/9jY+Hr4XoDkftcypOTV4iigDpbWCeSNMbOfaaN6uk+kXvA88VMsM9zhX5U0X bQpwq1ABLqAxA== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v8 07/13] platform/x86: hfi: add online and offline callback support Date: Tue, 18 Feb 2025 13:08:16 -0600 Message-ID: <20250218190822.1039982-8-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan There are some firmware parameters that need to be configured when a CPU core is brought online or offline. when CPU is online, it will initialize the workload classification parameters to CPU firmware which will trigger the workload class ID updating function. Once the CPU is going to offline, it will need to disable the workload classification function and clear the history. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v8: * Move cpus member to this patch * Add comment about online v7: * move mutex to this patch --- drivers/platform/x86/amd/hfi/hfi.c | 87 ++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index e1550f4463275..90b57175ccd97 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -93,6 +93,7 @@ struct amd_hfi_classes { * struct amd_hfi_cpuinfo - HFI workload class info per CPU * @cpu: cpu index * @apic_id: apic id of the current cpu + * @cpus: mask of cpus associated with amd_hfi_cpuinfo * @class_index: workload class ID index * @nr_class: max number of workload class supported * @ipcc_scores: ipcc scores for each class @@ -103,6 +104,7 @@ struct amd_hfi_classes { struct amd_hfi_cpuinfo { int cpu; u32 apic_id; + cpumask_var_t cpus; s16 class_index; u8 nr_class; int *ipcc_scores; @@ -111,6 +113,8 @@ struct amd_hfi_cpuinfo { static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static DEFINE_MUTEX(hfi_cpuinfo_lock); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -234,6 +238,80 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) return 0; } +static int amd_hfi_set_state(unsigned int cpu, bool state) +{ + int ret; + + ret = wrmsrl_on_cpu(cpu, AMD_WORKLOAD_CLASS_CONFIG, state); + if (ret) + return ret; + + return wrmsrl_on_cpu(cpu, AMD_WORKLOAD_HRST, 0x1); +} + +/** + * amd_hfi_online() - Enable workload classification on @cpu + * @cpu: CPU in which the workload classification will be enabled + * + * Return: 0 on success, negative error code on failure + */ +static int amd_hfi_online(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + struct amd_hfi_classes *hfi_classes; + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + /* + * Check if @cpu as an associated, initialized and ranking data must be filled + */ + hfi_classes = hfi_info->amd_hfi_classes; + if (!hfi_classes) + return -EINVAL; + + guard(mutex)(&hfi_cpuinfo_lock); + + if (!zalloc_cpumask_var(&hfi_info->cpus, GFP_KERNEL)) + return -ENOMEM; + + cpumask_set_cpu(cpu, hfi_info->cpus); + + ret = amd_hfi_set_state(cpu, true); + if (ret) + pr_err("WCT enable failed for CPU %d\n", cpu); + + return ret; +} + +/** + * amd_hfi_offline() - Disable workload classification on @cpu + * @cpu: CPU in which the workload classification will be disabled + * + * Remove @cpu from those covered by its HFI instance. + * + * Return: 0 on success, negative error code on failure + */ +static int amd_hfi_offline(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = &per_cpu(amd_hfi_cpuinfo, cpu); + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + guard(mutex)(&hfi_cpuinfo_lock); + + ret = amd_hfi_set_state(cpu, false); + if (ret) + pr_err("WCT disable failed for CPU %d\n", cpu); + + free_cpumask_var(hfi_info->cpus); + + return ret; +} + static int update_hfi_ipcc_scores(void) { int cpu; @@ -339,6 +417,15 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + /* + * Tasks will already be running at the time this happens. This is + * OK because rankings will be adjusted by the callbacks. + */ + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/amd_hfi:online", + amd_hfi_online, amd_hfi_offline); + if (ret < 0) + return ret; + return 0; } From patchwork Tue Feb 18 19:08:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980623 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80D07280A3B; Tue, 18 Feb 2025 19:09:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905747; cv=none; b=Vvgj94w2c4r83HGLL9t64zvEsrqsLyi8D6IOlQwx1Cyeh+Ntwrfcr6I6w5eTkcRicN/KuB8idMPtHOUwazDTaCeP8ATzDg3yCCI4WEQkEcnWguqxR2oRvCFOSi0lW8Qh9u4duUdTHLjNmkVJX/qcQw0juEFcFSu0u0YCEbDXpnw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905747; c=relaxed/simple; bh=kkmiHVXfJXfM1Y0OJM/t6VFEd5Na7GfS4a+2m3iMWLg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k+FwNq6f+z517C3HNuktTAJ2V8OHXpvo51iwtTdix80RciKTdGIcTP2y7gNvumxrmHp8EJTtpIMai1Qf1y/o22teXeD6IC2oa+90TUme156JSZZXV1i1Pbeu/oenCRrrcjxGlSBwJtPlvfZro4q8MB/hxv/ewSuIDKzEcWlcUFY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZIhAA2CC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZIhAA2CC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2BE33C4CEEB; Tue, 18 Feb 2025 19:09:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905747; bh=kkmiHVXfJXfM1Y0OJM/t6VFEd5Na7GfS4a+2m3iMWLg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZIhAA2CCktPixohzXmZW70xmnmxvwcqLXe8g27dIHBCCSxh6fbayD2QE5k+ZJcQJG y68xysEsJ42aolH8Tzz4zt5ONXz73OfVHsSPpI3j2iWowWt8W1N4noDSj7THqL1e3Y mYR4/UHNxR6YE7XBeOInMu2IRJIrVrC3zMjDGNWQqAzuOyEpC3AsmFw3RbnuRDJ5x8 OTDtpa3HDcoi2a9QKD8io4hEjiBIsnF1itijCZDug+I2SmSgib9EKR0MuqYx8s8pzr CliJELyTWSFVgHH0jVvr8VQkxwomdbeTAaG00VCbJHIgX9q6YQmoV1MIvk2Xeo68Bd U0U/5dSAggNJQ== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v8 08/13] platform/x86: hfi: add power management callback Date: Tue, 18 Feb 2025 13:08:17 -0600 Message-ID: <20250218190822.1039982-9-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduces power management callbacks for the `amd_hfi` driver. Specifically, the `suspend` and `resume` callbacks have been added to handle the necessary operations during system low power states and wake-up. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/hfi.c | 33 ++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 90b57175ccd97..ad93c3b5d5ddf 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -381,6 +381,38 @@ static int amd_hfi_metadata_parser(struct platform_device *pdev, return ret; } +static int amd_hfi_pm_resume(struct device *dev) +{ + int ret, cpu; + + for_each_online_cpu(cpu) { + ret = amd_hfi_set_state(cpu, true); + if (ret < 0) { + dev_err(dev, "failed to enable workload class config: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int amd_hfi_pm_suspend(struct device *dev) +{ + int ret, cpu; + + for_each_online_cpu(cpu) { + ret = amd_hfi_set_state(cpu, false); + if (ret < 0) { + dev_err(dev, "failed to disable workload class config: %d\n", ret); + return ret; + } + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(amd_hfi_pm_ops, amd_hfi_pm_suspend, amd_hfi_pm_resume); + static const struct acpi_device_id amd_hfi_platform_match[] = { {"AMDI0104", 0}, { } @@ -433,6 +465,7 @@ static struct platform_driver amd_hfi_driver = { .driver = { .name = AMD_HFI_DRIVER, .owner = THIS_MODULE, + .pm = &amd_hfi_pm_ops, .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), }, .probe = amd_hfi_probe, From patchwork Tue Feb 18 19:08:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980624 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77B33281363; Tue, 18 Feb 2025 19:09:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905749; cv=none; b=V953DhMIFBSIEYvQixm/zSr1MdrOoTQIaDDfEZLZzUq7idxCH6U+1wpmizExKK+NWNlxtpsdZHDEIkPrrjA9g2sPGK7m/Fe0aORje5qx2W8GcZ0XmbZ1Sayje5VFfwiGaa7UkIULKMVb8UKTZROm3PSgJFrwis5V7Rt4QPtoD/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905749; c=relaxed/simple; bh=SI1sRPnXmV2AWytIfSaxpRG24MRaOV6/z0jvYmJu0ng=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K7+H97ZexRRRvBEXO/7uCD3aJGKPmKrLM71af9X5O759M3i6eHsAFehGjXxMLKkGPEDKVPrkLbMPSvun63f1oFecOZlyGecxRp4orEequv7+u5L6l9auq2c63ozJmFrl0whFoeuPfJe23/ugEOvfPgsRvA3JgtU6KnrpevfNlwk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MM29XqyV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MM29XqyV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B2A3C4CEE9; Tue, 18 Feb 2025 19:09:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905749; bh=SI1sRPnXmV2AWytIfSaxpRG24MRaOV6/z0jvYmJu0ng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MM29XqyVyD2JEs3mtEVhbTMSO0zM5lM9J6SlOgol5maq6slhT7+bchdEWluGedzkX o8CEB7HezddAJtD+RNvSrQ6EtenYXl6McqeZCPWenp009RcuNokXQhRSN649yrx2a0 xvpHhgm+XGVw8yAVUuxreYtvYpKnNqe5+ISq9llyPb2cY4wt3o5u1jmmuXItuVwYJr KCAEhpLY4pzARzw7m5sYYZfhqvEknGLab4YJWXrvQI2otpTDq9/etcvBSBhaBejxSn SdvvWNXnRcl2VCIZ1Nl8WbiupjWQRjpz42/Wys/4tO4QAGm9i8fdNL6JGabbRCNia3 czg9R8dPWgEMQ== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v8 09/13] x86/process: Clear hardware feedback history for AMD processors Date: Tue, 18 Feb 2025 13:08:18 -0600 Message-ID: <20250218190822.1039982-10-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Incorporate a mechanism within the context switching code to reset the hardware history for AMD processors. Specifically, when a task is switched in, the class ID was read and reset the hardware workload classification history of CPU firmware and then it start to trigger workload classification for the next running thread. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v8: * Only for 64 bit --- arch/x86/kernel/process_64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 226472332a70d..371e0e8f987fa 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -709,6 +709,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + /* Reset hw history on AMD CPUs */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); + return prev_p; } From patchwork Tue Feb 18 19:08:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980625 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9489F1E8321; Tue, 18 Feb 2025 19:09:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905751; cv=none; b=Axosrbor1ZMW2fX1DcWsO8aik+JEobU4/vWv1EHiB4ys6gaYYdTWvxfwIgk8CXbgtqbREb+1j1srnuk45aMSDjSN5Bl0S58q2G4rZaYEmokDKhZf4NEQHP0+nfiaU8j7HcwwCzzSgxgq+RH8iuDgeNvYNGSRPE3a00hI6MinjMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905751; c=relaxed/simple; bh=UUsgChwbUHBlYwwpoY3cvOHOZcSsECzzdaCFSYHUK1I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VkmolRxsnFk0zeBacs4ehZ3uR78hl5SbJfxvFUA8TPvUU8eh0Cm7HecuUffvsmpvPKXPfgoapAI7E1rTwohrMbo577x5CRUKuhh6X+0/59oTjHyA4BLGxxvqBiS4hjiqtRvEVaj4TpOyJ4bO4j5W+2O2TWZaaOI1uw72czK5QF8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QsNJs3Bw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QsNJs3Bw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B123C4CEE4; Tue, 18 Feb 2025 19:09:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905751; bh=UUsgChwbUHBlYwwpoY3cvOHOZcSsECzzdaCFSYHUK1I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QsNJs3BwNqhWKEEIqpqH3/O1j7OeTY+o60cE+ilm+2og2JbnP8ttaFBckXUBHBPD+ M4/x2A3SYiXQXSxnADZtkKUQVVn6YVZeIrljNMLurKlOJlN0w+HCsqc+kzxm/Bxn1E MFeDzdlGSlT0PMK8Tljnhb/lee+MGurnu3QCfHEXQGz52631w9JG64H36vo/pRXD0P Qgk4YM6+1r/LbZipXiYztZAdWUPLg3834nsPUBagCA5UbocnV5A8Db/hGdYxpQ8eDk 9NiThExB3ZF7w+Tu+U0QI4P797XRSW6vHemVGZMriDxC8T5/KNABAtkG/HPa19TJeT NtvOXaRDRtk5w== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v8 10/13] cpufreq/amd-pstate: Disable preferred cores on designs with workload classification Date: Tue, 18 Feb 2025 13:08:19 -0600 Message-ID: <20250218190822.1039982-11-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello On designs that have workload classification, it's preferred that the amd-hfi driver is used to provide hints to the scheduler of which cores to use instead of the amd-pstate driver. Reviewed-by: Gautham R. Shenoy Reviewed-by: Perry Yuan Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 08ae480768120..f425fb7ec77d7 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -806,6 +806,12 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) /* user disabled or not detected */ if (!amd_pstate_prefcore) return; + /* should use amd-hfi instead */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS) && + IS_ENABLED(CONFIG_AMD_HFI)) { + amd_pstate_prefcore = false; + return; + } cpudata->hw_prefcore = true; From patchwork Tue Feb 18 19:08:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980626 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 908021E8348; Tue, 18 Feb 2025 19:09:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905753; cv=none; b=MBFXBd3PJS43UmNXLo3IbYmUT/p3StTfXGDgdBoATW/MtwzOpC0epfJgKGbmdzlQ1HpeX8Mw6pMJIBRuyLnnAq0FuS0OQ7P4t0hYYV5nEXqGTH6hJJotreG1+WFEeK3951n1jek2yNbOTtFx8dMi+FXUKgCHE7U0k3P8PC0JCdA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905753; c=relaxed/simple; bh=YGEAUNoTxiERCe+Zc0PbxN3oROVjMDUCDEuhQhPA2Wg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LP6k5tRUHJD27BGhzzdjv84En9tioW+3j4px64E9DCsjL+8GOVZaY13cpFU8sLGvc3Zx+sl4RZHjahTteDcnBHWZGRCn+WHHug/W7O/eOimeMMZlhqOPTAd7ADbgJTk0A+91mPLyBFykYSzdXtlfwUwIRB5GwhLiIDwLIjg840Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gmU0Fz5t; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gmU0Fz5t" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 51B67C4AF0B; Tue, 18 Feb 2025 19:09:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905753; bh=YGEAUNoTxiERCe+Zc0PbxN3oROVjMDUCDEuhQhPA2Wg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gmU0Fz5tJAaUm6z+U40ArTbs2+jxyzM3QuDxgNSpak9bqS+kNKjO+j7J7IaT1BCvB uVQVR9HQmncLS45cO0QMOTHgMc42JBeRyERVS2fX5c3EoKd6VyLga4AjLBUWkGmgLM sP7MPUPJqdhPevq4pzQZgYZiQ2LrMTtX1ASJFLXYwmWOPEtBknTWZ9EacNgDhhZITc nPNyuzEP2qKW48J2p+wFw1W2fmu8tQhhhqKDm1SPTSmxFAuU7/aX5ohVV8rbnk71tX LEQCAC/rXke7aWAzeSH3vLFgz5N+xFnqOxxK75lGDsCRKXilnIWofXid0aye/sOehs N4AjBcCJUVkJA== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v8 11/13] platform/x86/amd: hfi: Set ITMT priority from ranking data Date: Tue, 18 Feb 2025 13:08:20 -0600 Message-ID: <20250218190822.1039982-12-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello The static ranking data that is read at module load should be used to set up the priorities for the cores relative to the performance values. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/Kconfig | 1 + drivers/platform/x86/amd/hfi/hfi.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig index 532939eb08a6a..045f598f4866c 100644 --- a/drivers/platform/x86/amd/hfi/Kconfig +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -7,6 +7,7 @@ config AMD_HFI bool "AMD Hetero Core Hardware Feedback Driver" depends on ACPI depends on CPU_SUP_AMD + depends on SCHED_MC_PRIO help Select this option to enable the AMD Heterogeneous Core Hardware Feedback Interface. If selected, hardware provides runtime thread diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index ad93c3b5d5ddf..14378a0e09e21 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -115,6 +115,12 @@ static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = static DEFINE_MUTEX(hfi_cpuinfo_lock); +static void amd_hfi_sched_itmt_work(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_amd_hfi_itmt_work, amd_hfi_sched_itmt_work); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -235,6 +241,8 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], hfi_cpuinfo->amd_hfi_classes[i].perf); + sched_set_itmt_core_prio(hfi_cpuinfo->ipcc_scores[0], cpu); + return 0; } @@ -458,6 +466,8 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret < 0) return ret; + schedule_work(&sched_amd_hfi_itmt_work); + return 0; } From patchwork Tue Feb 18 19:08:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980628 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A10171EFF9C; Tue, 18 Feb 2025 19:09:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905757; cv=none; b=Uph5lVCfZ/ZDZx0A+Or1zvUr0vhmsPRj2hdDTx5p9LYCAENc8M73J+QE1WjbTxXH5Y2BEO3g4N1gnC5q/GYxSCIQ5Nnn138208XH7VtTVdkqOvv/t5P+6ZF0oEZLRNZDZJLN9lgPKfQQhZsDhDnm7+60rEET4PT0ScfWUFdk/8M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905757; c=relaxed/simple; bh=5tqtTKe1lqiBpYBvved5ezJFmx7RjdV4hMjpw3suVTk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n2x1d82X9gn3fhzC7v8j8PbKTOJKosbq5uTjCRZjBMjHU+nNh+hZ61OMaXh52+qGtn+40rmhuzJXuFJfCu/QwHL7/7StvSfQ2L0NwLMpn//e04R0FWNLDlMd9faZblqu9kjq/yYYh0TJEjA3GhaqkKuvQPKs2r1MYjIMKboYbrg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tyiiETFR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tyiiETFR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 519D7C4CEE9; Tue, 18 Feb 2025 19:09:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905755; bh=5tqtTKe1lqiBpYBvved5ezJFmx7RjdV4hMjpw3suVTk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tyiiETFRaKcaoJQl/R1X4oOg3uJimyVxjlG8636VT9ZAeFE7YYa0PSU7ORdtkbkdM noymckPMHYpTiivADmqXWs0hWEEYiHBn52vwQNxDdjo2o3DB4QQCVWhon3FDU9sBJL /zC6mUL0iq7T0fTZHdiz9hWQBmZLpCBsFXnU5t79nFICRrmxria3CtXAlaYUKbTJ3B sD4G0Kw4c99VU9kGE9xLN7NEmGoqtWcyW5K9qvne8O+vcgMM3F0+eygTp5hqsYiMHp KwEvU/ZdwOcI7Ls/YZ/n3BsDoLdmAWE6z8ESajOfOCt2V9Gk0IPG3ADqIbiwhzsePm i3KTmpYSOVV/Q== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v8 12/13] platform/x86/amd: hfi: Add debugfs support Date: Tue, 18 Feb 2025 13:08:21 -0600 Message-ID: <20250218190822.1039982-13-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Add a dump of the class and capabilities table to debugfs to assist with debugging scheduler issues. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v8: * s,for_each_present_cpu,for_each_possible_cpu, v3: * Move idx to earlier line --- drivers/platform/x86/amd/hfi/hfi.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 14378a0e09e21..79d065d7b6441 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -74,6 +75,8 @@ struct amd_hfi_data { void __iomem *pcc_comm_addr; struct acpi_subtable_header *pcct_entry; struct amd_shmem_info *shmem; + + struct dentry *dbgfs_dir; }; /** @@ -235,6 +238,13 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) return 0; } +static void amd_hfi_remove(struct platform_device *pdev) +{ + struct amd_hfi_data *dev = platform_get_drvdata(pdev); + + debugfs_remove_recursive(dev->dbgfs_dir); +} + static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) { for (int i = 0; i < hfi_cpuinfo->nr_class; i++) @@ -389,6 +399,26 @@ static int amd_hfi_metadata_parser(struct platform_device *pdev, return ret; } +static int class_capabilities_show(struct seq_file *s, void *unused) +{ + int cpu, idx; + + seq_puts(s, "CPU #\tWLC\tPerf\tEff\n"); + for_each_possible_cpu(cpu) { + struct amd_hfi_cpuinfo *hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + + seq_printf(s, "%d", cpu); + for (idx = 0; idx < hfi_cpuinfo->nr_class; idx++) { + seq_printf(s, "\t%d\t%d\t%d\n", idx, + hfi_cpuinfo->amd_hfi_classes[idx].perf, + hfi_cpuinfo->amd_hfi_classes[idx].eff); + } + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(class_capabilities); + static int amd_hfi_pm_resume(struct device *dev) { int ret, cpu; @@ -468,6 +498,10 @@ static int amd_hfi_probe(struct platform_device *pdev) schedule_work(&sched_amd_hfi_itmt_work); + amd_hfi_data->dbgfs_dir = debugfs_create_dir("amd_hfi", arch_debugfs_dir); + debugfs_create_file("class_capabilities", 0644, amd_hfi_data->dbgfs_dir, pdev, + &class_capabilities_fops); + return 0; } @@ -479,6 +513,7 @@ static struct platform_driver amd_hfi_driver = { .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), }, .probe = amd_hfi_probe, + .remove = amd_hfi_remove, }; static int __init amd_hfi_init(void) From patchwork Tue Feb 18 19:08:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13980627 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32E0D1EFF8F; Tue, 18 Feb 2025 19:09:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905757; cv=none; b=hEvdBoPil3F8NrUDZrgWL2ps2kzciUy+Oe/g+BGhzOnBppkBlaHJeIsex/8RTRxIzpJK1PBjtiLfCbQIJerTHRdwUidE1YWsoLvv2Qfe7MkEZ/xuuuUdF/2y1ms/l0UfiqBLFvn6Facr18znmPajj+q7krupU0Zy0T9fpNWVvJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739905757; c=relaxed/simple; bh=3a2aiKieSWb1qeAo/5/1a29z/LlaFpGijoR/tz4zb+Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IDrJwZ4kxQ1BC3gA6IB1ZG4XtJGHlQ/+r1KV7uLJZrQZRD5cascDlx/bIm+3ot+UDbtMFSHu4/bUsaKWr9j7cMLcvIh0B4WouKLuFi/gvgHCVWymh7OrtMY7MQ0RXlayUZecINEp9mABVImkHPQ7ozeduwOQ5ONizUo74sj6eig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=vHd56J4b; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="vHd56J4b" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5A4B2C4CEE2; Tue, 18 Feb 2025 19:09:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739905757; bh=3a2aiKieSWb1qeAo/5/1a29z/LlaFpGijoR/tz4zb+Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vHd56J4bBmHA9XnvNr7WiwE5lzEPPSTgfAMBbSOw49Hq/0j6jqN3bY4LAhIeQZXpC DT7e4ltB+t5geG0ru2zkQbnWghEEkxlRXywH7xeNZhYOe3jdxC8ENYeKqvNWTKQwuZ GP98ehz2CWvV5MEWfq5wYSVbAV8PKLNXXHlmMAZKftkR22GVdEwzXWlVh/FG524H09 mmi/ZuhZta2hMpQe6RI4hAGx8ybkIJNHLrd4BUGHxy7+W9Xry+MKpW22SWcWGJJgbS pJU0xy0L7xyL6RBG5uwdikMvl4YPRk0SpGJzgQwuxUzP0JvmHyHznDpA7LD+1CQtx0 wUq5FBW9UUF4A== From: Mario Limonciello To: Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v8 13/13] x86/itmt: Add debugfs file to show core priorities Date: Tue, 18 Feb 2025 13:08:22 -0600 Message-ID: <20250218190822.1039982-14-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250218190822.1039982-1-superm1@kernel.org> References: <20250218190822.1039982-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Multiple drivers can report priorities to ITMT. To aid in debugging any issues with the values reported by drivers introduce a debugfs file to read out the values. Signed-off-by: Mario Limonciello --- v8: * New patch arch/x86/kernel/itmt.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/itmt.c b/arch/x86/kernel/itmt.c index 9cea1fc36c18f..243a769fdd97b 100644 --- a/arch/x86/kernel/itmt.c +++ b/arch/x86/kernel/itmt.c @@ -59,6 +59,18 @@ static ssize_t sched_itmt_enabled_write(struct file *filp, return result; } +static int sched_core_priority_show(struct seq_file *s, void *unused) +{ + int cpu; + + seq_puts(s, "CPU #\tPriority\n"); + for_each_possible_cpu(cpu) + seq_printf(s, "%d\t%d\n", cpu, arch_asym_cpu_priority(cpu)); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(sched_core_priority); + static const struct file_operations dfs_sched_itmt_fops = { .read = debugfs_read_file_bool, .write = sched_itmt_enabled_write, @@ -67,6 +79,7 @@ static const struct file_operations dfs_sched_itmt_fops = { }; static struct dentry *dfs_sched_itmt; +static struct dentry *dfs_sched_core_prio; /** * sched_set_itmt_support() - Indicate platform supports ITMT @@ -102,6 +115,14 @@ int sched_set_itmt_support(void) return -ENOMEM; } + dfs_sched_core_prio = debugfs_create_file("sched_core_priority", 0644, + arch_debugfs_dir, NULL, + &sched_core_priority_fops); + if (IS_ERR_OR_NULL(dfs_sched_core_prio)) { + dfs_sched_core_prio = NULL; + return -ENOMEM; + } + sched_itmt_capable = true; sysctl_sched_itmt_enabled = 1; @@ -133,6 +154,8 @@ void sched_clear_itmt_support(void) debugfs_remove(dfs_sched_itmt); dfs_sched_itmt = NULL; + debugfs_remove(dfs_sched_core_prio); + dfs_sched_core_prio = NULL; if (sysctl_sched_itmt_enabled) { /* disable sched_itmt if we are no longer ITMT capable */