From patchwork Wed Feb 19 09:20:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jay Liu X-Patchwork-Id: 13983128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6439C021B0 for ; Wed, 19 Feb 2025 23:48:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B7E710E0C4; Wed, 19 Feb 2025 23:48:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="tmsH5njP"; dkim-atps=neutral Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD39510E799 for ; Wed, 19 Feb 2025 09:21:05 +0000 (UTC) X-UUID: d58151f2eea211efaae1fd9735fae912-20250219 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ojz46lwYrvC+/B96oirWUt9+aNCFGHjtvSOr+aVZyPo=; b=tmsH5njPU/sbbKgGbGgDtd6N6jcoMJI/K3LQB3sSNiBbikEpAaC2kS6VjWH001pgnHLHainlMQX8d6Eagdw52sR3qoc15UjGGOVlMf8cbI7DqDLm42Jjt7HuMOSn4D8SOjj6T0/jgkmFfAVmMX/zenUlbYXZ0cT5C/p9AmBubKM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46, REQID:68169584-d22d-47b8-9084-39b50c05f11e, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:60aa074, CLOUDID:9df8fe28-e0f8-414e-b8c3-b75c08217be8, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: d58151f2eea211efaae1fd9735fae912-20250219 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 844446571; Wed, 19 Feb 2025 17:21:00 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 19 Feb 2025 17:20:59 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 19 Feb 2025 17:20:58 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu , CK Hu , Hsin-Yi Wang CC: , , , , , , Jay Liu Subject: [PATCH 1/7] drm/mediatek: Add CCORR component support for MT8196 Date: Wed, 19 Feb 2025 17:20:34 +0800 Message-ID: <20250219092040.11227-2-jay.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20250219092040.11227-1-jay.liu@mediatek.com> References: <20250219092040.11227-1-jay.liu@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 19 Feb 2025 23:48:37 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add CCORR component support for MT8196. CCORR is a hardware module that optimizes the visual effects of images by adjusting the color matrix, enabling features such as night light. The 8196 hardware platform includes two CCORR (Color Correction) units. However, the `mtk_ccorr_ctm_set` API only utilizes one of these units. To prevent the unused CCORR unit from inadvertently taking effect, we need to block it by adding mandatory_ccorr flag in the driver_data. Signed-off-by: Jay Liu --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 3 ++- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index edc6417639e6..d7e230bac53e 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -457,7 +457,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, + [DDP_COMPONENT_CCORR0] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, + [DDP_COMPONENT_CCORR1] = { MTK_DISP_CCORR, 1, &ddp_ccorr }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither }, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 10d60d2c2a56..94e82b3fa2d8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -31,11 +31,13 @@ struct mtk_disp_ccorr_data { u32 matrix_bits; + enum mtk_ddp_comp_id mandatory_ccorr; }; struct mtk_disp_ccorr { struct clk *clk; void __iomem *regs; + enum mtk_ddp_comp_id comp_id; struct cmdq_client_reg cmdq_reg; const struct mtk_disp_ccorr_data *data; }; @@ -115,6 +117,9 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) if (!blob) return; + if (ccorr->comp_id != ccorr->data->mandatory_ccorr) + return; + ctm = (struct drm_color_ctm *)blob->data; input = ctm->matrix; @@ -154,6 +159,7 @@ static int mtk_disp_ccorr_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mtk_disp_ccorr *priv; int ret; + enum mtk_ddp_comp_id comp_id; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -169,6 +175,14 @@ static int mtk_disp_ccorr_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(priv->regs), "failed to ioremap ccorr\n"); + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_CCORR); + if (comp_id < 0) { + dev_err(dev, "Failed to identify by alias: %d\n", comp_id); + return comp_id; + } + + priv->comp_id = comp_id; + #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); if (ret) @@ -192,10 +206,12 @@ static void mtk_disp_ccorr_remove(struct platform_device *pdev) static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { .matrix_bits = 10, + .mandatory_ccorr = DDP_COMPONENT_CCORR0, }; static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { .matrix_bits = 11, + .mandatory_ccorr = DDP_COMPONENT_CCORR0, }; static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { From patchwork Wed Feb 19 09:20:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jay Liu X-Patchwork-Id: 13983129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C266C021B1 for ; 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Wed, 19 Feb 2025 17:21:03 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 19 Feb 2025 17:21:01 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 19 Feb 2025 17:21:00 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu , CK Hu , Hsin-Yi Wang CC: , , , , , , Jay Liu Subject: [PATCH 2/7] drm/mediatek: fix CCORR mtk_ctm_s31_32_to_s1_n function issue Date: Wed, 19 Feb 2025 17:20:35 +0800 Message-ID: <20250219092040.11227-3-jay.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20250219092040.11227-1-jay.liu@mediatek.com> References: <20250219092040.11227-1-jay.liu@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 19 Feb 2025 23:48:37 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" if matrixbit is 11, The range of color matrix is from 0 to (BIT(11) - 1). Values from 0 to (BIT(11) - 1) represent positive numbers, values from BIT(11) to (BIT(12) - 1) represent negative numbers. For example, -1 need converted to 8191. Fixes: 738ed4156fba ("drm/mediatek: Add matrix_bits private data for ccorr") Signed-off-by: Jay Liu --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 94e82b3fa2d8..a9f91b71534b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -100,6 +100,15 @@ static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) r |= (in >> (32 - n)) & GENMASK(n, 0); } + /* + *The range of r is from 0 to (BIT(n + 1) - 1), + *where values from 0 to (BIT(n) - 1) represent positive numbers, + *and values from BIT(n) to (BIT(n + 1) - 1) represent negative numbers. + *For example, if n is 11, -1 will be converted to 8191. + */ + if (r & BIT(n + 1)) + r = (~(r & GENMASK(n, 0)) + 1) & GENMASK(n + 1, 0); + return r; } From patchwork Wed Feb 19 09:20:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jay Liu X-Patchwork-Id: 13983130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9EFBC021B0 for ; Wed, 19 Feb 2025 23:48:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 40F2A10E8A9; Wed, 19 Feb 2025 23:48:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="jcBSJ+hw"; dkim-atps=neutral Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 893A110E799 for ; Wed, 19 Feb 2025 09:21:11 +0000 (UTC) X-UUID: d862c036eea211efaae1fd9735fae912-20250219 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=RvnJMlnup8mEpwfevKOMTTVHsPosdfiR6HlWkNh6UU8=; b=jcBSJ+hwKm+tYgduKJRQkMiOMXiSq4Jy7I2AQZGppBlciOqllMBn3XhfxxYGKscfkRIpRnBmNF+DmF/fEl5eC0G+2DTvfu8lpqyyjhaNCi+SlCX5a2jS8VVhYtzJWZ/V57kTvwSqGooRoQspcRD6TkY1wGblYOM5lPyS7eWF0Hs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46, REQID:f7e2c174-f04b-4eef-a0ec-148530822d50, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:60aa074, CLOUDID:f95d51b5-a2a1-4ef3-9ef9-e116773da0a7, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: d862c036eea211efaae1fd9735fae912-20250219 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1733944336; Wed, 19 Feb 2025 17:21:05 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 19 Feb 2025 17:21:03 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 19 Feb 2025 17:21:02 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu , CK Hu , Hsin-Yi Wang CC: , , , , , , Jay Liu Subject: [PATCH 3/7] drm/mediatek: Add TDSHP component support for MT8196 Date: Wed, 19 Feb 2025 17:20:36 +0800 Message-ID: <20250219092040.11227-4-jay.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20250219092040.11227-1-jay.liu@mediatek.com> References: <20250219092040.11227-1-jay.liu@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 19 Feb 2025 23:48:37 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add TDSHP component support for MT8196. TDSHP is a hardware module designed to enhance the sharpness and clarity of displayed images by analyzing and improving edges and fine details in frames. Signed-off-by: Jay Liu --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 58 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 + 3 files changed, 61 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index d7e230bac53e..b87fde64ee49 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -57,6 +57,16 @@ #define POSTMASK_RELAY_MODE BIT(0) #define DISP_REG_POSTMASK_SIZE 0x0030 +#define DISP_REG_TDSHP_EN 0x0000 +#define DISP_TDSHP_TDS_EN BIT(31) +#define DISP_REG_TDSHP_CTRL 0x0100 +#define DISP_TDSHP_CTRL_EN BIT(0) +#define DISP_TDSHP_PWR_SCL_EN BIT(2) +#define DISP_REG_TDSHP_CFG 0x0110 +#define DISP_REG_TDSHP_INPUT_SIZE 0x0120 +#define DISP_REG_TDSHP_OUTPUT_OFFSET 0x0124 +#define DISP_REG_TDSHP_OUTPUT_SIZE 0x0128 + #define DISP_REG_UFO_START 0x0000 #define UFO_BYPASS BIT(2) @@ -261,6 +271,44 @@ static void mtk_postmask_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN); } +static void mtk_disp_tdshp_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + u32 tdshp_ctrl = (bpc == 8) ? DISP_TDSHP_PWR_SCL_EN | DISP_TDSHP_CTRL_EN : 0; + + mtk_ddp_write(cmdq_pkt, tdshp_ctrl, &priv->cmdq_reg, priv->regs, + DISP_REG_TDSHP_CTRL); + + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, + DISP_REG_TDSHP_INPUT_SIZE); + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, + DISP_REG_TDSHP_OUTPUT_SIZE); + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs, + DISP_REG_TDSHP_OUTPUT_OFFSET); + + mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, + priv->regs, DISP_REG_TDSHP_CFG); + + mtk_ddp_write_mask(cmdq_pkt, DISP_TDSHP_TDS_EN, &priv->cmdq_reg, priv->regs, + DISP_REG_TDSHP_EN, DISP_TDSHP_TDS_EN); +} + +static void mtk_disp_tdshp_start(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel(DISP_TDSHP_CTRL_EN, priv->regs + DISP_REG_TDSHP_CTRL); +} + +static void mtk_disp_tdshp_stop(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel(0x0, priv->regs + DISP_REG_TDSHP_CTRL); +} + static void mtk_ufoe_start(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); @@ -268,6 +316,14 @@ static void mtk_ufoe_start(struct device *dev) writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); } +static const struct mtk_ddp_comp_funcs ddp_tdshp = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_disp_tdshp_config, + .start = mtk_disp_tdshp_start, + .stop = mtk_disp_tdshp_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_aal = { .clk_enable = mtk_aal_clk_enable, .clk_disable = mtk_aal_clk_disable, @@ -440,6 +496,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_POSTMASK] = "postmask", [MTK_DISP_PWM] = "pwm", [MTK_DISP_RDMA] = "rdma", + [MTK_DISP_TDSHP] = "tdshp", [MTK_DISP_UFOE] = "ufoe", [MTK_DISP_WDMA] = "wdma", [MTK_DP_INTF] = "dp-intf", @@ -495,6 +552,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma }, + [DDP_COMPONENT_TDSHP0] = { MTK_DISP_TDSHP, 0, &ddp_tdshp }, [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h index 39720b27f4e9..fc90d32b8c2e 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_type { MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_RDMA, + MTK_DISP_TDSHP, MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index f22ad2882697..4ec09864bc8c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -790,6 +790,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8195-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8196-disp-tdshp", + .data = (void *)MTK_DISP_TDSHP }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt8173-disp-wdma", From patchwork Wed Feb 19 09:20:37 2025 Content-Type: text/plain; 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Wed, 19 Feb 2025 17:21:10 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 19 Feb 2025 17:21:06 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 19 Feb 2025 17:21:05 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu , CK Hu , Hsin-Yi Wang CC: , , , , , , Jay Liu Subject: [PATCH 4/7] dt-bindings: display: mediatek: ccorr: Add support for MT8196 Date: Wed, 19 Feb 2025 17:20:37 +0800 Message-ID: <20250219092040.11227-5-jay.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20250219092040.11227-1-jay.liu@mediatek.com> References: <20250219092040.11227-1-jay.liu@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 19 Feb 2025 23:48:37 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a compatible string for MediaTek MT8196 SoC Signed-off-by: Jay Liu --- .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index fca8e7bb0cbc..581003aa9b9c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8186-disp-ccorr - mediatek,mt8188-disp-ccorr - mediatek,mt8195-disp-ccorr + - mediatek,mt8196-disp-ccorr - const: mediatek,mt8192-disp-ccorr reg: From patchwork Wed Feb 19 09:20:38 2025 Content-Type: text/plain; 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Wed, 19 Feb 2025 17:21:09 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 19 Feb 2025 17:21:08 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 19 Feb 2025 17:21:07 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu , CK Hu , Hsin-Yi Wang CC: , , , , , , Jay Liu Subject: [PATCH 5/7] dt-bindings: display: mediatek: dither: Add support for MT8196 Date: Wed, 19 Feb 2025 17:20:38 +0800 Message-ID: <20250219092040.11227-6-jay.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20250219092040.11227-1-jay.liu@mediatek.com> References: <20250219092040.11227-1-jay.liu@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 19 Feb 2025 23:48:37 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a compatible string for MediaTek MT8196 SoC Signed-off-by: Jay Liu --- .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index abaf27916d13..1f1719228b5d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither - mediatek,mt8365-disp-dither + - mediatek,mt8196-disp-dither - const: mediatek,mt8183-disp-dither reg: From patchwork Wed Feb 19 09:20:39 2025 Content-Type: text/plain; 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Wed, 19 Feb 2025 17:21:11 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 19 Feb 2025 17:21:10 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 19 Feb 2025 17:21:09 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu , CK Hu , Hsin-Yi Wang CC: , , , , , , Jay Liu Subject: [PATCH 6/7] dt-bindings: display: mediatek: gamma: Add support for MT8196 Date: Wed, 19 Feb 2025 17:20:39 +0800 Message-ID: <20250219092040.11227-7-jay.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20250219092040.11227-1-jay.liu@mediatek.com> References: <20250219092040.11227-1-jay.liu@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 19 Feb 2025 23:48:37 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a compatible string for MediaTek MT8196 SoC Signed-off-by: Jay Liu --- .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index 48542dc7e784..513e51c6d2b9 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -40,6 +40,7 @@ properties: - items: - enum: - mediatek,mt8188-disp-gamma + - mediatek,mt8196-disp-gamma - const: mediatek,mt8195-disp-gamma reg: From patchwork Wed Feb 19 09:20:40 2025 Content-Type: text/plain; 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Wed, 19 Feb 2025 17:21:16 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 19 Feb 2025 17:21:15 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 19 Feb 2025 17:21:14 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu , CK Hu , Hsin-Yi Wang CC: , , , , , , Jay Liu Subject: [PATCH 7/7] dt-bindings: display: mediatek: tdshp: Add support for MT8196 Date: Wed, 19 Feb 2025 17:20:40 +0800 Message-ID: <20250219092040.11227-8-jay.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20250219092040.11227-1-jay.liu@mediatek.com> References: <20250219092040.11227-1-jay.liu@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 19 Feb 2025 23:48:37 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a compatible string for MediaTek MT8196 SoC Signed-off-by: Jay Liu --- .../display/mediatek/mediatek,tdshp.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml new file mode 100644 index 000000000000..5ed7bdd53d0e --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,tdshp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display clarity correction + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: | + MediaTek display clarity correction, namely TDSHP, provides a + operation used to adjust sharpness in display system. + TDSHP device node must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml + for details. +properties: + compatible: + oneOf: + - enum: + - mediatek,mt8196-disp-tdshp + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + + soc { + #address-cells = <2>; + #size-cells = <2>; + + tdshp@321e0000 { + compatible = "mediatek,mt8196-disp-tdshp"; + reg = <0 0x321e0000 0 0x1000>; + clocks = <&dispsys_config_clk 107>; + }; + };