From patchwork Thu Feb 20 07:38:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Naveen N Rao (AMD)" X-Patchwork-Id: 13983445 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54C0E1E5734; Thu, 20 Feb 2025 07:41:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740037304; cv=none; b=QiYYS6E92GJdfOctWRxWzjkOP6PA8o0iaTMexYHafof4BjjUVzcGXko1J0pvg18OrPX1fYi3aC1wzYAt7RDa3HihwqJgqeWzZlMap4tGlIzAkOPrR+GTZA5Sj/7WXa539QFQPp6wLaXlNw74fb8zDhjD4emRETLrNCLJipMlc0s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740037304; c=relaxed/simple; bh=5x0s1WlNtpqFXMyrSmNE9vzJHobilFLK27L/pcU/Ilw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oRql3K1r2I1TEmyS7sVALRGHq+ARAhSih3/mYAukpEvWRBsS13VC10xBwlSw6AZuZIm27E5feYnjIRaBsbWG7fFqu5uKMgW6YewHy+lWGIrDaoKKxxiuvv2AY+PeahOAo7s3v1eHyQAUiUYrar2Kr1tJLjpXwY1W568bBPEK+H8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PZ655Cyo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PZ655Cyo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 35B7AC4CEDD; Thu, 20 Feb 2025 07:41:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740037302; bh=5x0s1WlNtpqFXMyrSmNE9vzJHobilFLK27L/pcU/Ilw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PZ655CyoPlDc4RvyQwajAJJSoowEXHi1sCwjPzd0KI3EBkXM0NKxYlO0D0s8ZabQW eZ6Iu3Uv7L1EtGioujNXqOUc1QwVGjKrOIkKzPWmlkR+vVvMeU8DwH5+BQkgEsr4Va /L0t8fNCc5ERpaOIhAlSNE66GAgwM2VaSm2qXWbX7mi/V4WiJvBEFyAmhPw+dngWlh MJSJ3wOuOG/c6SDdIQuje28bm2Qu2tmNurkm29rfckXAOEOYM2jTlsNb5nad6u4NMP G9S5K7NK1wfKcWNEtOp0xDWrfafzeqvNH50eX+sWRf/orl7fzZMKMRr+THDIyr7v2C S6yajYalJy1gg== From: "Naveen N Rao (AMD)" To: , Cc: Sean Christopherson , Paolo Bonzini , Suravee Suthikulpanit , Vasant Hegde Subject: [PATCH v3 1/2] KVM: SVM: Increase X2AVIC limit to 4096 vcpus Date: Thu, 20 Feb 2025 13:08:02 +0530 Message-ID: <330d10700c1172982bcb7947a37c0351f7b50958.1740036492.git.naveen@kernel.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Suravee Suthikulpanit Newer AMD platforms enhance x2AVIC feature to support up to 4096 vcpus. This capatility is detected via CPUID_Fn8000000A_ECX[x2AVIC_EXT]. Modify the SVM driver to check the capability. If detected, extend bitmask for guest max physical APIC ID to 0xFFF, increase maximum vcpu index to 4095, and increase the size of the Phyical APIC ID table from 4K to 32K in order to accommodate up to 4096 entries. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/svm.h | 4 ++++ arch/x86/kvm/svm/avic.c | 45 ++++++++++++++++++++++++++------------ 2 files changed, 35 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index e2fac21471f5..4ff5b2f767e1 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -268,6 +268,7 @@ enum avic_ipi_failure_cause { }; #define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(8, 0) +#define AVIC_PHYSICAL_MAX_INDEX_4K_MASK GENMASK_ULL(11, 0) /* * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254), as @@ -277,11 +278,14 @@ enum avic_ipi_failure_cause { /* * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (511). + * For extended x2AVIC, the max index allowed for physical APIC ID table is 0xfff (4095). */ #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL +#define X2AVIC_MAX_PHYSICAL_ID_4K 0xFFFUL static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == AVIC_MAX_PHYSICAL_ID); static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_MAX_PHYSICAL_ID); +static_assert((X2AVIC_MAX_PHYSICAL_ID_4K & AVIC_PHYSICAL_MAX_INDEX_4K_MASK) == X2AVIC_MAX_PHYSICAL_ID_4K); #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 65fd245a9953..1fb322d2ac18 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -38,9 +38,9 @@ * size of the GATag is defined by hardware (32 bits), but is an opaque value * as far as hardware is concerned. */ -#define AVIC_VCPU_ID_MASK AVIC_PHYSICAL_MAX_INDEX_MASK +#define AVIC_VCPU_ID_MASK AVIC_PHYSICAL_MAX_INDEX_4K_MASK -#define AVIC_VM_ID_SHIFT HWEIGHT32(AVIC_PHYSICAL_MAX_INDEX_MASK) +#define AVIC_VM_ID_SHIFT HWEIGHT32(AVIC_PHYSICAL_MAX_INDEX_4K_MASK) #define AVIC_VM_ID_MASK (GENMASK(31, AVIC_VM_ID_SHIFT) >> AVIC_VM_ID_SHIFT) #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VM_ID_SHIFT) & AVIC_VM_ID_MASK) @@ -73,6 +73,9 @@ static u32 next_vm_id = 0; static bool next_vm_id_wrapped = 0; static DEFINE_SPINLOCK(svm_vm_data_hash_lock); bool x2avic_enabled; +static bool x2avic_4k_vcpu_supported; +static u64 x2avic_max_physical_id; +static u64 avic_physical_max_index_mask; /* * This is a wrapper of struct amd_iommu_ir_data. @@ -87,7 +90,7 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) struct vmcb *vmcb = svm->vmcb01.ptr; vmcb->control.int_ctl &= ~(AVIC_ENABLE_MASK | X2APIC_MODE_MASK); - vmcb->control.avic_physical_id &= ~AVIC_PHYSICAL_MAX_INDEX_MASK; + vmcb->control.avic_physical_id &= ~avic_physical_max_index_mask; vmcb->control.int_ctl |= AVIC_ENABLE_MASK; @@ -100,7 +103,7 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) */ if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { vmcb->control.int_ctl |= X2APIC_MODE_MASK; - vmcb->control.avic_physical_id |= X2AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |= x2avic_max_physical_id; /* Disabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, false); } else { @@ -122,7 +125,7 @@ static void avic_deactivate_vmcb(struct vcpu_svm *svm) struct vmcb *vmcb = svm->vmcb01.ptr; vmcb->control.int_ctl &= ~(AVIC_ENABLE_MASK | X2APIC_MODE_MASK); - vmcb->control.avic_physical_id &= ~AVIC_PHYSICAL_MAX_INDEX_MASK; + vmcb->control.avic_physical_id &= ~avic_physical_max_index_mask; /* * If running nested and the guest uses its own MSR bitmap, there @@ -182,7 +185,8 @@ void avic_vm_destroy(struct kvm *kvm) if (kvm_svm->avic_logical_id_table_page) __free_page(kvm_svm->avic_logical_id_table_page); if (kvm_svm->avic_physical_id_table_page) - __free_page(kvm_svm->avic_physical_id_table_page); + __free_pages(kvm_svm->avic_physical_id_table_page, + get_order(sizeof(u64) * (x2avic_max_physical_id + 1))); spin_lock_irqsave(&svm_vm_data_hash_lock, flags); hash_del(&kvm_svm->hnode); @@ -197,13 +201,15 @@ int avic_vm_init(struct kvm *kvm) struct kvm_svm *k2; struct page *p_page; struct page *l_page; - u32 vm_id; + u32 vm_id, entries; if (!enable_apicv) return 0; - /* Allocating physical APIC ID table (4KB) */ - p_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); + /* Allocating physical APIC ID table */ + entries = x2avic_max_physical_id + 1; + p_page = alloc_pages(GFP_KERNEL_ACCOUNT | __GFP_ZERO, + get_order(sizeof(u64) * entries)); if (!p_page) goto free_avic; @@ -266,7 +272,7 @@ static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm); if ((!x2avic_enabled && index > AVIC_MAX_PHYSICAL_ID) || - (index > X2AVIC_MAX_PHYSICAL_ID)) + (index > x2avic_max_physical_id)) return NULL; avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page); @@ -281,7 +287,7 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) struct vcpu_svm *svm = to_svm(vcpu); if ((!x2avic_enabled && id > AVIC_MAX_PHYSICAL_ID) || - (id > X2AVIC_MAX_PHYSICAL_ID)) + (id > x2avic_max_physical_id)) return -EINVAL; if (!vcpu->arch.apic->regs) @@ -493,7 +499,7 @@ int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu) u32 icrh = svm->vmcb->control.exit_info_1 >> 32; u32 icrl = svm->vmcb->control.exit_info_1; u32 id = svm->vmcb->control.exit_info_2 >> 32; - u32 index = svm->vmcb->control.exit_info_2 & 0x1FF; + u32 index = svm->vmcb->control.exit_info_2 & avic_physical_max_index_mask; struct kvm_lapic *apic = vcpu->arch.apic; trace_kvm_avic_incomplete_ipi(vcpu->vcpu_id, icrh, icrl, id, index); @@ -1218,8 +1224,19 @@ bool avic_hardware_setup(void) /* AVIC is a prerequisite for x2AVIC. */ x2avic_enabled = boot_cpu_has(X86_FEATURE_X2AVIC); - if (x2avic_enabled) - pr_info("x2AVIC enabled\n"); + if (x2avic_enabled) { + x2avic_4k_vcpu_supported = !!(cpuid_ecx(0x8000000a) & 0x40); + if (x2avic_4k_vcpu_supported) { + x2avic_max_physical_id = X2AVIC_MAX_PHYSICAL_ID_4K; + avic_physical_max_index_mask = AVIC_PHYSICAL_MAX_INDEX_4K_MASK; + } else { + x2avic_max_physical_id = X2AVIC_MAX_PHYSICAL_ID; + avic_physical_max_index_mask = AVIC_PHYSICAL_MAX_INDEX_MASK; + } + + pr_info("x2AVIC enabled%s\n", + x2avic_4k_vcpu_supported ? " (w/ 4K-vcpu)" : ""); + } amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); From patchwork Thu Feb 20 07:38:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Naveen N Rao (AMD)" X-Patchwork-Id: 13983446 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AF5F1EB1AA; Thu, 20 Feb 2025 07:41:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740037308; cv=none; b=ilY0rniJUwKiCzJt9oe7HpAkp8DXxZwoxcMbeTYF8H8WT6uWFIjda/g3tSwwS7zTDwt6LuHRXEdYrzYceZn6x7KciB1HsLvxVg/+F395kxlCogYvDnc6Jj/uvZRMoqvCePjvUUFkaWGlQJLS4yQN5tJRK9f+Z4lSozSPVZku0/U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740037308; c=relaxed/simple; bh=2m5fMq0w89y2cVxObSFljzgnxj6ecbAOXIvZHg3WaRs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M2B62/dn4xflWPIQ0ymQRxMwJxtK4heh2C5jCX9H++hL4lml3g3DYCeNSvVkWLe7OW6HOTFVvFL3eqaGCOp+q98y6zHh1vIbUXMWSZXawCkevby1CAKtWKgu5DBjAVqCOb/x1G6RXXpd3JJ3TZ5mlfEWo1B9QY6DYPU9idMQIy0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=modqC0LJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="modqC0LJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 07757C4CED1; Thu, 20 Feb 2025 07:41:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740037307; bh=2m5fMq0w89y2cVxObSFljzgnxj6ecbAOXIvZHg3WaRs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=modqC0LJcC7bgfBYPaLE7oc1nMfrcxeR9HtewLJuggSQgluMo4oLcOKZRiYIYdzBj izRGFZ2toDIfcJPUdARSICdfjOyCgWpS88Mdz8ZXEvRhc22HWiApgQbc/LfKuf/o8c /dz+u+jgE0S7Y8wHxJkfCu+82oxSybafr2be6P6KwJ/82CNQ8umdvMAK8yknswXUtk jbInxR+lE4cKDlhfmof10kzeRrjGsrnhuzcYnFwFOkUABvC33n9J7f6NQUV9EXD7SX bJxeXGTk+1DYvfG38uuTBIbytQikn8P/Aqu3S9nTefbr3YEu6qsUXdOAkHnRzdP+wO NwWLVeMqMVfkQ== From: "Naveen N Rao (AMD)" To: , Cc: Sean Christopherson , Paolo Bonzini , Suravee Suthikulpanit , Vasant Hegde Subject: [PATCH v3 2/2] KVM: SVM: Limit AVIC physical max index based on configured max_vcpu_ids Date: Thu, 20 Feb 2025 13:08:03 +0530 Message-ID: X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 KVM allows VMMs to specify the maximum possible APIC ID for a virtual machine through KVM_CAP_MAX_VCPU_ID capability so as to limit data structures related to APIC/x2APIC. Utilize the same to set the AVIC physical max index in the VMCB, similar to VMX. This helps hardware limit the number of entries to be scanned in the physical APIC ID table speeding up IPI broadcasts for virtual machines with smaller number of vcpus. The minimum allocation required for the Physical APIC ID table is one 4k page supporting up to 512 entries. With AVIC support for 4096 vcpus though, it is sufficient to only allocate memory to accommodate the AVIC physical max index that will be programmed into the VMCB. Limit memory allocated for the Physical APIC ID table accordingly. Signed-off-by: Naveen N Rao (AMD) Reviewed-by: Pankaj Gupta --- arch/x86/kvm/svm/avic.c | 53 ++++++++++++++++++++++++++++++----------- arch/x86/kvm/svm/svm.c | 6 +++++ arch/x86/kvm/svm/svm.h | 1 + 3 files changed, 46 insertions(+), 14 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 1fb322d2ac18..dac4a6648919 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -85,6 +85,17 @@ struct amd_svm_iommu_ir { void *data; /* Storing pointer to struct amd_ir_data */ }; +static inline u32 avic_get_max_physical_id(struct kvm *kvm, bool is_x2apic) +{ + u32 avic_max_physical_id = is_x2apic ? x2avic_max_physical_id : AVIC_MAX_PHYSICAL_ID; + + /* + * Assume vcpu_id is the same as APIC ID. Per KVM_CAP_MAX_VCPU_ID, max_vcpu_ids + * represents the max APIC ID for this vm, rather than the max vcpus. + */ + return min(kvm->arch.max_vcpu_ids - 1, avic_max_physical_id); +} + static void avic_activate_vmcb(struct vcpu_svm *svm) { struct vmcb *vmcb = svm->vmcb01.ptr; @@ -103,7 +114,7 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) */ if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { vmcb->control.int_ctl |= X2APIC_MODE_MASK; - vmcb->control.avic_physical_id |= x2avic_max_physical_id; + vmcb->control.avic_physical_id |= avic_get_max_physical_id(svm->vcpu.kvm, true); /* Disabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, false); } else { @@ -114,7 +125,7 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, &svm->vcpu); /* For xAVIC and hybrid-xAVIC modes */ - vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |= avic_get_max_physical_id(svm->vcpu.kvm, false); /* Enabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, true); } @@ -174,6 +185,12 @@ int avic_ga_log_notifier(u32 ga_tag) return 0; } +static inline int avic_get_physical_id_table_order(struct kvm *kvm) +{ + /* Limit to the maximum physical ID supported in x2avic mode */ + return get_order((avic_get_max_physical_id(kvm, true) + 1) * sizeof(u64)); +} + void avic_vm_destroy(struct kvm *kvm) { unsigned long flags; @@ -186,7 +203,7 @@ void avic_vm_destroy(struct kvm *kvm) __free_page(kvm_svm->avic_logical_id_table_page); if (kvm_svm->avic_physical_id_table_page) __free_pages(kvm_svm->avic_physical_id_table_page, - get_order(sizeof(u64) * (x2avic_max_physical_id + 1))); + avic_get_physical_id_table_order(kvm)); spin_lock_irqsave(&svm_vm_data_hash_lock, flags); hash_del(&kvm_svm->hnode); @@ -199,22 +216,12 @@ int avic_vm_init(struct kvm *kvm) int err = -ENOMEM; struct kvm_svm *kvm_svm = to_kvm_svm(kvm); struct kvm_svm *k2; - struct page *p_page; struct page *l_page; - u32 vm_id, entries; + u32 vm_id; if (!enable_apicv) return 0; - /* Allocating physical APIC ID table */ - entries = x2avic_max_physical_id + 1; - p_page = alloc_pages(GFP_KERNEL_ACCOUNT | __GFP_ZERO, - get_order(sizeof(u64) * entries)); - if (!p_page) - goto free_avic; - - kvm_svm->avic_physical_id_table_page = p_page; - /* Allocating logical APIC ID table (4KB) */ l_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); if (!l_page) @@ -265,6 +272,24 @@ void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb) avic_deactivate_vmcb(svm); } +int avic_alloc_physical_id_table(struct kvm *kvm) +{ + struct kvm_svm *kvm_svm = to_kvm_svm(kvm); + struct page *p_page; + + if (kvm_svm->avic_physical_id_table_page || !enable_apicv || !irqchip_in_kernel(kvm)) + return 0; + + p_page = alloc_pages(GFP_KERNEL_ACCOUNT | __GFP_ZERO, + avic_get_physical_id_table_order(kvm)); + if (!p_page) + return -ENOMEM; + + kvm_svm->avic_physical_id_table_page = p_page; + + return 0; +} + static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, unsigned int index) { diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index b8aa0f36850f..3cb23298cdc3 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1423,6 +1423,11 @@ void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb) svm->vmcb = target_vmcb->ptr; } +static int svm_vcpu_precreate(struct kvm *kvm) +{ + return avic_alloc_physical_id_table(kvm); +} + static int svm_vcpu_create(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm; @@ -5007,6 +5012,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .emergency_disable_virtualization_cpu = svm_emergency_disable_virtualization_cpu, .has_emulated_msr = svm_has_emulated_msr, + .vcpu_precreate = svm_vcpu_precreate, .vcpu_create = svm_vcpu_create, .vcpu_free = svm_vcpu_free, .vcpu_reset = svm_vcpu_reset, diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 5b159f017055..b4670afe0034 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -694,6 +694,7 @@ bool avic_hardware_setup(void); int avic_ga_log_notifier(u32 ga_tag); void avic_vm_destroy(struct kvm *kvm); int avic_vm_init(struct kvm *kvm); +int avic_alloc_physical_id_table(struct kvm *kvm); void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu);