From patchwork Fri Feb 21 07:18:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChunHao Lin X-Patchwork-Id: 13984895 X-Patchwork-Delegate: kuba@kernel.org Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C2B41FE443; Fri, 21 Feb 2025 07:19:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740122364; cv=none; b=P/f1H04coL5mI9IMyDPFpz5VHiluq8lRoTIj+BtjLT4ebR4L95ZlUxur6EkgG7+2AkWSzBquRyBdcvX/5KIjLFdeZCyKxEXDYSG9PPAT1CCj60PUvAZPw2HtomfWSd+juvIr55gM3Za+EdgDEtIdVCTX2nT5vYN88UNqV/ULfx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740122364; c=relaxed/simple; bh=PztQzWtJ2SLBJTPpC8NuKA2Zrl1gqV/FzrKY5msalnY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aYq357aBIgyC7yqTYoRT0cVhrQEzRLmZ5t7+3mWq8+Ezab90S5hdhOxGMx2qqhhKYkHIE51gAu9hK7PY3KpBVYSFAXtU5NvIhqesvSqM3CPoB0MnMrtnM9TW3hP5QNW7ZeBInVKkTT9GCysLzvwA1RsBGr/7CLiGVYgWXWQZGx8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=temperror (0-bit key) header.d=realtek.com header.i=@realtek.com header.b=ef1DVhpa; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=realtek.com header.i=@realtek.com header.b="ef1DVhpa" X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 51L7IejyE1489827, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realtek.com; s=dkim; t=1740122320; bh=PztQzWtJ2SLBJTPpC8NuKA2Zrl1gqV/FzrKY5msalnY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=ef1DVhpa+tzCWpLe6Qteda0fhx5lzXJtxOz9KNvsASnvwVMKfNGxnrogW/9J91Xer XWO6mK8HS7thRvpkLttFJXAj/5xlY2D5izQJrPEuATNWzeZqhdyh28XJknkk9Dy2p4 WHkpQJHTSvuOA64DYcjs8A2AMX12qCoaAkmAixsTgF+l2qdW/86Wfl8ginke1+tqKu YwbmeYCWgr7aPYfg/NcQrEhSltSJBekzpeX0wL1fFLIn/QKrm5XsQej2BwQ8ACgTPi /Dofu6jDCCy1/t+IE+3130XD1a9xP0U0cswIGOb6pRJzhJhoU3Hq0IoSVcHvpSO8aQ 5MtvhWftKeeZA== Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/3.06/5.92) with ESMTPS id 51L7IejyE1489827 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 21 Feb 2025 15:18:40 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 21 Feb 2025 15:18:40 +0800 Received: from RTEXH36505.realtek.com.tw (172.21.6.25) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 21 Feb 2025 15:18:37 +0800 Received: from fc40.realtek.com.tw (172.22.241.7) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 21 Feb 2025 15:18:37 +0800 From: ChunHao Lin To: , , , , , , CC: , , ChunHao Lin Subject: [PATCH net-next 1/3] r8169: enable RTL8168H/RTL8168EP/RTL8168FP ASPM support Date: Fri, 21 Feb 2025 15:18:26 +0800 Message-ID: <20250221071828.12323-440-nic_swsd@realtek.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250221071828.12323-439-nic_swsd@realtek.com> References: <20250221071828.12323-439-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-Patchwork-Delegate: kuba@kernel.org This patch will enable RTL8168H/RTL8168EP/RTL8168FP ASPM support on the platforms that have tested with ASPM enabled. Signed-off-by: ChunHao Lin Reviewed-by: Heiner Kallweit --- drivers/net/ethernet/realtek/r8169_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index fa339bd8c775..731302361989 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -5394,7 +5394,7 @@ static void rtl_init_mac_address(struct rtl8169_private *tp) /* register is set if system vendor successfully tested ASPM 1.2 */ static bool rtl_aspm_is_safe(struct rtl8169_private *tp) { - if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && + if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) return true; From patchwork Fri Feb 21 07:18:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChunHao Lin X-Patchwork-Id: 13984897 X-Patchwork-Delegate: kuba@kernel.org Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C25F1FCCE9; Fri, 21 Feb 2025 07:19:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740122364; cv=none; b=YY6EPVsWpVAAz9eU3YAts8OS8Vo5fr3Q3u6b9LBkkOxjPCxK42nJM/khS6cEtzbdmv+dU+Y4jUxLrdAyAVIvHBxAbBMQqTpue9PTXkkIP2WytRMCfYWEyZyp1UT0O0KFvIfP2AhcgZyCQ4779UN4n60R2eXjugvLS6L8v75cMXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740122364; c=relaxed/simple; bh=EOqgPKfRw6fHKRcscN6V0azTs4N6D/BrVvwMtWWjraU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Nc40hMYZIm78fXPfcnb4FLPU4nOuLqIpnJXezi2GudhaD1FpobdhYXVSurwJ4axFlcqEPgq50LChvUCzbwiuPuCMnf8wgj91fAVDK3G9PdchOcD2kcY71dvKBdr1NPFyRkdWtj/YDfoKQuPiTAeCN0hjehsoMDPbGdx6tbGaICc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=temperror (0-bit key) header.d=realtek.com header.i=@realtek.com header.b=bGoSAQ9N; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=realtek.com header.i=@realtek.com header.b="bGoSAQ9N" X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 51L7Iek061489827, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realtek.com; s=dkim; t=1740122320; bh=EOqgPKfRw6fHKRcscN6V0azTs4N6D/BrVvwMtWWjraU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=bGoSAQ9NkKPiqJg7Hz+b3QDfgD51S3kzez/ZnKPSCrnVhZU2s5eMdKICd/VkUVayi t41tBn5uMM/LSZkI8Wcljbn+3leyz593Y3Vd+hCPnLee+c9lk7l61HY/2draRthMzO xpcBehbCEboiqB1saehiO0bA59CoT0p1DSXjCCulHpeWb0H1sUO6HHwsmrlnMT29Zo qNFnykanL1IQWkpv5Cw1rFrejJ3hWKL0/1rqdO8kY5Icc3vploJzq/bjhXxe9cd1bc MtGR20nJcKzDwVB7zs/NLRO4OtQpC3WaHrhrOu4SuRqc/iZGHeeuERVlSA3dhcP3pD zfBJKtExzp1UQ== Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/3.06/5.92) with ESMTPS id 51L7Iek061489827 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 21 Feb 2025 15:18:40 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 21 Feb 2025 15:18:40 +0800 Received: from RTEXH36505.realtek.com.tw (172.21.6.25) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 21 Feb 2025 15:18:37 +0800 Received: from fc40.realtek.com.tw (172.22.241.7) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 21 Feb 2025 15:18:37 +0800 From: ChunHao Lin To: , , , , , , CC: , , ChunHao Lin Subject: [PATCH net-next 2/3] r8169: enable RTL8168H/RTL8168EP/RTL8168FP/RTL8125/RTL8126 LTR support Date: Fri, 21 Feb 2025 15:18:27 +0800 Message-ID: <20250221071828.12323-441-nic_swsd@realtek.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250221071828.12323-439-nic_swsd@realtek.com> References: <20250221071828.12323-439-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-Patchwork-Delegate: kuba@kernel.org This patch will enable RTL8168H/RTL8168EP/RTL8168FP/RTL8125/RTL8126 LTR support on the platforms that have tested with LTR enabled. Signed-off-by: ChunHao Lin --- drivers/net/ethernet/realtek/r8169_main.c | 108 ++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index 731302361989..9953eaa01c9d 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -2955,6 +2955,111 @@ static void rtl_disable_exit_l1(struct rtl8169_private *tp) } } +static void rtl_set_ltr_latency(struct rtl8169_private *tp) +{ + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_70: + case RTL_GIGA_MAC_VER_71: + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd2, 0x8c09); + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd4, 0x9003); + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); + r8168_mac_ocp_write(tp, 0xcde8, 0x887a); + r8168_mac_ocp_write(tp, 0xcdea, 0x9003); + r8168_mac_ocp_write(tp, 0xcdec, 0x8c09); + r8168_mac_ocp_write(tp, 0xcdee, 0x9003); + r8168_mac_ocp_write(tp, 0xcdf0, 0x8a62); + r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); + r8168_mac_ocp_write(tp, 0xcdf4, 0x883e); + r8168_mac_ocp_write(tp, 0xcdf6, 0x9003); + break; + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd2, 0x889c); + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c30); + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); + r8168_mac_ocp_write(tp, 0xcde8, 0x883e); + r8168_mac_ocp_write(tp, 0xcdea, 0x9003); + r8168_mac_ocp_write(tp, 0xcdec, 0x889c); + r8168_mac_ocp_write(tp, 0xcdee, 0x9003); + r8168_mac_ocp_write(tp, 0xcdf0, 0x8C09); + r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); + break; + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_53: + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd2, 0x883c); + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12); + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); + break; + default: + break; + } +} + +static void rtl_reset_pci_ltr(struct rtl8169_private *tp) +{ + struct pci_dev *pdev = tp->pci_dev; + u16 cap; + + pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap); + if (cap & PCI_EXP_DEVCTL2_LTR_EN) { + pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); + pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); + } +} + +static void rtl_enable_ltr(struct rtl8169_private *tp) +{ + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: + r8168_mac_ocp_modify(tp, 0xe034, 0x0000, 0xc000); + r8168_mac_ocp_modify(tp, 0xe0a2, 0x0000, BIT(0)); + r8168_mac_ocp_modify(tp, 0xe032, 0x0000, BIT(14)); + break; + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: + case RTL_GIGA_MAC_VER_52 ... RTL_GIGA_MAC_VER_53: + r8168_mac_ocp_modify(tp, 0xe0a2, 0x0000, BIT(0)); + RTL_W8(tp, 0xb6, RTL_R8(tp, 0xb6) | BIT(0)); + fallthrough; + case RTL_GIGA_MAC_VER_51: + r8168_mac_ocp_modify(tp, 0xe034, 0x0000, 0xc000); + r8168_mac_ocp_write(tp, 0xe02c, 0x1880); + r8168_mac_ocp_write(tp, 0xe02e, 0x4880); + break; + default: + return; + } + + rtl_set_ltr_latency(tp); + + /* chip can trigger LTR */ + r8168_mac_ocp_modify(tp, 0xe032, 0x0003, BIT(0)); + + /* reset LTR to notify host */ + rtl_reset_pci_ltr(tp); +} + +static void rtl_disable_ltr(struct rtl8169_private *tp) +{ + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_71: + r8168_mac_ocp_modify(tp, 0xe032, 0x0003, 0); + break; + default: + break; + } +} + static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) { u8 val8; @@ -2971,6 +3076,8 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) tp->mac_version == RTL_GIGA_MAC_VER_43) return; + rtl_enable_ltr(tp); + rtl_mod_config5(tp, 0, ASPM_en); switch (tp->mac_version) { case RTL_GIGA_MAC_VER_70: @@ -4821,6 +4928,7 @@ static void rtl8169_down(struct rtl8169_private *tp) rtl8169_cleanup(tp); rtl_disable_exit_l1(tp); + rtl_disable_ltr(tp); rtl_prepare_power_down(tp); if (tp->dash_type != RTL_DASH_NONE) From patchwork Fri Feb 21 07:18:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChunHao Lin X-Patchwork-Id: 13984896 X-Patchwork-Delegate: kuba@kernel.org Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C19D1FBCAF; Fri, 21 Feb 2025 07:19:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740122364; cv=none; b=JO2Lq22zO5/RlfozQYLmFNu6Hgr7mNl8I+I12XpOFRVy4Tg/FdKp+4lGR0yocZCzzKUW0pfG4qfX/hsIIM5VYTOSGRiS4CrJrYIA/FYgUHr/mrFE28Sfl1aMDv6GSVJUCWGg9Pugb1OWEGiAmUz18sRTB34c4Mku7XuaIBPexEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740122364; c=relaxed/simple; bh=IWFjlCH/kLyoap2CM8IgWET+F6vKtvdYg6i397zwm1k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FDUtZl8geYzPgXPGCFm2xZP5Ek5HWqpfKWoc4mYfAyZsJz0BBuovEaCUJsWl4QB9dFa1kJtsP7y4eRz3YYJVY1Rgq2FoWwrbS2Xgug2ydlOskrnHF6Z2Hiy1QrVIxfC3FrqvmP+ZzU5cQ1LCo++KkFCmXcrJfmYVn5nAhMfZ0dA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=temperror (0-bit key) header.d=realtek.com header.i=@realtek.com header.b=oF80Q8qZ; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=realtek.com header.i=@realtek.com header.b="oF80Q8qZ" X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 51L7IgTlA1489835, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realtek.com; s=dkim; t=1740122322; bh=IWFjlCH/kLyoap2CM8IgWET+F6vKtvdYg6i397zwm1k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=oF80Q8qZ2Y6KHqRUg6UCRbOQl57Gb8qiYI1DC8rj0S3Nzxw0R3b/eOOUAo4NPkRjm CSO+OduKfQ1Au3UDBcZwrrmDRHa4YRWFrhYI12eN8Y9M6Ij1mopHXpg0LLVtxAYxc1 3YCimHv/8+QQ2wUNxv/T9ynFdaOo39cbs/xw3/oL/NfgSrlY1eb7XXtUxEwNZnQfEZ GMK846EvhV9wl+qS4JOEBpRaBxxQg9y3ETUaJYe8pXKLx4I6FNtqFRMgr4Nrq9vipt n5VxhRwg96hZjUO6RWqCFgEH/ZySuFLTlV8lbCsk/e17KSV8vkD7q9nmTlKslULPvz fQGt/ysqzn+oA== Received: from mail.realtek.com (rtexh36505.realtek.com.tw[172.21.6.25]) by rtits2.realtek.com.tw (8.15.2/3.06/5.92) with ESMTPS id 51L7IgTlA1489835 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 21 Feb 2025 15:18:42 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 21 Feb 2025 15:18:42 +0800 Received: from RTEXH36505.realtek.com.tw (172.21.6.25) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 21 Feb 2025 15:18:38 +0800 Received: from fc40.realtek.com.tw (172.22.241.7) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 21 Feb 2025 15:18:38 +0800 From: ChunHao Lin To: , , , , , , CC: , , ChunHao Lin Subject: [PATCH net-next 3/3] r8169: disable RTL8126 ZRX-DC timeout Date: Fri, 21 Feb 2025 15:18:28 +0800 Message-ID: <20250221071828.12323-442-nic_swsd@realtek.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250221071828.12323-439-nic_swsd@realtek.com> References: <20250221071828.12323-439-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-Patchwork-Delegate: kuba@kernel.org Disable it due to it dose not meet ZRX-DC specification. If it is enabled, device will exit L1 substate every 100ms. Disable it for saving more power in L1 substate. Signed-off-by: ChunHao Lin --- drivers/net/ethernet/realtek/r8169_main.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index 9953eaa01c9d..7a5b99d54e12 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -2851,6 +2851,21 @@ static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) RTL_R32(tp, CSIDR) : ~0; } +static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp) +{ + struct pci_dev *pdev = tp->pci_dev; + u8 val; + + if (pdev->cfg_size > 0x0890 && + pci_read_config_byte(pdev, 0x0890, &val) == PCIBIOS_SUCCESSFUL && + pci_write_config_byte(pdev, 0x0890, val & ~BIT(0)) == PCIBIOS_SUCCESSFUL) + return; + + netdev_notice_once(tp->dev, + "No native access to PCI extended config space, falling back to CSI\n"); + rtl_csi_write(tp, 0x0890, rtl_csi_read(tp, 0x0890) & ~BIT(0)); +} + static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) { struct pci_dev *pdev = tp->pci_dev; @@ -3930,6 +3945,7 @@ static void rtl_hw_start_8125d(struct rtl8169_private *tp) static void rtl_hw_start_8126a(struct rtl8169_private *tp) { + rtl_disable_zrxdc_timeout(tp); rtl_set_def_aspm_entry_latency(tp); rtl_hw_start_8125_common(tp); }