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Fri, 21 Feb 2025 11:19:49 -0800 (PST) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] dt-bindings: bus: add documentation for the IMX AIPSTZ bridge Date: Fri, 21 Feb 2025 14:19:05 -0500 Message-Id: <20250221191909.31874-2-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> References: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Laurentiu Mihalcea Add documentation for IMX AIPSTZ bridge. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li --- .../bindings/bus/fsl,imx8mp-aipstz.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml new file mode 100644 index 000000000000..b0d6eaf70a84 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8mp-aipstz.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Secure AHB to IP Slave bus (AIPSTZ) bridge + +description: + The secure AIPS bridge (AIPSTZ) acts as a bridge for AHB masters + issuing transactions to IP Slave peripherals. Additionally, this module + offers access control configurations meant to restrict which peripherals + a master can access. + +maintainers: + - Laurentiu Mihalcea + +select: + properties: + compatible: + contains: + const: fsl,imx8mp-aipstz + required: + - compatible + +properties: + compatible: + items: + - const: fsl,imx8mp-aipstz + - const: simple-bus + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#access-controller-cells": + const: 0 + +required: + - compatible + - reg + - power-domains + - "#access-controller-cells" + +allOf: + - $ref: /schemas/simple-bus.yaml# + +unevaluatedProperties: false + +examples: + - | + bus@30df0000 { + compatible = "fsl,imx8mp-aipstz", "simple-bus"; + reg = <0x30df0000 0x10000>; + power-domains = <&pgc_audio>; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <0>; + ranges; + }; From patchwork Fri Feb 21 19:19:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurentiu Mihalcea X-Patchwork-Id: 13986200 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC3AA253344 for ; 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Fri, 21 Feb 2025 11:19:51 -0800 (PST) Received: from playground.nxp.com ([82.79.237.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb9cee79fasm995276266b.129.2025.02.21.11.19.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 11:19:51 -0800 (PST) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] dt-bindings: dsp: fsl,dsp: document 'access-controllers' property Date: Fri, 21 Feb 2025 14:19:06 -0500 Message-Id: <20250221191909.31874-3-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> References: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Laurentiu Mihalcea Some DSP instances may have their access to certain peripherals conditioned by a bus access controller such as the one from the AIPSTZ bridge. Add the optional 'access-controllers' property, which may be used in such cases. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li --- Documentation/devicetree/bindings/dsp/fsl,dsp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml index ab93ffd3d2e5..869df7fcece0 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -82,6 +82,9 @@ properties: description: Phandle to syscon block which provide access for processor enablement + access-controllers: + maxItems: 1 + required: - compatible - reg From patchwork Fri Feb 21 19:19:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurentiu Mihalcea X-Patchwork-Id: 13986201 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA34C25335B for ; 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Fri, 21 Feb 2025 11:19:53 -0800 (PST) Received: from playground.nxp.com ([82.79.237.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb9cee79fasm995276266b.129.2025.02.21.11.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 11:19:53 -0800 (PST) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] bus: add driver for IMX AIPSTZ bridge Date: Fri, 21 Feb 2025 14:19:07 -0500 Message-Id: <20250221191909.31874-4-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> References: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Laurentiu Mihalcea The secure AHB to IP Slave (AIPSTZ) bus bridge provides access control configurations meant to restrict access to certain peripherals. Some of the configurations include: 1) Marking masters as trusted for R/W. Based on this (and the configuration of the accessed peripheral), the bridge may choose to abort the R/W transactions issued by certain masters. 2) Allowing/disallowing write accesses to peripherals. Add driver for this IP. Since there's currently no framework for access controllers (and since there's currently no need for having flexibility w.r.t the configurations) all this driver does is it applies a relaxed, "default" configuration, in which all masters are trusted for R/W. Note that some instances of this IP may be tied to a power domain and may lose their configuration when the domain is powered off. This is why the configuration has to be restored when the domain is powered on. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea --- drivers/bus/Kconfig | 6 +++ drivers/bus/Makefile | 1 + drivers/bus/imx-aipstz.c | 92 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 99 insertions(+) create mode 100644 drivers/bus/imx-aipstz.c diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index ff669a8ccad9..fe7600283e70 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -87,6 +87,12 @@ config HISILICON_LPC Driver to enable I/O access to devices attached to the Low Pin Count bus on the HiSilicon Hip06/7 SoC. +config IMX_AIPSTZ + tristate "Support for IMX Secure AHB to IP Slave bus (AIPSTZ) bridge" + depends on ARCH_MXC + help + Enable support for IMX AIPSTZ bridge. + config IMX_WEIM bool "Freescale EIM DRIVER" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index cddd4984d6af..8e693fe8a03a 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/ obj-$(CONFIG_BT1_APB) += bt1-apb.o obj-$(CONFIG_BT1_AXI) += bt1-axi.o +obj-$(CONFIG_IMX_AIPSTZ) += imx-aipstz.o obj-$(CONFIG_IMX_WEIM) += imx-weim.o obj-$(CONFIG_INTEL_IXP4XX_EB) += intel-ixp4xx-eb.o obj-$(CONFIG_MIPS_CDMM) += mips_cdmm.o diff --git a/drivers/bus/imx-aipstz.c b/drivers/bus/imx-aipstz.c new file mode 100644 index 000000000000..75696eac8ba2 --- /dev/null +++ b/drivers/bus/imx-aipstz.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include + +#define IMX_AIPSTZ_MPR0 0x0 + +struct imx_aipstz_config { + u32 mpr0; +}; + +static void imx_aipstz_apply_default(void __iomem *base, + const struct imx_aipstz_config *default_cfg) +{ + writel(default_cfg->mpr0, base + IMX_AIPSTZ_MPR0); +} + +static int imx_aipstz_probe(struct platform_device *pdev) +{ + void __iomem *base; + const struct imx_aipstz_config *default_cfg; + + base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(base)) + return dev_err_probe(&pdev->dev, -ENOMEM, + "failed to get/ioremap memory\n"); + + default_cfg = of_device_get_match_data(&pdev->dev); + + imx_aipstz_apply_default(base, default_cfg); + + dev_set_drvdata(&pdev->dev, base); + + pm_runtime_set_active(&pdev->dev); + devm_pm_runtime_enable(&pdev->dev); + + return devm_of_platform_populate(&pdev->dev); +} + +static int imx_aipstz_runtime_resume(struct device *dev) +{ + void __iomem *base; + const struct imx_aipstz_config *default_cfg; + + base = dev_get_drvdata(dev); + default_cfg = of_device_get_match_data(dev); + + /* restore potentially lost configuration during domain power-off */ + imx_aipstz_apply_default(base, default_cfg); + + return 0; +} + +static const struct dev_pm_ops imx_aipstz_pm_ops = { + RUNTIME_PM_OPS(NULL, imx_aipstz_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + +/* + * following configuration is equivalent to: + * masters 0-7 => trusted for R/W + use AHB's HPROT[1] to det. privilege + */ +static const struct imx_aipstz_config imx8mp_aipstz_default_cfg = { + .mpr0 = 0x77777777, +}; + +static const struct of_device_id imx_aipstz_of_ids[] = { + { .compatible = "fsl,imx8mp-aipstz", .data = &imx8mp_aipstz_default_cfg }, + { } +}; +MODULE_DEVICE_TABLE(of, imx_aipstz_of_ids); + +static struct platform_driver imx_aipstz_of_driver = { + .probe = imx_aipstz_probe, + .driver = { + .name = "imx-aipstz", + .of_match_table = imx_aipstz_of_ids, + .pm = pm_ptr(&imx_aipstz_pm_ops), + }, +}; +module_platform_driver(imx_aipstz_of_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("IMX secure AHB to IP Slave bus (AIPSTZ) bridge driver"); +MODULE_AUTHOR("Laurentiu Mihalcea "); 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Fri, 21 Feb 2025 11:19:55 -0800 (PST) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] arm64: dts: imx8mp: convert 'aips5' to 'aipstz5' Date: Fri, 21 Feb 2025 14:19:08 -0500 Message-Id: <20250221191909.31874-5-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> References: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Laurentiu Mihalcea AIPS5 is actually AIPSTZ5 as it offers some security-related configurations. Since these configurations need to be applied before accessing any of the peripherals on the bus, it's better to make AIPSTZ5 be their parent instead of keeping AIPS5 and adding a child node for AIPSTZ5. Also, because of the security configurations, the address space of the bus has to be changed to that of the configuration registers. Finally, since AIPSTZ5 belongs to the AUDIOMIX power domain, add the missing 'power-domains' property. The domain needs to be powered on before attempting to configure the security-related registers. The DT node name is not changed to avoid potential issues with DTs in which this node is referenced. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index e0d3b8cba221..a1d9b834d2da 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1399,11 +1399,13 @@ eqos: ethernet@30bf0000 { }; }; - aips5: bus@30c00000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30c00000 0x400000>; + aips5: bus@30df0000 { + compatible = "fsl,imx8mp-aipstz", "simple-bus"; + reg = <0x30df0000 0x10000>; + power-domains = <&pgc_audio>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <0>; ranges; spba-bus@30c00000 { From patchwork Fri Feb 21 19:19:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurentiu Mihalcea X-Patchwork-Id: 13986203 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65A0C253F0E for ; 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Fri, 21 Feb 2025 11:19:57 -0800 (PST) Received: from playground.nxp.com ([82.79.237.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb9cee79fasm995276266b.129.2025.02.21.11.19.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 11:19:57 -0800 (PST) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] arm64: dts: imx8mp: make 'dsp' node depend on 'aips5' Date: Fri, 21 Feb 2025 14:19:09 -0500 Message-Id: <20250221191909.31874-6-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> References: <20250221191909.31874-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Laurentiu Mihalcea The DSP may want to access peripherals on AIPSTZ5. To do so, the security-related registers of the bridge have to be configured before the DSP is started. Enforce a dependency on AIPSTZ5 by adding the 'access-controllers' property to the 'dsp' node. Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index a1d9b834d2da..9ec51e7e6678 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2423,6 +2423,7 @@ dsp: dsp@3b6e8000 { mboxes = <&mu2 2 0>, <&mu2 2 1>, <&mu2 3 0>, <&mu2 3 1>; memory-region = <&dsp_reserved>; + access-controllers = <&aips5>; status = "disabled"; }; };