From patchwork Fri Feb 21 20:32:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13986274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B0EAC021B3 for ; Fri, 21 Feb 2025 20:36:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ZCn4OXt1rKFxWRXj+H4O8yAzMZpo+ImdOMNPkNdHGXo=; b=DeKDnfjPkeTtimEO9JNHv7ZjVO ri4lv9QKe+Nw7szufpPTo2h/XZui6q3wHbu2Ck36sCL67QKa5tF9Oj3XsZ+qwhxC/0AAjbhiAWXEE E6U5UMuNV1ho12GFwhOzp4bfRKaQ3TYm/KcTakZvytKB204xvXDQLCv3V/SCzE9j9NtPCGChWbwnS E8fOGO82qx6TwetBtfjmzG5eUCeyexEwAhuz08vjCkEgoz2KYce7q54wUTLFcNnnX9Sbx6HXaaGLz U1pltwkyHJLacRlJtbJgbEAGpb3EIfKgfGICFBIBEclUbTZaPrvmHlqh3ZW5EDvloT05mT7lBzvuS 5EOxLeKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlZka-00000006oXN-2KDI; Fri, 21 Feb 2025 20:35:56 +0000 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tlZhV-00000006nqA-20Mw for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 20:32:46 +0000 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-5ded51d31f1so4350239a12.3 for ; Fri, 21 Feb 2025 12:32:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740169964; x=1740774764; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZCn4OXt1rKFxWRXj+H4O8yAzMZpo+ImdOMNPkNdHGXo=; b=lAIklagFffU2v6eL/mcvu0t9/9oAI1qThHDErT0g3tfnbU2gKfAs1FBGT+8/IeoIy5 M1MKCLo11NxzQeqdSEgKwmuxQBxdP2g4pcrNrC69cAO0P6FENIjygsyiJuoyyHOMdDU2 2pn2fKgNCHxGEEPulFNdum1OWsfVayGrS5SYB0i1JYDMjkdQnRm3TOKnXJE42D4RtQSs 97G3wzAej1b01r2WQqKhmNAx2qPm/UmGjwFQbp7/mdq+Sss1DsSlDrAA5tNlFQKhZ/dV wVsmXmWh7ANXNSCfTaep35huGy6jWfEcMh5G7OkhAMLo7y7QPwBLqnyuUX24koqiZjxW MSlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740169964; x=1740774764; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZCn4OXt1rKFxWRXj+H4O8yAzMZpo+ImdOMNPkNdHGXo=; b=h2zD220E+0Q2twUynBwVaW4HdB2KL+24wJRfQDRBmaKI7YDwtA06NNSos35M8ewk+X E3DR49NS2kVGsc3ZuYJOht23OZ+d8oDiHBQ8sP018IEXYhxD8dRwZwHUOBHs8cn+Ijn6 VcpIsKnUq/qgcQhRy9jxqGAPueq6rbauyrpH5vUvC7vQtnXsX+zGSjL+36dMqgb2Mb+Z HxcvBCniB2SmJKioJgEzQhJ/6MPY0Lv3NYKHqGXpm6DQ7Pz/ksvTP7aHUpb7FvHYCbQb g6NCeuMnNXyVgjSvLyAKZQ1GE08O8sJrLVHogv4zeYHMfsdHUNK66v3h81pfscLpaWCZ naBQ== X-Forwarded-Encrypted: i=1; AJvYcCUYsRgZTXOkWh8kwv/ZsUNAENbcHUMahkID+B7+H+b8L/KR4JCMtGVHaCsNq+SnIRQnmdjlRYhwY/gyqB0I15Cd@lists.infradead.org X-Gm-Message-State: AOJu0YzfK+70wxGnQwZd174scPXDDlZ31t4cuAcFb6UMyoz5tptBiuyI Z5iZQZOe8NFZqy30lwvixA15llUrc7JpDjCOkES5hxHCwudTdmIX X-Gm-Gg: ASbGncsZHDDm2fV6o949m0UrUhp0Xymu79uYdJcQ9rvIskkf/ewZRRZ9WzktvjlZlTV roaBYUm1PMFyZyBuKz95NGNZ45Uic3Wp4Omq6mJminIcoHIEhWWNqKQRFH2eiiadL/audHdJ55V BIYMUqcpkIlyFPN1NiIqpwfFOLbsh6b3Emk1wz8VhIlJp2vaoRPi+3Vk2YjBneEVJ9oFeL6PnvU 1MRZBlTnKNSYxc9RoZyD5zyYGxNq6F6Cm7Gbkwsegt0LoZWfGu/wgl5tEHmMvzmBamUrg9s0dQC a3Wy4kpwl/loohM87P7PAB2cnBGUNxlBatA0RYgxqs6jyCWq3DGuyUM4YnfvaUS3v7OKkgCz X-Google-Smtp-Source: AGHT+IFgnLCCi3RErue61glfb6xjxJDZZ92IhClCzKrH/m+jqwqtiTl7Ly7vqMdOKhmkffKjBQuywQ== X-Received: by 2002:a05:6402:2347:b0:5d0:e563:4475 with SMTP id 4fb4d7f45d1cf-5e0b722c319mr4363564a12.29.1740169963795; Fri, 21 Feb 2025 12:32:43 -0800 (PST) Received: from hex.my.domain (83.8.202.192.ipv4.supernova.orange.pl. [83.8.202.192]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dece1c418bsm14653485a12.24.2025.02.21.12.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 12:32:42 -0800 (PST) From: Artur Weber Date: Fri, 21 Feb 2025 21:32:37 +0100 Subject: [PATCH v2 1/6] dt-bindings: pinctrl: Add bindings for BCM21664 pin controller MIME-Version: 1.0 Message-Id: <20250221-bcm21664-pinctrl-v2-1-7d1f0279fe16@gmail.com> References: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> In-Reply-To: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stanislav Jakubek , ~postmarketos/upstreaming@lists.sr.ht, Artur Weber X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740169959; l=5996; i=aweber.kernel@gmail.com; s=20231030; h=from:subject:message-id; bh=LrzKwcuKH+7lMFxFZZvTxrTIVtGnQjlfl1kXpaPq4+8=; b=KiP8RteV4d7KyJ/O+JBJXcIu0smkdw/YjWP7kyB9+XWKukjr4V+K0sD4Od+UEIstpKIt1gJ+Z qfw1Y0ets6BADhHuoCft0/aZod8vHdFoUefvv+lPlqX9n+Nq//+jI63 X-Developer-Key: i=aweber.kernel@gmail.com; a=ed25519; pk=RhDBfWbJEHqDibXbhNEBAnc9FMkyznGxX/hwfhL8bv8= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_123245_523417_A86CC85E X-CRM114-Status: GOOD ( 16.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device tree bindings for the pin controller included in the BCM21664 chip. The bindings are based off brcm,bcm11351-pinctrl.yaml; both chips use the same driver, but have different pins, and the BCM21664 has 6 alt modes instead of 4. Signed-off-by: Artur Weber --- Changes in v2: - Drop "property: true" declarations which had no effect with "unevaluatedProperties: false" - Define property limits for I2C pins only instead of standard pins, making the pin-specific "if" condition significantly smaller --- .../bindings/pinctrl/brcm,bcm21664-pinctrl.yaml | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm21664-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm21664-pinctrl.yaml new file mode 100644 index 0000000000000000000000000000000000000000..32b7e44e25900b9873790480b04f2feb9e54be02 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm21664-pinctrl.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm21664-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM21664 pin controller + +maintainers: + - Florian Fainelli + - Ray Jui + - Scott Branden + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: brcm,bcm21664-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '-grp[0-9]$': + type: object + unevaluatedProperties: false + + properties: + pins: + description: + Specifies the name(s) of one or more pins to be configured by + this node. + items: + enum: [ adcsyn, batrm, bsc1clk, bsc1dat, camcs0, camcs1, clk32k, + clk_cx8, dclk1, dclk4, dclkreq1, dclkreq4, dmic0clk, + dmic0dq, dsi0te, gpio00, gpio01, gpio02, gpio03, gpio04, + gpio05, gpio06, gpio07, gpio08, gpio09, gpio10, gpio11, + gpio12, gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, + gpio19, gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio32, gpio33, gpio34, gpio93, + gpio94, gps_calreq, gps_hostreq, gps_pablank, gps_tmark, + icusbdm, icusbdp, lcdcs0, lcdres, lcdscl, lcdsda, lcdte, + mdmgpio00, mdmgpio01, mdmgpio02, mdmgpio03, mdmgpio04, + mdmgpio05, mdmgpio06, mdmgpio07, mdmgpio08, mmc0ck, + mmc0cmd, mmc0dat0, mmc0dat1, mmc0dat2, mmc0dat3, mmc0dat4, + mmc0dat5, mmc0dat6, mmc0dat7, mmc0rst, mmc1ck, mmc1cmd, + mmc1dat0, mmc1dat1, mmc1dat2, mmc1dat3, mmc1dat4, + mmc1dat5, mmc1dat6, mmc1dat7, mmc1rst, pc1, pc2, pmbscclk, + pmbscdat, pmuint, resetn, rfst2g_mtsloten3g, + rtxdata2g_txdata3g1, rtxen2g_txdata3g2, rxdata3g0, + rxdata3g1, rxdata3g2, sdck, sdcmd, sddat0, sddat1, sddat2, + sddat3, simclk, simdat, simdet, simrst, spi0clk, spi0fss, + spi0rxd, spi0txd, sri_c, sri_d, sri_e, sspck, sspdi, + sspdo, sspsyn, stat1, stat2, swclktck, swdiotms, sysclken, + tdi, tdo, testmode, traceclk, tracedt00, tracedt01, + tracedt02, tracedt03, tracedt04, tracedt05, tracedt06, + tracedt07, tracedt08, tracedt09, tracedt10, tracedt11, + tracedt12, tracedt13, tracedt14, tracedt15, trstb, + txdata3g0, ubctsn, ubrtsn, ubrx, ubtx ] + + function: + description: + Specifies the pin mux selection. + enum: [ alt1, alt2, alt3, alt4, alt5, alt6 ] + + slew-rate: + description: | + Meaning depends on configured pin mux: + bsc*clk/pmbscclk or bsc*dat/pmbscdat: + 0: Standard (100 kbps) & Fast (400 kbps) mode + 1: Highspeed (3.4 Mbps) mode + Otherwise: + 0: fast slew rate + 1: normal slew rate + + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + required: + - pins + + allOf: + - $ref: pincfg-node.yaml# + + # Limitations for I2C pins + - if: + properties: + pins: + contains: + enum: [ bsc1clk, bsc1dat, gpio16, gpio17, pmbscclk, + pmbscdat ] + then: + properties: + drive-strength: false + bias-pull-down: false + input-schmitt-enable: false + input-schmitt-disable: false + + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@35004800 { + compatible = "brcm,bcm21664-pinctrl"; + reg = <0x35004800 0x7f0>; + + dev-a-active-pins { + /* group node defining 1 standard pin */ + std-grp0 { + pins = "gpio00"; + function = "alt1"; + input-schmitt-enable; + bias-disable; + slew-rate = <1>; + drive-strength = <4>; + }; + + /* group node defining 2 I2C pins */ + i2c-grp0 { + pins = "bsc1clk", "bsc1dat"; + function = "alt2"; + bias-pull-up = <720>; + input-enable; + }; + }; + }; +... From patchwork Fri Feb 21 20:32:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13986275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28F08C021B3 for ; Fri, 21 Feb 2025 20:37:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=snTumn4iv+UCdzCDJTBtnrtlkQDZvBl625j3dPFfzu0=; b=e0ac0njUbQuntTxzAov8fxSz7r m7IOAlO8NvXgYxmswcogBNsjIh7bqxFwwbnCF6FlHFv5yUafAL2fxqYlVAwOEROg3zjOMDcs1V/x9 IirBW4x+pJzysneEvPzgcBfYfQVKD7E114LWM9d1ANqMiEjtLkQD85tvBBlQrhGZgV+agLWTcbZ88 7PB+7LxzQoosQTfuMktfJ6nIZHYog3jHnC9aIyBJYZq7AUbAS0sIaqVskV579r5L4thqnxP11+oR0 0XXnQu/IkuG71CQBOUeek1FLgAC4DPM4n0cxpwG4U+sY494vsie0NqYHjCAQbDv3z0B7HIPnzUNEW l16kUk1A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlZm2-00000006os7-0pB0; Fri, 21 Feb 2025 20:37:26 +0000 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tlZhY-00000006nqc-2CHa for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 20:32:49 +0000 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5e02eba02e8so3434711a12.0 for ; Fri, 21 Feb 2025 12:32:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740169967; x=1740774767; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=snTumn4iv+UCdzCDJTBtnrtlkQDZvBl625j3dPFfzu0=; b=eleK0HGa6e3m3Zdp+IPKjSYn4U7u/q72YXV3hdY7bQAxlRbtGEkjeVfVUd/kDP0zG0 8TJXUfauBsXU/Ue1U7v7a3ZZS+74xC+rzBZr63sOY++oCRZZEXH+xksvpdkmz4Cm+KVB AGqnLWH0rIrVEyglBEEpnKkT/rSl5WdBM57Hh6b3Iicl7Vq/Czpni4KNscPeQK8eCSa9 CHQ+EIFs6OEN7UBDgSBrTdOdDIzbJ3Fz1m2yQ+kAS+FYL3CQowvQzoxaoRmytD7maRj3 mim08c9wtP3RIk6h4Z+l7oFd++Jyv0ZMTO2PmFiYByYe4dGFGD/Jv2GaSZXng0jJf/Tw iqIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740169967; x=1740774767; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=snTumn4iv+UCdzCDJTBtnrtlkQDZvBl625j3dPFfzu0=; b=A3MwUp4ywkPGGTZ52rWf9OT8llh5hJbz03NShsrfqPHLvRXy8xZETKGXPnfnAhfJ9o eAAwqNCWtvtlnfXsxD2FDBaP2aUPQjTblT+ikhB56pB7KqhO2kEqt8rNtzLbcy5ablC6 klLFGEBmxJpzjyaG4aF0oOXaZ7WFSCGp8NU/W8tvC6I7noBdKIGQ58JFTUj2o+AYD8KC 67PrurChn3nLiVT8H21hQHBj68KvZrDMDU/7SyCQiPBhU8QpcO1A52mXzKPprXjerBco 7Zqtu6MEYlZ66jfh4QOjkv1PGZCzkN658Amtr6cHbWlXXiu2jbSvXjHYNE5pYhv4h/M/ 3UlA== X-Forwarded-Encrypted: i=1; AJvYcCXDrlPJr3has+FeQTt4BRmHnacWmJCW/TXMztSU4mtr3hYD9/9sKPrxRbOk3IQ5nHq6i0faFlXKV97WjUQ/k6K8@lists.infradead.org X-Gm-Message-State: AOJu0Ywzr94a+yUQWAXXrnA7WL10pxAAjGdPcSds2dQYAafKLVA4I0L0 91RLHuPjaW8IkBmx5/PNTH0Dh3FNovsyogl8+Eh0/0qyv9bCLanD X-Gm-Gg: ASbGnctY2+yDRbbfFubmHvEXdBBGCB/sp8lvDZgCoVymd3+aXsWUCb34CI/V2GQD1VH RXPrY4gFMr1a3zY/ZxldQbCv2HCarUa7ftghzCJueE852jbkoaLsD5IxO0+aW6g/pZGBrQ3Rvjm Iv9eDUKk5FRPg+ozqZ1511vGS5Fvz0lniG9T+JID3IFfkLAvVrqmcK3l5riBQxT212z0ZkPs5Vs GBpCfNhF/WeqtsqSg9URHTjrGYT8UgXm7Sga7gAstyfa23lJvxUQYyNT5UTpGN8es1wx/VP80F/ J7oYCsXX+NB/ClSlFaIvhmMhEHSkfkwX0jl5GkqQxfl1mYbGkI5NjmLpxt2qxYOygN9KJ44D X-Google-Smtp-Source: AGHT+IFTxkMlCgyEhrq+P+QrT3EEXq7+LvpCxZ7kChZ/0Jf/Wob5JHP2c7HEHF/fdXcS44PmZFoEWw== X-Received: by 2002:a05:6402:388e:b0:5e0:818a:5f43 with SMTP id 4fb4d7f45d1cf-5e0b723ee9cmr4508702a12.30.1740169966265; Fri, 21 Feb 2025 12:32:46 -0800 (PST) Received: from hex.my.domain (83.8.202.192.ipv4.supernova.orange.pl. [83.8.202.192]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dece1c418bsm14653485a12.24.2025.02.21.12.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 12:32:45 -0800 (PST) From: Artur Weber Date: Fri, 21 Feb 2025 21:32:38 +0100 Subject: [PATCH v2 2/6] pinctrl: bcm281xx: Use "unsigned int" instead of bare "unsigned" MIME-Version: 1.0 Message-Id: <20250221-bcm21664-pinctrl-v2-2-7d1f0279fe16@gmail.com> References: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> In-Reply-To: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stanislav Jakubek , ~postmarketos/upstreaming@lists.sr.ht, Artur Weber X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740169959; l=5672; i=aweber.kernel@gmail.com; s=20231030; h=from:subject:message-id; bh=8Mipz4VrzSKXY8BbbxBUC3KcuVRejyAjsTstQRtR2iA=; b=361j678cJVEP1V9qvwiEzsITzWeF0xPxKGUFsbIxvFBTKMrsoLTjkkVw8eJ1g9mNiTBiDa2m9 swVJ5JJYpnoATWOl4KmsMUCH2hQpfUOge9WUV+wrwskkWxXCCScvD+O X-Developer-Key: i=aweber.kernel@gmail.com; a=ed25519; pk=RhDBfWbJEHqDibXbhNEBAnc9FMkyznGxX/hwfhL8bv8= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_123248_566961_02C3F649 X-CRM114-Status: GOOD ( 14.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Replace uses of bare "unsigned" with "unsigned int" to fix checkpatch warnings. No functional change. Signed-off-by: Artur Weber --- drivers/pinctrl/bcm/pinctrl-bcm281xx.c | 44 +++++++++++++++++----------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index cf6efa9c0364a1ad65885c982e7634f26d19c944..a039b490cdb8e6c41169bfd48abb371447c150a0 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -72,7 +72,7 @@ static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI; struct bcm281xx_pin_function { const char *name; const char * const *groups; - const unsigned ngroups; + const unsigned int ngroups; }; /* @@ -84,10 +84,10 @@ struct bcm281xx_pinctrl_data { /* List of all pins */ const struct pinctrl_pin_desc *pins; - const unsigned npins; + const unsigned int npins; const struct bcm281xx_pin_function *functions; - const unsigned nfunctions; + const unsigned int nfunctions; struct regmap *regmap; }; @@ -941,7 +941,7 @@ static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = { }; static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev, - unsigned pin) + unsigned int pin) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); @@ -985,7 +985,7 @@ static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) } static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) + unsigned int group) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); @@ -993,9 +993,9 @@ static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, } static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned group, + unsigned int group, const unsigned **pins, - unsigned *num_pins) + unsigned int *num_pins) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); @@ -1007,7 +1007,7 @@ static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) + unsigned int offset) { seq_printf(s, " %s", dev_name(pctldev->dev)); } @@ -1029,7 +1029,7 @@ static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev) } static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, - unsigned function) + unsigned int function) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); @@ -1037,9 +1037,9 @@ static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, } static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, - unsigned function, + unsigned int function, const char * const **groups, - unsigned * const num_groups) + unsigned int * const num_groups) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); @@ -1050,8 +1050,8 @@ static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, } static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) + unsigned int function, + unsigned int group) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); const struct bcm281xx_pin_function *f = &pdata->functions[function]; @@ -1082,7 +1082,7 @@ static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = { }; static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *config) { return -ENOTSUPP; @@ -1091,9 +1091,9 @@ static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, /* Goes through the configs and update register val/mask */ static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *configs, - unsigned num_configs, + unsigned int num_configs, u32 *val, u32 *mask) { @@ -1207,9 +1207,9 @@ static const u16 bcm281xx_pullup_map[] = { /* Goes through the configs and update register val/mask */ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *configs, - unsigned num_configs, + unsigned int num_configs, u32 *val, u32 *mask) { @@ -1277,9 +1277,9 @@ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, /* Goes through the configs and update register val/mask */ static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *configs, - unsigned num_configs, + unsigned int num_configs, u32 *val, u32 *mask) { @@ -1321,9 +1321,9 @@ static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, } static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *configs, - unsigned num_configs) + unsigned int num_configs) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); enum bcm281xx_pin_type pin_type; From patchwork Fri Feb 21 20:32:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13986276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 416E9C021B3 for ; Fri, 21 Feb 2025 20:39:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QaYFxN/ihbyHEozZR8rg46OlgPGpXgAil1GgQ0yQw30=; b=A0wxU8Ov6qCHgI+cGRdcX1HAl6 iTt2B4C52ja429fyHwNkKtk/C/pnXdnhgyxCGHYqMJdiO1Vsp0xx79JArtC6L5axaZWbim3FrZtnl 9WpqqYMEw2Hm9U+FP0kQJTJfI4F211BpwDpOxtKmsWmU018Bl6ItlIluJvPAYx810dPHFrxZUFDei qgq1BOsMSI61oJZqNeLBvCxMsabPsRvv6aU5J+FBBDIPORrBrXLv7Np3vc0y8VlpiqQPyTOpIXxcx zZYNNFM0gvnVoacYPWq8XgrIPnoiyemN4I8MyBO2Y6MU04m4w2mWDqpxwPbpOx267Z2MBrpvMWkJq PPFxcvlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlZnS-00000006p69-3dFp; Fri, 21 Feb 2025 20:38:54 +0000 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tlZhZ-00000006nqr-2h7z for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 20:32:50 +0000 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5e0939c6456so4312159a12.3 for ; Fri, 21 Feb 2025 12:32:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740169968; x=1740774768; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QaYFxN/ihbyHEozZR8rg46OlgPGpXgAil1GgQ0yQw30=; b=VbBDzX25SA0lsawf+q2Ni6FMYKZ1Xv+XscJDaZwEeWhwnnZ5kD2P/K53gEDnR7kBZy +iOMWHEHYnG538rckYmqE9swwjcuRhQ1Zld//iBJIffz33kIiVNjJeOGp0moga25oQXy VXAsqEl3YEhQWBPCa2jaEbbU5UObRyEGfQ813YttVLX5xh8gjd2LunfuqRepwQVBYP8I U9j8BUhjIIroRpWorsu92QzGe5CMzNYWdK7NsOzSj+eB/h8e5ytzMqWbCzc31ml710pg aEbWH2JFCjuqWWHqif9Q+5srHfsDcpa9dMopfWq09NwWkK6yqH+JA9QAcJYkmzmH3iZz wrpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740169968; x=1740774768; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QaYFxN/ihbyHEozZR8rg46OlgPGpXgAil1GgQ0yQw30=; b=tcHWafAeGvxZHCva3SjEUCelBwPi9sxFdZDCy0iaLijeXRFijF/Ip40lrLKqtzqPjr te2cgtCHqGmb0KvPbdRxqLjijKuZfHFa+fIweXV+/o4LRjK/uKAVQc2Tl14que5AYtPr iaTLiml5up3NAvrNMh8R9hZ0tCrd9tLE3FVBguSyXZjGvvzA+HFbVzq0dgOM7w9uFqmO DGQ/OpN+uWx8Tz9PkqVNvtdkf/opOENyjKNWnoJRZdXLcIyoU0L7VqhjARw27zm7r9X5 lBB99smHzZuXLw7m1p5/E08wVAOqVug3CgjEBqeg4s41hQenUDE7bK3AKMBE9lsOdfle TS3w== X-Forwarded-Encrypted: i=1; AJvYcCXTPYEqpiJbBb3XRH3OxMcw9Y5FqRLmjSvNeGhcXpmsM5P4WsF9vXfGyrYddCrKsCvkNF/NJxBKJnRK9H1PWmJr@lists.infradead.org X-Gm-Message-State: AOJu0YzqnLvnA3xNgfii/8SUK1p6tedo4c15a1pU/2v63cq0dVnJbHWR yPPvgjC5Ls3RZeZwpWqc2swudd3K7HrLPgNBBxgEr3PHgLjRjlFiznsfxw== X-Gm-Gg: ASbGncsy6eG+jtksU7t6nnppPkoc4PKZllsFo9Kc1SZeufPEh9XcwiusUgosxCZLPAL p9E4xFi9Fsv5AYKnJb6sQ9c2ZbhbN0mMIGheCe5vYPM2tT5Es0oA7F+3RWk1E/pyfkk86GI1Pgg R7VAmDjycB7aIO8bPI35OCVWupG7UXlGBkrcdgXHowixMDlBlbhCO+JNvBN9AIOso4s+v6KYG9s 4EDrCgp/SkbGPPWz8D2KCPuHq+h6pZVfKlnYAwuyyYkdAP1+XMDqIfz1/suzkIlI9g6HN4jjdS6 JZl5SkPBghMVeNoh+pKS3Q2eLSESY8AjnVpHkfBMRjQCSlnmEVhqeigg2rRC6+IWBcPV3rGf X-Google-Smtp-Source: AGHT+IGLEG8ESnyf5EpQSCaMOyDDp05nAfmVmcjBASTZj4YCtR7n5vuxkxAJJQElkQsuXfucOVIclg== X-Received: by 2002:a05:6402:388c:b0:5de:c9d0:6742 with SMTP id 4fb4d7f45d1cf-5e0b70df001mr3712533a12.9.1740169968116; Fri, 21 Feb 2025 12:32:48 -0800 (PST) Received: from hex.my.domain (83.8.202.192.ipv4.supernova.orange.pl. [83.8.202.192]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dece1c418bsm14653485a12.24.2025.02.21.12.32.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 12:32:47 -0800 (PST) From: Artur Weber Date: Fri, 21 Feb 2025 21:32:39 +0100 Subject: [PATCH v2 3/6] pinctrl: bcm281xx: Provide pinctrl device info as OF platform data MIME-Version: 1.0 Message-Id: <20250221-bcm21664-pinctrl-v2-3-7d1f0279fe16@gmail.com> References: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> In-Reply-To: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stanislav Jakubek , ~postmarketos/upstreaming@lists.sr.ht, Artur Weber X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740169959; l=11471; i=aweber.kernel@gmail.com; s=20231030; h=from:subject:message-id; bh=hBqTyx3cRXjMO8YcrUQl3T9HLfXnpEZnzEJ9oJSb1Dc=; b=HTFfRP+A/6+NN/h42IoNON8PlB0XejYOo4pnPd22j6rOXZSQO1Q0LXzCPcSasChSDnt09ZK1I pyXJqAmLA6ECEHuD6U8oabKGasVSyr+jO+xTqfmn3kdsaXc1SJierYT X-Developer-Key: i=aweber.kernel@gmail.com; a=ed25519; pk=RhDBfWbJEHqDibXbhNEBAnc9FMkyznGxX/hwfhL8bv8= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_123249_819440_8EB79447 X-CRM114-Status: GOOD ( 24.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce a new struct type, "bcm281xx_pinctrl_info", that holds information about the pins, pin functions and regmap config for a pin control chip. Create such a struct for the BCM218xx and pass it as device data for the OF compatible match. This is done in preparation for introducing additional chip types to the driver. Signed-off-by: Artur Weber --- Changes in v2: - Make regmap_config pointer member of bcm281xx_pinctrl_info a pointer (fixes "initializer element is not a compile-time constant" error) --- drivers/pinctrl/bcm/pinctrl-bcm281xx.c | 119 +++++++++++++++++++++------------ 1 file changed, 78 insertions(+), 41 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index a039b490cdb8e6c41169bfd48abb371447c150a0..f5aeb8a56e6ffa1204423ddc22204a4f0f4e8f84 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -76,20 +76,40 @@ struct bcm281xx_pin_function { }; /* - * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data - * @reg_base - base of pinctrl registers + * Device types (used in bcm281xx_pinctrl_desc to differentiate + * the two device types from each other) */ -struct bcm281xx_pinctrl_data { - void __iomem *reg_base; +enum bcm281xx_pinctrl_type { + BCM281XX_PINCTRL_TYPE, +}; + +/* + * bcm281xx_pinctrl_info - description of a pinctrl device supported + * by this driver, intended to be used as a provider of OF match data. + */ +struct bcm281xx_pinctrl_info { + enum bcm281xx_pinctrl_type device_type; /* List of all pins */ const struct pinctrl_pin_desc *pins; - const unsigned int npins; + unsigned int npins; const struct bcm281xx_pin_function *functions; - const unsigned int nfunctions; + unsigned int nfunctions; + + const struct regmap_config *regmap_config; +}; + +/* + * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data + * @reg_base - base of pinctrl registers + */ +struct bcm281xx_pinctrl_data { + struct device *dev; + void __iomem *reg_base; struct regmap *regmap; + const struct bcm281xx_pinctrl_info *info; }; /* @@ -933,11 +953,22 @@ static const struct bcm281xx_pin_function bcm281xx_functions[] = { BCM281XX_PIN_FUNCTION(alt4), }; -static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = { +static const struct regmap_config bcm281xx_pinctrl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = BCM281XX_PIN_VC_CAM3_SDA * 4, +}; + +static const struct bcm281xx_pinctrl_info bcm281xx_pinctrl = { + .device_type = BCM281XX_PINCTRL_TYPE, + .pins = bcm281xx_pinctrl_pins, .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins), .functions = bcm281xx_functions, .nfunctions = ARRAY_SIZE(bcm281xx_functions), + + .regmap_config = &bcm281xx_pinctrl_regmap_config, }; static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev, @@ -945,10 +976,10 @@ static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev, { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - if (pin >= pdata->npins) + if (pin >= pdata->info->npins) return BCM281XX_PIN_TYPE_UNKNOWN; - return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data); + return *(enum bcm281xx_pin_type *)(pdata->info->pins[pin].drv_data); } #define BCM281XX_PIN_SHIFT(type, param) \ @@ -970,18 +1001,11 @@ static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask, *reg_mask |= param_mask; } -static const struct regmap_config bcm281xx_pinctrl_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = BCM281XX_PIN_VC_CAM3_SDA * 4, -}; - static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - return pdata->npins; + return pdata->info->npins; } static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, @@ -989,7 +1013,7 @@ static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - return pdata->pins[group].name; + return pdata->info->pins[group].name; } static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, @@ -999,7 +1023,7 @@ static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - *pins = &pdata->pins[group].number; + *pins = &pdata->info->pins[group].number; *num_pins = 1; return 0; @@ -1025,7 +1049,7 @@ static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - return pdata->nfunctions; + return pdata->info->nfunctions; } static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, @@ -1033,7 +1057,7 @@ static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - return pdata->functions[function].name; + return pdata->info->functions[function].name; } static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, @@ -1043,8 +1067,8 @@ static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - *groups = pdata->functions[function].groups; - *num_groups = pdata->functions[function].ngroups; + *groups = pdata->info->functions[function].groups; + *num_groups = pdata->info->functions[function].ngroups; return 0; } @@ -1054,14 +1078,15 @@ static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, unsigned int group) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - const struct bcm281xx_pin_function *f = &pdata->functions[function]; - u32 offset = 4 * pdata->pins[group].number; + const struct bcm281xx_pin_function *f = &pdata->info->functions[function]; + unsigned int pin = pdata->info->pins[group].number; + u32 offset = 4 * pin; int rc = 0; dev_dbg(pctldev->dev, "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n", - __func__, f->name, function, pdata->pins[group].name, - pdata->pins[group].number, offset); + __func__, f->name, function, pdata->info->pins[group].name, + pin, offset); rc = regmap_update_bits(pdata->regmap, offset, BCM281XX_PIN_REG_F_SEL_MASK, @@ -1069,7 +1094,7 @@ static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, if (rc) dev_err(pctldev->dev, "Error updating register for pin %s (%d).\n", - pdata->pins[group].name, pdata->pins[group].number); + pdata->info->pins[group].name, pin); return rc; } @@ -1168,7 +1193,7 @@ static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev, "Invalid Drive Strength value (%d) for " "pin %s (%d). Valid values are " "(2..16) mA, even numbers only.\n", - arg, pdata->pins[pin].name, pin); + arg, pdata->info->pins[pin].name, pin); return -EINVAL; } bcm281xx_pin_update(val, mask, (arg/2)-1, @@ -1179,7 +1204,7 @@ static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev, default: dev_err(pctldev->dev, "Unrecognized pin config %d for pin %s (%d).\n", - param, pdata->pins[pin].name, pin); + param, pdata->info->pins[pin].name, pin); return -EINVAL; } /* switch config */ @@ -1233,7 +1258,7 @@ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, "Invalid pull-up value (%d) for pin %s " "(%d). Valid values are 568, 720, 831, " "1080, 1200, 1800, 2700 Ohms.\n", - arg, pdata->pins[pin].name, pin); + arg, pdata->info->pins[pin].name, pin); return -EINVAL; } @@ -1266,7 +1291,7 @@ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, default: dev_err(pctldev->dev, "Unrecognized pin config %d for pin %s (%d).\n", - param, pdata->pins[pin].name, pin); + param, pdata->info->pins[pin].name, pin); return -EINVAL; } /* switch config */ @@ -1311,7 +1336,7 @@ static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, default: dev_err(pctldev->dev, "Unrecognized pin config %d for pin %s (%d).\n", - param, pdata->pins[pin].name, pin); + param, pdata->info->pins[pin].name, pin); return -EINVAL; } /* switch config */ @@ -1354,7 +1379,7 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, default: dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n", - pdata->pins[pin].name, pin); + pdata->info->pins[pin].name, pin); return -EINVAL; } /* switch pin type */ @@ -1364,13 +1389,13 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", - __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); + __func__, pdata->info->pins[pin].name, pin, cfg_val, cfg_mask); rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); if (rc) { dev_err(pctldev->dev, "Error updating register for pin %s (%d).\n", - pdata->pins[pin].name, pin); + pdata->info->pins[pin].name, pin); return rc; } @@ -1390,11 +1415,23 @@ static struct pinctrl_desc bcm281xx_pinctrl_desc = { .owner = THIS_MODULE, }; +static struct bcm281xx_pinctrl_data bcm281xx_pinctrl_pdata; + static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) { - struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl; + struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl_pdata; struct pinctrl_dev *pctl; + /* Set device pointer in platform data */ + pdata->dev = &pdev->dev; + + /* Get the data to use from OF match */ + pdata->info = of_device_get_match_data(&pdev->dev); + if (!pdata->info) { + dev_err(&pdev->dev, "Failed to get data from OF match\n"); + return -ENODEV; + } + /* So far We can assume there is only 1 bank of registers */ pdata->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pdata->reg_base)) { @@ -1404,15 +1441,15 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) /* Initialize the dynamic part of pinctrl_desc */ pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base, - &bcm281xx_pinctrl_regmap_config); + pdata->info->regmap_config); if (IS_ERR(pdata->regmap)) { dev_err(&pdev->dev, "Regmap MMIO init failed.\n"); return -ENODEV; } bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev); - bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins; - bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins; + bcm281xx_pinctrl_desc.pins = pdata->info->pins; + bcm281xx_pinctrl_desc.npins = pdata->info->npins; pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata); if (IS_ERR(pctl)) { @@ -1426,7 +1463,7 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id bcm281xx_pinctrl_of_match[] = { - { .compatible = "brcm,bcm11351-pinctrl", }, + { .compatible = "brcm,bcm11351-pinctrl", .data = &bcm281xx_pinctrl }, { }, }; From patchwork Fri Feb 21 20:32:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13986277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32C1AC021B3 for ; Fri, 21 Feb 2025 20:40:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Qapm5KbcpgJuKYDxZVNyRTdYieG1bG67KMxvYqeWQwo=; b=sMUhSxJKgxIxD0r73ilIXZqShn fj+MkG4Hr72jqNjgzsinB4fu8nruNTOXRs0B8zcQwyQNGRlnNUBNj1dHS7dGnezuMpUFEnsjrTKW0 JuzpeNBDr3OlVnasoDhmdd5s9GL0yjyZ5aQtoC0ujayTRSdb0meWEr1IOZ9m75gT5KpbNKVBdy1wM GfrqDDDgG0q837e/70nYNYWQ/uviDjZawkfR+GPRmwyMNwNMTcdtFeQln1L4TXe9yPlJeCPkwZRUm Tebbd80DtlnMY7P3UX+9fLPxBIEvKl9DhgKHJGnPN4DhO8BzLtQcTgq8tcIVYhNQywZnXJybV2G8/ N+gHVt0g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlZou-00000006pJ8-27da; Fri, 21 Feb 2025 20:40:24 +0000 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tlZhb-00000006nrh-42v2 for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 20:32:53 +0000 Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-5e05717755bso3729438a12.0 for ; Fri, 21 Feb 2025 12:32:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740169970; x=1740774770; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Qapm5KbcpgJuKYDxZVNyRTdYieG1bG67KMxvYqeWQwo=; b=dTd9TRu8LSx3gLvcAuk4ZIAmtfNqjfVrGudRddTEPVJN+5MDpEEQN4WsGHi6DNECl1 Iajmngm4xh4yaxjsBX+gajAsnvFaZGGwGps3vNSSbh1Q/NvcdrGg2X3r0UX5GdIsGkQP d39Z7+lS2PiIamLtxKqYS3leBRlJ0Pi4T72CGPjjK93zmepRx/kSNnWuUQ5Kxm/PUzpK N2gcUXiG+mRCsvN4qW3Kw7053/37W9920dMqVsCnM2+b28w11jrY8uGuvkBmVOTD5y10 ExzVzLWP9lavRV3fDQYpxDHUfoHOUHaxfRY3Yxli+t3bmf5HWkd4DgTcVGQdm/SAXnsd sNNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740169970; x=1740774770; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qapm5KbcpgJuKYDxZVNyRTdYieG1bG67KMxvYqeWQwo=; b=v1y/ylnwPEf3sWaWfBPUbyGm1mrLENwyRWWaLjh4Vybn4n7dK7zmt1fS07O6bEYhhl f3RJxGAZxeU3XOmeAwwWmEKNeB8nvPQ3kuM3Ad3gnMMZ/nO9Jf8PcJDMst7LTBIs2HVS G2pZLnq/9PzO4sPmHtaB2v8q+0KiXttRzBctwde4bzarT+lO2Q3y/t6g7T26xNxP/J/5 breBodvNPy9Y0bfQhBlU5Piyllz+mZrqBSaL1L5acAcw4HFM3HnXgxps1cRvOC+Rx/a0 QgbbigbMzWH49aeBVfAxls6OFeHFXsBdIGt9wl3VcSQVHCvmzpwW6MVEapFpkmqbUHYJ 6o7A== X-Forwarded-Encrypted: i=1; AJvYcCV2zY05QOHfBUSryOiXiFhF+RBsABg20PQPVY0KgBC36tZ7npQ4S/jf7FHJrkW/Sp+GOKbWGCQBVHcC+1aFSa6b@lists.infradead.org X-Gm-Message-State: AOJu0YyLseoxj7RIC8YMWHnS8i6zsmcAms4bhnpBJwgI3TUkq56J+2SS e3YteBpdIuGk0H5AP4umeA45aN9pxo1yKgJCFXczwCQ0eEOlKvcp X-Gm-Gg: ASbGncuQplHoXNtMDmW1eHOL6lklVTmX7K9LgS0GllLz2XRcM2gx4LgKV7rkh7P8meH PL4A4M+CuAmNJylRiK9vGYkSuioU5dNa/7NLMW8kgzZJGFbskRgC8urAwzTJCeCooVRSrNXWQzs tUKEp0miGHJ65ggOBjjEym+vmdm0qwggYLCe8qwO1z0dpNkNzD9lOpyHp1fh1IlnLmPXGTbjEhn ETqDLqxwLQf2f0Lh5XZT1HznO8xS8RWeLf2qTf46v6a0xzm/OA96CQNeYsYB+SicfHsQfcePMng rqa0UleFkEcvASe/iIHnqE+cmd/GCAsD9zrRKpe35Hdfc1q+wBRgC28z93Z8BGSGlkTOFtFB X-Google-Smtp-Source: AGHT+IGw18yvpAN+b2fyDPjnLOLxKCVj6iXqpbs+434SmwTaCo4L+9qpV63b3OZdwbs+PWd8T6vUyw== X-Received: by 2002:a05:6402:3889:b0:5de:de2c:ea90 with SMTP id 4fb4d7f45d1cf-5e0b70e88c4mr4319699a12.11.1740169970191; Fri, 21 Feb 2025 12:32:50 -0800 (PST) Received: from hex.my.domain (83.8.202.192.ipv4.supernova.orange.pl. [83.8.202.192]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dece1c418bsm14653485a12.24.2025.02.21.12.32.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 12:32:49 -0800 (PST) From: Artur Weber Date: Fri, 21 Feb 2025 21:32:40 +0100 Subject: [PATCH v2 4/6] pinctrl: bcm281xx: Add support for BCM21664 pinmux MIME-Version: 1.0 Message-Id: <20250221-bcm21664-pinctrl-v2-4-7d1f0279fe16@gmail.com> References: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> In-Reply-To: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stanislav Jakubek , ~postmarketos/upstreaming@lists.sr.ht, Artur Weber X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740169959; l=27811; i=aweber.kernel@gmail.com; s=20231030; h=from:subject:message-id; bh=y4g7BxjbqcEdlTVgDTZPi6zawvXAGx09UYPJUltXi44=; b=wMTy88Ptpzo2qA4faqq+T9/y8rnkTEAHzSSVosJN/vdzEd1bnB2ert94hNc4d5vzUoFjcOUos TmD+4+7Br9iDwn9XmfZW9isgjs/lk8lYDFrPHJ8V7dbek4C+Fb3NfH5 X-Developer-Key: i=aweber.kernel@gmail.com; a=ed25519; pk=RhDBfWbJEHqDibXbhNEBAnc9FMkyznGxX/hwfhL8bv8= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_123252_112399_70F658FF X-CRM114-Status: GOOD ( 15.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org BCM21664 is another chip from the Kona line of Broadcom SoCs, and its pinmux shares a lot of similarities with the BCM281xx pinmux. Add support for the BCM21664 pinmux controller to the BCM281xx driver. This also enables pinmux support for the BCM23550, which has an identical pinmux config to the BCM21664 (hence they can share a single compatible, brcm,bcm21664-pinctrl). Signed-off-by: Artur Weber --- Changes in v2: - Adapt to regmap_config member of bcm281xx_pinctrl_info being a pointer now --- drivers/pinctrl/bcm/pinctrl-bcm281xx.c | 690 ++++++++++++++++++++++++++++++++- 1 file changed, 688 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index f5aeb8a56e6ffa1204423ddc22204a4f0f4e8f84..7c8f8bd7da129daff1c1312fe74abf2986b83fb9 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -52,6 +52,12 @@ #define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010 #define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4 +/* BCM21664 access lock registers */ +#define BCM21664_WR_ACCESS_OFFSET 0x07F0 +#define BCM21664_WR_ACCESS_PASSWORD 0xA5A501 +#define BCM21664_ACCESS_LOCK_OFFSET(lock) (0x0780 + (lock * 4)) +#define BCM21664_ACCESS_LOCK_COUNT 5 + /* * bcm281xx_pin_type - types of pin register */ @@ -81,6 +87,7 @@ struct bcm281xx_pin_function { */ enum bcm281xx_pinctrl_type { BCM281XX_PINCTRL_TYPE, + BCM21664_PINCTRL_TYPE, }; /* @@ -971,6 +978,571 @@ static const struct bcm281xx_pinctrl_info bcm281xx_pinctrl = { .regmap_config = &bcm281xx_pinctrl_regmap_config, }; +/* BCM21664 data */ +#define BCM21664_PIN_ADCSYN 0 +#define BCM21664_PIN_BATRM 1 +#define BCM21664_PIN_BSC1CLK 2 +#define BCM21664_PIN_BSC1DAT 3 +#define BCM21664_PIN_CAMCS0 4 +#define BCM21664_PIN_CAMCS1 5 +#define BCM21664_PIN_CLK32K 6 +#define BCM21664_PIN_CLK_CX8 7 +#define BCM21664_PIN_DCLK1 8 +#define BCM21664_PIN_DCLK4 9 +#define BCM21664_PIN_DCLKREQ1 10 +#define BCM21664_PIN_DCLKREQ4 11 +#define BCM21664_PIN_DMIC0CLK 12 +#define BCM21664_PIN_DMIC0DQ 13 +#define BCM21664_PIN_DSI0TE 14 +#define BCM21664_PIN_GPIO00 15 +#define BCM21664_PIN_GPIO01 16 +#define BCM21664_PIN_GPIO02 17 +#define BCM21664_PIN_GPIO03 18 +#define BCM21664_PIN_GPIO04 19 +#define BCM21664_PIN_GPIO05 20 +#define BCM21664_PIN_GPIO06 21 +#define BCM21664_PIN_GPIO07 22 +#define BCM21664_PIN_GPIO08 23 +#define BCM21664_PIN_GPIO09 24 +#define BCM21664_PIN_GPIO10 25 +#define BCM21664_PIN_GPIO11 26 +#define BCM21664_PIN_GPIO12 27 +#define BCM21664_PIN_GPIO13 28 +#define BCM21664_PIN_GPIO14 29 +#define BCM21664_PIN_GPIO15 30 +#define BCM21664_PIN_GPIO16 31 +#define BCM21664_PIN_GPIO17 32 +#define BCM21664_PIN_GPIO18 33 +#define BCM21664_PIN_GPIO19 34 +#define BCM21664_PIN_GPIO20 35 +#define BCM21664_PIN_GPIO21 36 +#define BCM21664_PIN_GPIO22 37 +#define BCM21664_PIN_GPIO23 38 +#define BCM21664_PIN_GPIO24 39 +#define BCM21664_PIN_GPIO25 40 +#define BCM21664_PIN_GPIO26 41 +#define BCM21664_PIN_GPIO27 42 +#define BCM21664_PIN_GPIO28 43 +#define BCM21664_PIN_GPIO32 44 +#define BCM21664_PIN_GPIO33 45 +#define BCM21664_PIN_GPIO34 46 +#define BCM21664_PIN_GPS_CALREQ 47 +#define BCM21664_PIN_GPS_HOSTREQ 48 +#define BCM21664_PIN_GPS_PABLANK 49 +#define BCM21664_PIN_GPS_TMARK 50 +#define BCM21664_PIN_ICUSBDM 51 +#define BCM21664_PIN_ICUSBDP 52 +#define BCM21664_PIN_LCDCS0 53 +#define BCM21664_PIN_LCDRES 54 +#define BCM21664_PIN_LCDSCL 55 +#define BCM21664_PIN_LCDSDA 56 +#define BCM21664_PIN_LCDTE 57 +#define BCM21664_PIN_MDMGPIO00 58 +#define BCM21664_PIN_MDMGPIO01 59 +#define BCM21664_PIN_MDMGPIO02 60 +#define BCM21664_PIN_MDMGPIO03 61 +#define BCM21664_PIN_MDMGPIO04 62 +#define BCM21664_PIN_MDMGPIO05 63 +#define BCM21664_PIN_MDMGPIO06 64 +#define BCM21664_PIN_MDMGPIO07 65 +#define BCM21664_PIN_MDMGPIO08 66 +#define BCM21664_PIN_MMC0CK 67 +#define BCM21664_PIN_MMC0CMD 68 +#define BCM21664_PIN_MMC0DAT0 69 +#define BCM21664_PIN_MMC0DAT1 70 +#define BCM21664_PIN_MMC0DAT2 71 +#define BCM21664_PIN_MMC0DAT3 72 +#define BCM21664_PIN_MMC0DAT4 73 +#define BCM21664_PIN_MMC0DAT5 74 +#define BCM21664_PIN_MMC0DAT6 75 +#define BCM21664_PIN_MMC0DAT7 76 +#define BCM21664_PIN_MMC0RST 77 +#define BCM21664_PIN_MMC1CK 78 +#define BCM21664_PIN_MMC1CMD 79 +#define BCM21664_PIN_MMC1DAT0 80 +#define BCM21664_PIN_MMC1DAT1 81 +#define BCM21664_PIN_MMC1DAT2 82 +#define BCM21664_PIN_MMC1DAT3 83 +#define BCM21664_PIN_MMC1DAT4 84 +#define BCM21664_PIN_MMC1DAT5 85 +#define BCM21664_PIN_MMC1DAT6 86 +#define BCM21664_PIN_MMC1DAT7 87 +#define BCM21664_PIN_MMC1RST 88 +#define BCM21664_PIN_PC1 89 +#define BCM21664_PIN_PC2 90 +#define BCM21664_PIN_PMBSCCLK 91 +#define BCM21664_PIN_PMBSCDAT 92 +#define BCM21664_PIN_PMUINT 93 +#define BCM21664_PIN_RESETN 94 +#define BCM21664_PIN_RFST2G_MTSLOTEN3G 95 +#define BCM21664_PIN_RTXDATA2G_TXDATA3G1 96 +#define BCM21664_PIN_RTXEN2G_TXDATA3G2 97 +#define BCM21664_PIN_RXDATA3G0 98 +#define BCM21664_PIN_RXDATA3G1 99 +#define BCM21664_PIN_RXDATA3G2 100 +#define BCM21664_PIN_SDCK 101 +#define BCM21664_PIN_SDCMD 102 +#define BCM21664_PIN_SDDAT0 103 +#define BCM21664_PIN_SDDAT1 104 +#define BCM21664_PIN_SDDAT2 105 +#define BCM21664_PIN_SDDAT3 106 +#define BCM21664_PIN_SIMCLK 107 +#define BCM21664_PIN_SIMDAT 108 +#define BCM21664_PIN_SIMDET 109 +#define BCM21664_PIN_SIMRST 110 +#define BCM21664_PIN_GPIO93 111 +#define BCM21664_PIN_GPIO94 112 +#define BCM21664_PIN_SPI0CLK 113 +#define BCM21664_PIN_SPI0FSS 114 +#define BCM21664_PIN_SPI0RXD 115 +#define BCM21664_PIN_SPI0TXD 116 +#define BCM21664_PIN_SRI_C 117 +#define BCM21664_PIN_SRI_D 118 +#define BCM21664_PIN_SRI_E 119 +#define BCM21664_PIN_SSPCK 120 +#define BCM21664_PIN_SSPDI 121 +#define BCM21664_PIN_SSPDO 122 +#define BCM21664_PIN_SSPSYN 123 +#define BCM21664_PIN_STAT1 124 +#define BCM21664_PIN_STAT2 125 +#define BCM21664_PIN_SWCLKTCK 126 +#define BCM21664_PIN_SWDIOTMS 127 +#define BCM21664_PIN_SYSCLKEN 128 +#define BCM21664_PIN_TDI 129 +#define BCM21664_PIN_TDO 130 +#define BCM21664_PIN_TESTMODE 131 +#define BCM21664_PIN_TRACECLK 132 +#define BCM21664_PIN_TRACEDT00 133 +#define BCM21664_PIN_TRACEDT01 134 +#define BCM21664_PIN_TRACEDT02 135 +#define BCM21664_PIN_TRACEDT03 136 +#define BCM21664_PIN_TRACEDT04 137 +#define BCM21664_PIN_TRACEDT05 138 +#define BCM21664_PIN_TRACEDT06 139 +#define BCM21664_PIN_TRACEDT07 140 +#define BCM21664_PIN_TRSTB 141 +#define BCM21664_PIN_TXDATA3G0 142 +#define BCM21664_PIN_UBCTSN 143 +#define BCM21664_PIN_UBRTSN 144 +#define BCM21664_PIN_UBRX 145 +#define BCM21664_PIN_UBTX 146 +#define BCM21664_PIN_TRACEDT08 147 +#define BCM21664_PIN_TRACEDT09 148 +#define BCM21664_PIN_TRACEDT10 149 +#define BCM21664_PIN_TRACEDT11 150 +#define BCM21664_PIN_TRACEDT12 151 +#define BCM21664_PIN_TRACEDT13 152 +#define BCM21664_PIN_TRACEDT14 153 +#define BCM21664_PIN_TRACEDT15 154 + +static const struct pinctrl_pin_desc bcm21664_pinctrl_pins[] = { + BCM281XX_PIN_DESC(BCM21664_PIN_ADCSYN, "adcsyn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_BATRM, "batrm", std), + BCM281XX_PIN_DESC(BCM21664_PIN_BSC1CLK, "bsc1clk", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_BSC1DAT, "bsc1dat", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_CAMCS0, "camcs0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_CAMCS1, "camcs1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_CLK32K, "clk32k", std), + BCM281XX_PIN_DESC(BCM21664_PIN_CLK_CX8, "clk_cx8", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DCLK1, "dclk1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DCLK4, "dclk4", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DCLKREQ1, "dclkreq1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DCLKREQ4, "dclkreq4", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DMIC0CLK, "dmic0clk", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DMIC0DQ, "dmic0dq", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DSI0TE, "dsi0te", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO00, "gpio00", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO01, "gpio01", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO02, "gpio02", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO03, "gpio03", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO04, "gpio04", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO05, "gpio05", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO06, "gpio06", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO07, "gpio07", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO08, "gpio08", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO09, "gpio09", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO10, "gpio10", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO11, "gpio11", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO12, "gpio12", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO13, "gpio13", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO14, "gpio14", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO15, "gpio15", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO16, "gpio16", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO17, "gpio17", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO18, "gpio18", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO19, "gpio19", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO20, "gpio20", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO21, "gpio21", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO22, "gpio22", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO23, "gpio23", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO24, "gpio24", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO25, "gpio25", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO26, "gpio26", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO27, "gpio27", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO28, "gpio28", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO32, "gpio32", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO33, "gpio33", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO34, "gpio34", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPS_CALREQ, "gps_calreq", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPS_HOSTREQ, "gps_hostreq", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPS_PABLANK, "gps_pablank", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPS_TMARK, "gps_tmark", std), + BCM281XX_PIN_DESC(BCM21664_PIN_ICUSBDM, "icusbdm", std), + BCM281XX_PIN_DESC(BCM21664_PIN_ICUSBDP, "icusbdp", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDCS0, "lcdcs0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDRES, "lcdres", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDSCL, "lcdscl", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDSDA, "lcdsda", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDTE, "lcdte", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO00, "mdmgpio00", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO01, "mdmgpio01", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO02, "mdmgpio02", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO03, "mdmgpio03", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO04, "mdmgpio04", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO05, "mdmgpio05", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO06, "mdmgpio06", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO07, "mdmgpio07", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO08, "mdmgpio08", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0CK, "mmc0ck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0CMD, "mmc0cmd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT0, "mmc0dat0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT1, "mmc0dat1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT2, "mmc0dat2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT3, "mmc0dat3", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT4, "mmc0dat4", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT5, "mmc0dat5", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT6, "mmc0dat6", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT7, "mmc0dat7", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0RST, "mmc0rst", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1CK, "mmc1ck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1CMD, "mmc1cmd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT0, "mmc1dat0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT1, "mmc1dat1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT2, "mmc1dat2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT3, "mmc1dat3", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT4, "mmc1dat4", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT5, "mmc1dat5", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT6, "mmc1dat6", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT7, "mmc1dat7", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1RST, "mmc1rst", std), + BCM281XX_PIN_DESC(BCM21664_PIN_PC1, "pc1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_PC2, "pc2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_PMBSCCLK, "pmbscclk", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_PMBSCDAT, "pmbscdat", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_PMUINT, "pmuint", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RESETN, "resetn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RTXDATA2G_TXDATA3G1, "rtxdata2g_txdata3g1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RXDATA3G0, "rxdata3g0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RXDATA3G1, "rxdata3g1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RXDATA3G2, "rxdata3g2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDCK, "sdck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDCMD, "sdcmd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT0, "sddat0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT1, "sddat1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT2, "sddat2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT3, "sddat3", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SIMCLK, "simclk", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SIMDAT, "simdat", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SIMDET, "simdet", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SIMRST, "simrst", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO93, "gpio93", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO94, "gpio94", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SPI0CLK, "spi0clk", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SPI0FSS, "spi0fss", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SPI0RXD, "spi0rxd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SPI0TXD, "spi0txd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SRI_C, "sri_c", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SRI_D, "sri_d", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SRI_E, "sri_e", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SSPCK, "sspck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SSPDI, "sspdi", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SSPDO, "sspdo", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SSPSYN, "sspsyn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_STAT1, "stat1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_STAT2, "stat2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SWCLKTCK, "swclktck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SWDIOTMS, "swdiotms", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SYSCLKEN, "sysclken", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TDI, "tdi", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TDO, "tdo", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TESTMODE, "testmode", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACECLK, "traceclk", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT00, "tracedt00", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT01, "tracedt01", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT02, "tracedt02", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT03, "tracedt03", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT04, "tracedt04", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT05, "tracedt05", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT06, "tracedt06", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT07, "tracedt07", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRSTB, "trstb", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TXDATA3G0, "txdata3g0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_UBCTSN, "ubctsn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_UBRTSN, "ubrtsn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_UBRX, "ubrx", std), + BCM281XX_PIN_DESC(BCM21664_PIN_UBTX, "ubtx", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT08, "tracedt08", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT09, "tracedt09", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT10, "tracedt10", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT11, "tracedt11", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT12, "tracedt12", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT13, "tracedt13", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT14, "tracedt14", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT15, "tracedt15", std), +}; + +static const char * const bcm21664_alt_groups[] = { + "adcsyn", + "batrm", + "bsc1clk", + "bsc1dat", + "camcs0", + "camcs1", + "clk32k", + "clk_cx8", + "dclk1", + "dclk4", + "dclkreq1", + "dclkreq4", + "dmic0clk", + "dmic0dq", + "dsi0te", + "gpio00", + "gpio01", + "gpio02", + "gpio03", + "gpio04", + "gpio05", + "gpio06", + "gpio07", + "gpio08", + "gpio09", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", + "gpio16", + "gpio17", + "gpio18", + "gpio19", + "gpio20", + "gpio21", + "gpio22", + "gpio23", + "gpio24", + "gpio25", + "gpio26", + "gpio27", + "gpio28", + "gpio32", + "gpio33", + "gpio34", + "gps_calreq", + "gps_hostreq", + "gps_pablank", + "gps_tmark", + "icusbdm", + "icusbdp", + "lcdcs0", + "lcdres", + "lcdscl", + "lcdsda", + "lcdte", + "mdmgpio00", + "mdmgpio01", + "mdmgpio02", + "mdmgpio03", + "mdmgpio04", + "mdmgpio05", + "mdmgpio06", + "mdmgpio07", + "mdmgpio08", + "mmc0ck", + "mmc0cmd", + "mmc0dat0", + "mmc0dat1", + "mmc0dat2", + "mmc0dat3", + "mmc0dat4", + "mmc0dat5", + "mmc0dat6", + "mmc0dat7", + "mmc0rst", + "mmc1ck", + "mmc1cmd", + "mmc1dat0", + "mmc1dat1", + "mmc1dat2", + "mmc1dat3", + "mmc1dat4", + "mmc1dat5", + "mmc1dat6", + "mmc1dat7", + "mmc1rst", + "pc1", + "pc2", + "pmbscclk", + "pmbscdat", + "pmuint", + "resetn", + "rfst2g_mtsloten3g", + "rtxdata2g_txdata3g1", + "rtxen2g_txdata3g2", + "rxdata3g0", + "rxdata3g1", + "rxdata3g2", + "sdck", + "sdcmd", + "sddat0", + "sddat1", + "sddat2", + "sddat3", + "simclk", + "simdat", + "simdet", + "simrst", + "gpio93", + "gpio94", + "spi0clk", + "spi0fss", + "spi0rxd", + "spi0txd", + "sri_c", + "sri_d", + "sri_e", + "sspck", + "sspdi", + "sspdo", + "sspsyn", + "stat1", + "stat2", + "swclktck", + "swdiotms", + "sysclken", + "tdi", + "tdo", + "testmode", + "traceclk", + "tracedt00", + "tracedt01", + "tracedt02", + "tracedt03", + "tracedt04", + "tracedt05", + "tracedt06", + "tracedt07", + "trstb", + "txdata3g0", + "ubctsn", + "ubrtsn", + "ubrx", + "ubtx", + "tracedt08", + "tracedt09", + "tracedt10", + "tracedt11", + "tracedt12", + "tracedt13", + "tracedt14", + "tracedt15", +}; + +#define BCM21664_PIN_FUNCTION(fcn_name) \ +{ \ + .name = #fcn_name, \ + .groups = bcm21664_alt_groups, \ + .ngroups = ARRAY_SIZE(bcm21664_alt_groups), \ +} + +static const struct bcm281xx_pin_function bcm21664_functions[] = { + BCM21664_PIN_FUNCTION(alt1), + BCM21664_PIN_FUNCTION(alt2), + BCM21664_PIN_FUNCTION(alt3), + BCM21664_PIN_FUNCTION(alt4), + BCM21664_PIN_FUNCTION(alt5), + BCM21664_PIN_FUNCTION(alt6), +}; + +static const struct regmap_config bcm21664_pinctrl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = BCM21664_WR_ACCESS_OFFSET, +}; + +static const struct bcm281xx_pinctrl_info bcm21664_pinctrl = { + .device_type = BCM21664_PINCTRL_TYPE, + + .pins = bcm21664_pinctrl_pins, + .npins = ARRAY_SIZE(bcm21664_pinctrl_pins), + .functions = bcm21664_functions, + .nfunctions = ARRAY_SIZE(bcm21664_functions), + + .regmap_config = &bcm21664_pinctrl_regmap_config, +}; + +/* BCM21664 pinctrl access lock handlers */ +static int bcm21664_pinctrl_lock_all(struct bcm281xx_pinctrl_data *pdata) +{ + int i, rc; + + for (i = 0; i < BCM21664_ACCESS_LOCK_COUNT; i++) { + rc = regmap_write(pdata->regmap, BCM21664_WR_ACCESS_OFFSET, + BCM21664_WR_ACCESS_PASSWORD); + if (rc) { + dev_err(pdata->dev, "Failed to enable write access: %d\n", + rc); + return rc; + } + regmap_write(pdata->regmap, BCM21664_ACCESS_LOCK_OFFSET(i), + 0xffffffff); + if (rc) { + dev_err(pdata->dev, "Failed to write access lock: %d\n", + rc); + return rc; + } + } + + return 0; +} + +static int bcm21664_pinctrl_set_pin_lock(struct bcm281xx_pinctrl_data *pdata, + unsigned int pin, bool lock) +{ + unsigned int access_lock = pin / 32; + int rc; + + dev_dbg(pdata->dev, + "%s(): %s pin %s (%d)\n", + __func__, lock ? "Lock" : "Unlock", pdata->info->pins[pin].name, + pin); + + rc = regmap_write(pdata->regmap, BCM21664_WR_ACCESS_OFFSET, + BCM21664_WR_ACCESS_PASSWORD); + if (rc) { + dev_err(pdata->dev, "Failed to enable write access: %d\n", + rc); + return rc; + } + + rc = regmap_update_bits(pdata->regmap, + BCM21664_ACCESS_LOCK_OFFSET(access_lock), + BIT(pin % 32), + (int)lock << (pin % 32)); + + if (rc) { + dev_err(pdata->dev, "Failed to %s pin: %d\n", + lock ? "lock" : "unlock", rc); + return rc; + } + + return 0; +} + static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev, unsigned int pin) { @@ -1079,6 +1651,7 @@ static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); const struct bcm281xx_pin_function *f = &pdata->info->functions[function]; + enum bcm281xx_pinctrl_type device_type = pdata->info->device_type; unsigned int pin = pdata->info->pins[group].number; u32 offset = 4 * pin; int rc = 0; @@ -1088,6 +1661,14 @@ static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, __func__, f->name, function, pdata->info->pins[group].name, pin, offset); + if (device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, false); + if (rc) { + /* Error is printed in bcm21664_pinctrl_set_pin_lock */ + return rc; + } + } + rc = regmap_update_bits(pdata->regmap, offset, BCM281XX_PIN_REG_F_SEL_MASK, function << BCM281XX_PIN_REG_F_SEL_SHIFT); @@ -1096,6 +1677,14 @@ static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, "Error updating register for pin %s (%d).\n", pdata->info->pins[group].name, pin); + if (device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, true); + if (rc) { + /* Error is printed in bcm21664_pinctrl_set_pin_lock */ + return rc; + } + } + return rc; } @@ -1300,6 +1889,68 @@ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, return 0; } +/* Goes through the configs and update register val/mask */ +static int bcm21664_i2c_pin_update(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs, + u32 *val, + u32 *mask) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i; + enum pin_config_param param; + u32 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + /* + * BCM21664 I2C pins use the same config bits as standard pins, + * but only pull up/none, slew rate and input enable/disable + * options are supported. + */ + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + bcm281xx_pin_update(val, mask, 1, + BCM281XX_PIN_SHIFT(STD, PULL_UP), + BCM281XX_PIN_MASK(STD, PULL_UP)); + break; + + case PIN_CONFIG_BIAS_DISABLE: + bcm281xx_pin_update(val, mask, 0, + BCM281XX_PIN_SHIFT(STD, PULL_UP), + BCM281XX_PIN_MASK(STD, PULL_UP)); + break; + + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(STD, SLEW), + BCM281XX_PIN_MASK(STD, SLEW)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(STD, INPUT_DIS), + BCM281XX_PIN_MASK(STD, INPUT_DIS)); + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->info->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + /* Goes through the configs and update register val/mask */ static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, unsigned int pin, @@ -1351,6 +2002,7 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, unsigned int num_configs) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + enum bcm281xx_pinctrl_type device_type = pdata->info->device_type; enum bcm281xx_pin_type pin_type; u32 offset = 4 * pin; u32 cfg_val, cfg_mask; @@ -1368,8 +2020,12 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, break; case BCM281XX_PIN_TYPE_I2C: - rc = bcm281xx_i2c_pin_update(pctldev, pin, configs, - num_configs, &cfg_val, &cfg_mask); + if (device_type == BCM21664_PINCTRL_TYPE) + rc = bcm21664_i2c_pin_update(pctldev, pin, configs, + num_configs, &cfg_val, &cfg_mask); + else + rc = bcm281xx_i2c_pin_update(pctldev, pin, configs, + num_configs, &cfg_val, &cfg_mask); break; case BCM281XX_PIN_TYPE_HDMI: @@ -1391,6 +2047,14 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", __func__, pdata->info->pins[pin].name, pin, cfg_val, cfg_mask); + if (device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, false); + if (rc) { + /* Error is printed in bcm21664_pinctrl_set_pin_lock */ + return rc; + } + } + rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); if (rc) { dev_err(pctldev->dev, @@ -1399,6 +2063,14 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, return rc; } + if (device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, true); + if (rc) { + /* Error is printed in bcm21664_pinctrl_set_pin_lock */ + return rc; + } + } + return 0; } @@ -1421,6 +2093,7 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) { struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl_pdata; struct pinctrl_dev *pctl; + int rc; /* Set device pointer in platform data */ pdata->dev = &pdev->dev; @@ -1451,6 +2124,18 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) bcm281xx_pinctrl_desc.pins = pdata->info->pins; bcm281xx_pinctrl_desc.npins = pdata->info->npins; + /* + * For BCM21664, lock all pins by default; they will be unlocked + * as needed + */ + if (pdata->info->device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_lock_all(pdata); + if (rc) { + dev_err(&pdev->dev, "Failed to lock all pins\n"); + return rc; + } + } + pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata); if (IS_ERR(pctl)) { dev_err(&pdev->dev, "Failed to register pinctrl\n"); @@ -1464,6 +2149,7 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id bcm281xx_pinctrl_of_match[] = { { .compatible = "brcm,bcm11351-pinctrl", .data = &bcm281xx_pinctrl }, + { .compatible = "brcm,bcm21664-pinctrl", .data = &bcm21664_pinctrl }, { }, }; From patchwork Fri Feb 21 20:32:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13986283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9783FC021B5 for ; Fri, 21 Feb 2025 20:42:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9YQfu5eAZOpEQuO+Sfc4ihsBhzM3CKhym7/o/Ff/aLE=; b=0mkFkYvV1oyQIQkexNokCQekhH cpGF02GZWfnRYPj0xwUc9Wa9RENokTKe2EjV52O6gZ0IuKW4mpPWL7Rqdw6cxSBfwTnMm15Fl9IJF y3QKD5ml5RTJVQ3sNbZ7+bO7WVKct18Lf58JCT/FbePJsMLI1Oj3a8oebW6/zuuYsO/tIET/OJZuk hLzsILC/rsnJLkUOZ+Tbp61WWsapba52dFIjSeQltPc43jcS/awhPoY8+U7tr6Oi4RodVKXHG5nnJ JMFZbpW1AeLI3bl4j4Mt09mQujDsAkxVC3aLTj+26tR52vnBWIBqPvkXv7P5HqFfNbr6XN986QEqy UGvKIbng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlZqM-00000006pXC-0xxr; Fri, 21 Feb 2025 20:41:54 +0000 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tlZhd-00000006ns0-0kXc for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 20:32:54 +0000 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-5dee07e51aaso4729754a12.3 for ; Fri, 21 Feb 2025 12:32:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740169972; x=1740774772; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9YQfu5eAZOpEQuO+Sfc4ihsBhzM3CKhym7/o/Ff/aLE=; b=C92htwrlS+gg1GyvkJzl98Lthr8OBNjL05oP1IZ9BUBfyldMk4kBfFcZ2Tam7NhvRe 52pqbCfHoWSfEy5bzITSG5tWG+KRg2zpDf3pTNVt9wJKv+M0Shg3rVlFV7YCI3PvfAHK C1NqlPIXG3jSZeNs+aRntaeUjv2nHBU1QqGEfgHNdztQmc7WdF02sryy2aNIwl/EM+iY XG1IExQMI8ApifFw5IFbCE2GRwgcG1+UvnyDSxxQEVmQ8bX4K8TYXExqSosICOu2ZVp0 n177Jgm4S1C+Ft8YBQ2F7qBefBnwDz9+StUvkBxXGVHxosR8IJmr4yEeN86fDXJYdZC+ H6lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740169972; x=1740774772; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9YQfu5eAZOpEQuO+Sfc4ihsBhzM3CKhym7/o/Ff/aLE=; b=elB5Qb7oK10cxGU7zqZf8GiRzbomysDBx6WAiEFH+hTGjcgRf2YhzI2A9Ow93lRKxH nOceYJVcZuBnJAXAoK3VL6KPImtdfcPumSkBQZZN+h+zkudQCXnsxJptUk0duYM6jooK L/BIJi/iT4rvQJM6LoP71FoSp706+y/llHRx8Bx+54pNWoxDUZS1rCaxYC4J0C4P+iu/ /NfbZjSNgfmLQseEq4uzn6iqjX9fNpE72/LIDTMMZw447pHANHjZOBNJTzrV1tfEanDO mdJlKGdE6+tj07blHShrkqaGTHRQkeAnw3on0RnGlOm2eA/hz4Mm90ZwOXQ+Itm34CEx 6J9g== X-Forwarded-Encrypted: i=1; AJvYcCX16T9KKp0AgZHZ/atS6xDCYNiCpeHpX/kZmCPoCaJ+GPgya6Ap2Qdy3PQY6rDxUqP7NvrcOU9iTb72vrfh04zF@lists.infradead.org X-Gm-Message-State: AOJu0YzVRARiZeeGXcU6KSbsyYr9Rs9pSE+Ez9ufvQrqALIwM4Pq74yc rNjKUOlXlPDIfNq5DU1Qlb3zl4/QCWEg70XXatp4ddIQEwkQA6+wgqiAqw== X-Gm-Gg: ASbGncuAPs1gVnUibT99BbCp9Bzd7x8NRq5rQISlF2XhvtqUPtFNVUp2gKSONn9TKBK Lg3Etg4Oe9KGmGbGuUNUF4OpnlK9JsySN7lWxdn9MFD2oQtWiOPJqH5WWuG5OK1YZ8p8aURBF/y NpAp5pe+UDkCX3Yz8ofU/JN/FjLvtWfqRW+kmPTdUj2aUQ6R+8SnxFMSHT1ep8R0Ch7r43GuQfE +uoO3W9zkcPfVYMANHD8t4K4zqVaLEy1YpI8nxcZJeuqIA9i+hdvfKugQjP30PQy+E3ukDpxsUx 9Jtnv462C70DIJ00ayAvq06K2zR3IBN1xNWcV1yGqm3Gyt7i/cWUD/POnCDI3w3JGdU+Wmv3 X-Google-Smtp-Source: AGHT+IFX16OnZk9d1DL8WxnUdqDk352LK10QFk5bhYj/vuHbbpoHUx8vxoyOPPZmEZpTd3FXudXcXw== X-Received: by 2002:a05:6402:388e:b0:5de:de30:dd0d with SMTP id 4fb4d7f45d1cf-5e0b7248363mr3572711a12.32.1740169971704; Fri, 21 Feb 2025 12:32:51 -0800 (PST) Received: from hex.my.domain (83.8.202.192.ipv4.supernova.orange.pl. [83.8.202.192]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dece1c418bsm14653485a12.24.2025.02.21.12.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 12:32:51 -0800 (PST) From: Artur Weber Date: Fri, 21 Feb 2025 21:32:41 +0100 Subject: [PATCH v2 5/6] ARM: dts: bcm2166x-common: Add pinctrl node MIME-Version: 1.0 Message-Id: <20250221-bcm21664-pinctrl-v2-5-7d1f0279fe16@gmail.com> References: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> In-Reply-To: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stanislav Jakubek , ~postmarketos/upstreaming@lists.sr.ht, Artur Weber X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740169959; l=896; i=aweber.kernel@gmail.com; s=20231030; h=from:subject:message-id; bh=xRQ8Om8ehQPvJHYxu39ZbgjQg1cKM3esiDGEfRR8xBY=; b=imTpwTI+Jp+A/uOxco0Ul0XB7DjOg3uyuqGuJeRn+bIitq+0cRSB7FHVyh6HSkhgxCIe5UP1C dCspq25gqPyBmoECI0KxT/cToXGsSGsHmG69DnJQy0vRcYNrYHSRGJs X-Developer-Key: i=aweber.kernel@gmail.com; a=ed25519; pk=RhDBfWbJEHqDibXbhNEBAnc9FMkyznGxX/hwfhL8bv8= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_123253_225203_BD310FED X-CRM114-Status: GOOD ( 12.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that the pinctrl driver supports the BCM21664, add a node for pinctrl in the DTS to allow for controlling pinmux pins. Signed-off-by: Artur Weber --- arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi index 87180b7fd695e65b52c52743e6315cbcca385fba..d4b412ac8b0343bd3773f50c59a20fa00a3923f8 100644 --- a/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi @@ -46,6 +46,11 @@ gpio: gpio@1003000 { interrupt-controller; }; + pinctrl: pinctrl@1004800 { + compatible = "brcm,bcm21664-pinctrl"; + reg = <0x01004800 0x7f4>; + }; + timer@1006000 { compatible = "brcm,kona-timer"; reg = <0x01006000 0x1c>; From patchwork Fri Feb 21 20:32:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13986284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCC48C021B3 for ; Fri, 21 Feb 2025 20:43:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1pvaaqiA/SmRoJNAwsNTHeXGNX/6oeYrcqiqLNPnA9o=; b=uVZt4mQ7Qif0NQQKimUdY7wfGW tZW2+SZsiTJJhNFSxc8nO31fxCKRJw/tbqXrH/mhYYQ1RZPyImALEJDR2T3uIc0EgOqvN6RVLyAHn zG+E6bq/ELXR+y/3P08SAoc0oKAJpNxqDn4ufRFBWCGh8DMxKfcIULcem05AY7JHr1SsiaOEtKHJ9 7+RlIfpKd5F2U9e/C3fGM56Mm3+RFHGFETRQhl4B+X+MxHFmsD6pfbUu4DbCgfqRID7l7q3kQAFwk y6SmS3lSa7OACKROTdhsfaWMi/ab0aiUX/DJokTfizViMZOQxBhGB/PvfcSaAkGLWVggbGFgRm6yJ FMiIDnYw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlZrm-00000006pm9-3dDG; Fri, 21 Feb 2025 20:43:22 +0000 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tlZhe-00000006nsS-2q5t for linux-arm-kernel@lists.infradead.org; Fri, 21 Feb 2025 20:32:56 +0000 Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-5e095d47a25so4848081a12.0 for ; Fri, 21 Feb 2025 12:32:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740169973; x=1740774773; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1pvaaqiA/SmRoJNAwsNTHeXGNX/6oeYrcqiqLNPnA9o=; b=EwrbQfqqz1BcZdgNpCeKoDJgdX0snfIsnAap0JQPLARKAz1sL7+Wo47qFKxk3/Z2js YbRmQN5s6DXf9TfEw5zbkPUJwYb9E8tI9Y794wb7E8QLXbIeyJC7TGXobeFPlD1lOpWr 9yKXNgx18eJP2K0owiFSBsu2DSAAe+LVaIwVOsKPEOMz7ZqbvlT+70h9buakrVc/QlHZ PADkI2wlJ3D0i9S4EiHfmMSY+vbFHh/s+hZocLvu/3UHuiiJQk2RhfljHhVuJ5PqRZEI uOLWdqAN2Mkglr7evQRF6Vhsppl0/YPnwEUl4kDBBQAMxwaynYAd5VGly8rD/cgFXb3k x/Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740169973; x=1740774773; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1pvaaqiA/SmRoJNAwsNTHeXGNX/6oeYrcqiqLNPnA9o=; b=KcF3I1RxbsDt9DP2dAm30jELEg9X01rJTb/ig27FqC/O2zVPO9xXmWRGzIDFgQeY7b duY7E/i9UCQNLAPXcuO73r8zWdJSOU21WS7o6i+e20abikd/U/zMKHgVB/7KRHlHK5W6 aqY4QHbYgKstQfLcBxPXVEh3UL2XIuBUSDugt/He0b8XKu5EdjaQRb/YNj2ke6OlWBUj 5F5ygnggaGGwYqGwObSKXFZ5WXDBWe0w66JVvc4qPA4hNwX0g8AC08Neg/cnDY37phH4 iOEDoqXB4MOl5ipzNQM19wquC8S2sveO9rCNGG0rFegsRMZIwMMPfL5a+Wh69qH5hqAK I0xQ== X-Forwarded-Encrypted: i=1; AJvYcCWqSD5BJ1CQcD6bMnl1GdK1HFCzGJ4Gm69bBm8Pps3rFJfpx7pACF14NLmwoCRy68xWPN9KSe9qvnGp0QvdImdO@lists.infradead.org X-Gm-Message-State: AOJu0YxgdGwK5jQRO9jXQWZd7OXbteAEeEAqvjqE9Ml6nsKEFU+X6Ut9 kRw30AypGiOTyXE7qlDArWOt+XAEWnHyPCgZWDUg1/GXppGkYwPU X-Gm-Gg: ASbGncukWxMFUTc+McdKuAz6LGL1DdOudu+/bqM3Ple6wQ32rYtPLXitXsq4PAem06D ClNRyHOYvujzgnoxNQbBPPPvZm6ASK5pSZ5TxJEgyC3Oo8er8dqtwTfiHZqolhuF9BbM0yfJNcI LXNE5tu7FyJRfIKRWSugsyAMWmkoqhEfJJ594KbxGDre6c4Mrw2/k2zwNQpjn8qGioOzU4CBZBN VR8DgIuxoGyYvOJBA6qKJWCx3u6wHlZJQbJCiAYXRl2OE/Kunq2IjM5YmqGVAl5JI9fu6ZCqqHD OWjt+T3JC+38uhzQ3q1LRpmM6VkHAglRTZogo6mcJ2rEZ/umFzp+wHZNiMp9fsRBKDGU3zlw X-Google-Smtp-Source: AGHT+IG8svSNh/gYeOBTqhQ8L5Z26mBOThRhLDOKdDTtl2i++2iJPATf7jNc/coLmYedzNMKZxPuAA== X-Received: by 2002:a05:6402:5192:b0:5de:4f37:e59c with SMTP id 4fb4d7f45d1cf-5e0b724782amr4219796a12.31.1740169972869; Fri, 21 Feb 2025 12:32:52 -0800 (PST) Received: from hex.my.domain (83.8.202.192.ipv4.supernova.orange.pl. [83.8.202.192]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dece1c418bsm14653485a12.24.2025.02.21.12.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 12:32:52 -0800 (PST) From: Artur Weber Date: Fri, 21 Feb 2025 21:32:42 +0100 Subject: [PATCH v2 6/6] ARM: dts: bcm2166x: Add bcm2166x-pinctrl DTSI MIME-Version: 1.0 Message-Id: <20250221-bcm21664-pinctrl-v2-6-7d1f0279fe16@gmail.com> References: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> In-Reply-To: <20250221-bcm21664-pinctrl-v2-0-7d1f0279fe16@gmail.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stanislav Jakubek , ~postmarketos/upstreaming@lists.sr.ht, Artur Weber X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740169959; l=7006; i=aweber.kernel@gmail.com; s=20231030; h=from:subject:message-id; bh=PoeeTQAJjZ5RdKFBcSwIbKAekpRiUcC0+f84D/Pj5vE=; b=zlHYkjc9MveY75Vzf279SZEL8zo1UrW74RttN4qfEkj8EQd/GvUY6pm98QsjvEAOjreBhiXbx /0PJXFlhOgeACkWOYaL/NeOugqp7mwMACJ6zcDULsBLMj7+0miqiOkn X-Developer-Key: i=aweber.kernel@gmail.com; a=ed25519; pk=RhDBfWbJEHqDibXbhNEBAnc9FMkyznGxX/hwfhL8bv8= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_123254_720483_21870C45 X-CRM114-Status: GOOD ( 15.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add common DTSI with common pin control configs for BCM21664/BCM23550 and include it in bcm2166x-common.dtsi. The configs are kept in a separate DTSI to keep things cleaner (pin config definitions take up quite a lot of space). Currently contains pins for BSC buses and SD/MMC; more pins can be added in the future. Signed-off-by: Artur Weber --- arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi | 2 + arch/arm/boot/dts/broadcom/bcm2166x-pinctrl.dtsi | 297 +++++++++++++++++++++++ 2 files changed, 299 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi index d4b412ac8b0343bd3773f50c59a20fa00a3923f8..f535212cb52fec0668abfc06e7268bead70d958a 100644 --- a/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi @@ -337,3 +337,5 @@ master_ccu: master_ccu@3f001000 { }; }; }; + +#include "bcm2166x-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/broadcom/bcm2166x-pinctrl.dtsi b/arch/arm/boot/dts/broadcom/bcm2166x-pinctrl.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..51b8730c8feea501f2c5ca6a7bad8233ed708c82 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2166x-pinctrl.dtsi @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Common pinmux configrations for BCM2166x (BCM21664/BCM23550). + * + * Copyright (C) 2025 Artur Weber + */ + +&pinctrl { + /* BSC1 */ + bsc1_pins: bsc1-pins { + bsc1clk-grp0 { + pins = "bsc1clk"; + function = "alt1"; /* BSC1CLK */ + }; + + bsc1dat-grp0 { + pins = "bsc1dat"; + function = "alt1"; /* BSC1DAT */ + }; + }; + + /* BSC2 */ + bsc2_pins: bsc2-pins { + bsc2clk-grp0 { + pins = "gpio16"; + function = "alt2"; /* BSC2CLK */ + }; + + bsc2dat-grp0 { + pins = "gpio17"; + function = "alt2"; /* BSC2DAT */ + }; + }; + + /* BSC3 */ + bsc3_pins: bsc3-pins { + bsc3clk-grp0 { + pins = "lcdscl"; + function = "alt1"; /* BSC3_CLK */ + }; + + bsc3dat-grp0 { + pins = "lcdsda"; + function = "alt1"; /* BSC3_SDA */ + }; + }; + + /* BSC4 */ + bsc4_pins: bsc4-pins { + bsc4clk-grp0 { + pins = "lcdres"; + function = "alt1"; /* BSC4_CLK */ + }; + + bsc4dat-grp0 { + pins = "lcdte"; + function = "alt1"; /* BSC4_SDA */ + }; + }; + + /* PMBSC */ + pmbsc_pins: pmbsc-pins { + pmbscclk-grp0 { + pins = "pmbscclk"; + function = "alt1"; /* PMBSCCLK */ + }; + + pmbscdat-grp0 { + pins = "pmbscdat"; + function = "alt1"; /* PMBSCDAT */ + }; + }; + + /* SD */ + sd_width1_pins: sd-width1-pins { + sdck-grp0 { + pins = "sdck"; + function = "alt1"; /* SDCK */ + bias-disable; + }; + + sdcmd-grp0 { + pins = "sdcmd"; + function = "alt1"; /* SDCMD */ + bias-pull-up; + }; + + sddat-grp0 { + pins = "sddat0"; + function = "alt1"; /* SDDATx */ + bias-pull-up; + }; + }; + + sd_width4_pins: sd-width4-pins { + sdck-grp0 { + pins = "sdck"; + function = "alt1"; /* SDCK */ + bias-disable; + }; + + sdcmd-grp0 { + pins = "sdcmd"; + function = "alt1"; /* SDCMD */ + bias-pull-up; + }; + + sddat-grp0 { + pins = "sddat0", "sddat1", "sddat2", "sddat3"; + function = "alt1"; /* SDDATx */ + bias-pull-up; + }; + }; + + /* SD1 */ + sd1_width1_pins: sd1-width1-pins { + sd1ck-grp0 { + pins = "mmc1dat7"; + function = "alt6"; /* SD1CK */ + bias-disable; + }; + + sd1cmd-grp0 { + pins = "spi0txd"; + function = "alt2"; /* SD1CMD */ + bias-pull-up; + }; + + sd1dat0-grp0 { + pins = "mmc1dat5"; + function = "alt6"; /* SD1DAT0 */ + bias-pull-up; + }; + }; + + sd1_width4_pins: sd1-width4-pins { + sd1ck-grp0 { + pins = "mmc1dat7"; + function = "alt6"; /* SD1CK */ + bias-disable; + }; + + sd1cmd-grp0 { + pins = "spi0txd"; + function = "alt2"; /* SD1CMD */ + bias-pull-up; + }; + + sd1dat0-grp0 { + pins = "mmc1dat5"; + function = "alt6"; /* SD1DAT0 */ + bias-pull-up; + }; + + sd1dat1-grp0 { + pins = "gpio93"; + function = "alt1"; /* SD1DAT1 */ + bias-pull-up; + }; + + sd1dat2-grp0 { + pins = "gpio94"; + function = "alt1"; /* SD1DAT2 */ + bias-pull-up; + }; + + sd1dat3-grp0 { + pins = "mmc1dat3"; + function = "alt6"; /* SD1DAT3 */ + bias-pull-up; + }; + }; + + /* MMC0 */ + mmc0_width1_pins: mmc0-width1-pins { + mmc0ck-grp0 { + pins = "mmc0ck"; + function = "alt1"; /* MMC0CK */ + bias-disable; + }; + + mmc0cmd-grp0 { + pins = "mmc0cmd"; + function = "alt1"; /* MMC0CMD */ + bias-pull-up; + }; + + mmc0dat-grp0 { + pins = "mmc0dat0"; + function = "alt1"; /* MMC0DATx */ + bias-pull-up; + }; + }; + + mmc0_width4_pins: mmc0-width4-pins { + mmc0ck-grp0 { + pins = "mmc0ck"; + function = "alt1"; /* MMC0CK */ + bias-disable; + }; + + mmc0cmd-grp0 { + pins = "mmc0cmd"; + function = "alt1"; /* MMC0CMD */ + bias-pull-up; + }; + + mmc0dat-grp0 { + pins = "mmc0dat0", "mmc0dat1", "mmc0dat2", "mmc0dat3"; + function = "alt1"; /* MMC0DATx */ + bias-pull-up; + }; + }; + + mmc0_width8_pins: mmc0-width8-pins { + mmc0ck-grp0 { + pins = "mmc0ck"; + function = "alt1"; /* MMC0CK */ + bias-disable; + }; + + mmc0cmd-grp0 { + pins = "mmc0cmd"; + function = "alt1"; /* MMC0CMD */ + bias-pull-up; + }; + + mmc0dat-grp0 { + pins = "mmc0dat0", "mmc0dat1", "mmc0dat2", "mmc0dat3", + "mmc0dat4", "mmc0dat5", "mmc0dat6", "mmc0dat7"; + function = "alt1"; /* MMC0DATx */ + bias-pull-up; + }; + }; + + /* MMC1 */ + mmc1_width1_pins: mmc1-width1-pins { + mmc1ck-grp0 { + pins = "mmc1ck"; + function = "alt1"; /* MMC1CK */ + bias-disable; + }; + + mmc1cmd-grp0 { + pins = "mmc1cmd"; + function = "alt1"; /* MMC1CMD */ + bias-pull-up; + }; + + mmc1dat-grp0 { + pins = "mmc1dat0"; + function = "alt1"; /* MMC1DATx */ + bias-pull-up; + }; + }; + + mmc1_width4_pins: mmc1-width4-pins { + mmc1ck-grp0 { + pins = "mmc1ck"; + function = "alt1"; /* MMC1CK */ + bias-disable; + }; + + mmc1cmd-grp0 { + pins = "mmc1cmd"; + function = "alt1"; /* MMC1CMD */ + bias-pull-up; + }; + + mmc1dat-grp0 { + pins = "mmc1dat0", "mmc1dat1", "mmc1dat2", "mmc1dat3"; + function = "alt1"; /* MMC1DATx */ + bias-pull-up; + }; + }; + + mmc1_width8_pins: mmc1-width8-pins { + mmc1ck-grp0 { + pins = "mmc1ck"; + function = "alt1"; /* MMC1CK */ + bias-disable; + }; + + mmc1cmd-grp0 { + pins = "mmc1cmd"; + function = "alt1"; /* MMC1CMD */ + bias-pull-up; + }; + + mmc1dat-grp0 { + pins = "mmc1dat0", "mmc1dat1", "mmc1dat2", "mmc1dat3", + "mmc1dat4", "mmc1dat5", "mmc1dat6", "mmc1dat7"; + function = "alt1"; /* MMC1DATx */ + bias-pull-up; + }; + }; +};