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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a property to tune usb2 phy's disconnect threshold. And add a compatible for mt8196. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chunfeng Yun --- v2: change property name --- Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml index a9e3139fd421..98faa823234d 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml @@ -49,6 +49,7 @@ properties: - enum: - mediatek,mt3611-xsphy - mediatek,mt3612-xsphy + - mediatek,mt8196-xsphy - const: mediatek,xsphy reg: @@ -129,6 +130,13 @@ patternProperties: minimum: 1 maximum: 7 + mediatek,disconnect-threshold: + description: + The selection of disconnect threshold (U2 phy) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 15 + mediatek,efuse-intr: description: The selection of Internal Resistor (U2/U3 phy) From patchwork Sat Feb 22 09:07:10 2025 Content-Type: text/plain; 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Sat, 22 Feb 2025 17:07:20 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Sat, 22 Feb 2025 17:07:19 +0800 From: Chunfeng Yun To: Vinod Koul , Rob Herring , Conor Dooley CC: Chunfeng Yun , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , , , , , Subject: [PATCH v2 2/2] phy: mediatek: xsphy: add support to set disconnect threshold Date: Sat, 22 Feb 2025 17:07:10 +0800 Message-ID: <20250222090710.10909-2-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250222090710.10909-1-chunfeng.yun@mediatek.com> References: <20250222090710.10909-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250222_010728_263356_420C0CB4 X-CRM114-Status: GOOD ( 10.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a property to tune usb2 phy's disconnect threshold. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chunfeng Yun --- v2: change property name --- drivers/phy/mediatek/phy-mtk-xsphy.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-xsphy.c b/drivers/phy/mediatek/phy-mtk-xsphy.c index 7c248f5cfca5..cac0f008bcb3 100644 --- a/drivers/phy/mediatek/phy-mtk-xsphy.c +++ b/drivers/phy/mediatek/phy-mtk-xsphy.c @@ -59,6 +59,7 @@ #define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018) #define P2A6_RG_BC11_SW_EN BIT(23) #define P2A6_RG_OTG_VBUSCMP_EN BIT(20) +#define PA6_RG_U2_DISCTH GENMASK(7, 4) #define XSP_U2PHYDTM1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C) #define P2D_FORCE_IDDIG BIT(9) @@ -95,6 +96,7 @@ struct xsphy_instance { int eye_src; int eye_vrt; int eye_term; + int discth; }; struct mtk_xsphy { @@ -244,9 +246,12 @@ static void phy_parse_property(struct mtk_xsphy *xsphy, &inst->eye_vrt); device_property_read_u32(dev, "mediatek,eye-term", &inst->eye_term); - dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n", + device_property_read_u32(dev, "mediatek,disconnect-threshold", + &inst->discth); + dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d, discth:%d\n", inst->efuse_intr, inst->eye_src, - inst->eye_vrt, inst->eye_term); + inst->eye_vrt, inst->eye_term, + inst->discth); break; case PHY_TYPE_USB3: device_property_read_u32(dev, "mediatek,efuse-intr", @@ -285,6 +290,9 @@ static void u2_phy_props_set(struct mtk_xsphy *xsphy, if (inst->eye_term) mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL, inst->eye_term); + if (inst->discth) + mtk_phy_update_field(pbase + XSP_USBPHYACR6, PA6_RG_U2_DISCTH, + inst->discth); } static void u3_phy_props_set(struct mtk_xsphy *xsphy,