From patchwork Mon Feb 24 08:24:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13987566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B766C021B8 for ; Mon, 24 Feb 2025 08:26:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmTll-0000G1-2Y; Mon, 24 Feb 2025 03:24:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmTlW-00005W-8Q for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:41 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmTlR-00019Y-9Y for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:35 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-22104c4de96so67765765ad.3 for ; Mon, 24 Feb 2025 00:24:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1740385471; x=1740990271; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=AqEFQR6NtqYF016dWrhbdwKDvTxMgBYRr2uJaanV30U=; b=gWq9A+ify6ClIR+tq8nSwPQHghtwaY9ls2lsirVyosmNtw1W7bigd0bsIvdrOMtuCq q4HNE1G4OA07EuT1wJqkwgqqMh/JWhF2gnXig29cVQ8OqqUjEL+t64L/V3iLi7b42NXd jDp2edwGNzzRZ6H0M7VneTqS4fcUOpGaH6zJV2vdpyK8pPEH6hrcNwfOK0kLaFY8M76u nKd/BaS9+AHddRUfxArHgasDlyiVZb0I2E3flk0Mt0LjLmYoy/TudQIbMWh9S2gb/Ogk MHHUFG+ObnaRhrLKUJzjxayajJyaY/yXqbs0bnsgMt9M1XO/2ySdB12o/LvICfV7DlzE O32Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740385471; x=1740990271; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=AqEFQR6NtqYF016dWrhbdwKDvTxMgBYRr2uJaanV30U=; b=gumdV4tz++uEhXx5ergQCbTK60rUp21bw00g7RYn02Ll+0X2SkMmkvPAvb441R2H9K 9PHi4I13VPEi/pzOclW+TRL1U6daUsQYXxseDYNW4VyOFCn4Yb7o/I4OljR202G4WOTV MutNT6eCNaDa3xk3sor/iqwUrk9Hj4hhpcM+g3Raqs4JzWlYP7lTedNaXFku3zzBWLVk 3KDkawHzkvMlYuzYe58Ecpz/xaIYENNMcMWjgSh8qZMIygQOtg2QFMjxNgliPIa6syUJ CVIDvcyAWRjcbl4adlxQQuVZaKrPjEtF6N6xMDjf5D7T3EM9SbbVODGMORFOYaM8S0Rj 2DMQ== X-Gm-Message-State: AOJu0YzRe/JMeFZjoLGtCNW3Kii/YuhknVqm8NkgLNGTxsR15PdT42dy Oa7rIpfJrH37JdLYeU6/KcAQXczTNsshp9PVbNa3/uiDsBrnzO7gAKmRNT5o9xZEEODDEM5pMc6 eTbI55TRjEJ3liZTFsY23RycJUZD4VdUgYnrv9UyA5YCbVfTFxVqaZoZ/Qsaj3w6oJVwF4jpHS5 /CFfVjPr4K17DHCRdhLdMJpqvmERbmvTrh9AXA7A31Zg== X-Gm-Gg: ASbGncu6eR9fDldKQIyM1pPmkaGyFshegMaPvVrhsNYh+t+LfzIdV3tKVzzcQyiZU+P sb6AUGkE6WPShxR1dSy8vhF4Qzc5ML/Bpfkj6pNA56vGDZiQuCtgEuMaf916kffb23yYFCyDJl8 W1rHFyfH0/AXOWNVSgwMnIEk4MHb4caJ2ITejlHNXrT4rEdcmghjehtRt/aE0jolNtx3AYA5JN6 x8ZDQ4ds0h8iLdBgY12Ygw7J9hrXXtDwJigSfMvX1r7ERjSgpxH2NBRPIOeOHfk3OR3EIzhN5+o EhaEe7EHvQz5ViNuNVmZ32w80LB/9ukTc0vjGgIdUzy3KPRlf67fJpa9 X-Google-Smtp-Source: AGHT+IF5QqudS/guWJAwcTCu7MubeLiRik2qZEgTLndydkU2C2LlObe5fgmUapkZfrPinHV8GkaCVw== X-Received: by 2002:a05:6a21:501:b0:1f0:ea87:b40e with SMTP id adf61e73a8af0-1f0ea87b40fmr4464540637.41.1740385471311; Mon, 24 Feb 2025 00:24:31 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7325c88d74esm17714914b3a.149.2025.02.24.00.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 00:24:30 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR Date: Mon, 24 Feb 2025 16:24:08 +0800 Message-Id: <20250224082417.31382-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250224082417.31382-1-yongxuan.wang@sifive.com> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As KVM_REG_RISCV_CSR includes several subtypes of CSR, rewrite the related macros and functions to prepare for other subtypes. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 70 +++++++++++++++++++++++--------------- 1 file changed, 43 insertions(+), 27 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 471fd554b369..ff1211d2fe39 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -111,9 +111,8 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ KVM_REG_RISCV_CORE_REG(name)) -#define RISCV_CSR_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ - KVM_REG_RISCV_CSR_REG(name)) +#define RISCV_CSR_REG(env, idx) \ + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, idx) #define RISCV_CONFIG_REG(env, name) \ kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ @@ -130,17 +129,20 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ KVM_REG_RISCV_VECTOR_CSR_REG(name)) -#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ +#define RISCV_GENERAL_CSR_REG(name) \ + (KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(name)) + +#define KVM_RISCV_GET_CSR(cs, env, idx, reg) \ do { \ - int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ if (_ret) { \ return _ret; \ } \ } while (0) -#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ +#define KVM_RISCV_SET_CSR(cs, env, idx, reg) \ do { \ - int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ if (_ret) { \ return _ret; \ } \ @@ -608,36 +610,50 @@ static int kvm_riscv_put_regs_core(CPUState *cs) return ret; } -static int kvm_riscv_get_regs_csr(CPUState *cs) +static int kvm_riscv_get_regs_general_csr(CPUState *cs) { CPURISCVState *env = &RISCV_CPU(cs)->env; - KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); - KVM_RISCV_GET_CSR(cs, env, sie, env->mie); - KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); - KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); - KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); - KVM_RISCV_GET_CSR(cs, env, scause, env->scause); - KVM_RISCV_GET_CSR(cs, env, stval, env->stval); - KVM_RISCV_GET_CSR(cs, env, sip, env->mip); - KVM_RISCV_GET_CSR(cs, env, satp, env->satp); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sstatus), env->mstatus); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sie), env->mie); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stvec), env->stvec); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sscratch), env->sscratch); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sepc), env->sepc); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(scause), env->scause); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stval), env->stval); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sip), env->mip); + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(satp), env->satp); return 0; } -static int kvm_riscv_put_regs_csr(CPUState *cs) +static int kvm_riscv_put_regs_general_csr(CPUState *cs) { CPURISCVState *env = &RISCV_CPU(cs)->env; - KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); - KVM_RISCV_SET_CSR(cs, env, sie, env->mie); - KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); - KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); - KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); - KVM_RISCV_SET_CSR(cs, env, scause, env->scause); - KVM_RISCV_SET_CSR(cs, env, stval, env->stval); - KVM_RISCV_SET_CSR(cs, env, sip, env->mip); - KVM_RISCV_SET_CSR(cs, env, satp, env->satp); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sstatus), env->mstatus); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sie), env->mie); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stvec), env->stvec); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sscratch), env->sscratch); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sepc), env->sepc); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(scause), env->scause); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stval), env->stval); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sip), env->mip); + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(satp), env->satp); + + return 0; +} + +static int kvm_riscv_get_regs_csr(CPUState *cs) +{ + kvm_riscv_get_regs_general_csr(cs); + + return 0; +} + +static int kvm_riscv_put_regs_csr(CPUState *cs) +{ + kvm_riscv_put_regs_general_csr(cs); return 0; } From patchwork Mon Feb 24 08:24:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13987557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6E40C021B3 for ; Mon, 24 Feb 2025 08:25:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmTli-0000EF-Cs; Mon, 24 Feb 2025 03:24:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmTlZ-000062-Gi for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:44 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmTlW-0001AF-3Y for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:39 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-220c665ef4cso67900755ad.3 for ; Mon, 24 Feb 2025 00:24:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1740385476; x=1740990276; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=/bWOD2oND7Vlosu6daJhAwxVOQyujRyeWSVMNgf17/o=; b=jrZR5GrXF+l/NJzNeacCA10YcrCE83kUCxclmEW0haMDE2m+coIB0I3f7D2HC3Ujer THeAGMAI4EJ0mhptUPhGM5ZYNOGNf3o/XeS/M85xJuXsADUYpwAQ+yhx60mhigI+zMI9 yF5Om8iqARVPueGatAo4qEUyrDDlbAEwNHEANXf4vuqOgLfLe5v+lUsCa5pTnt3HB64E fbVjy/C7ZQZZSi1JwY6PqX+tHMNYY5jpbgmbIV4sT8kQWZfybQRsDffdjIIopSFTZoqc 9v2dLTpLbbNkUjrPYHRXjbj6l97ki3X4IKyaDajcv2VN/MzQrk2RA/oPI19RJq3HGbzb 9dfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740385476; x=1740990276; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=/bWOD2oND7Vlosu6daJhAwxVOQyujRyeWSVMNgf17/o=; b=oHZA4F1dnKxRdFS5HUaLoTIvsIbroQKarkPjZ4S8c1SBBnO1QiB8tQGVzDRGpRsswb jWi/OSB0AB7TJdCN0EipRzOk8MiMxYSjqb3yfNkSNBFCVyBsvrNkb6z7Dw/3NBauZ4NV FNb8lwpKJ6sSh/zo/4EkmCHRsuxIMLLM/u4hjUnLBKvfah8+XLuGoe6hAWoGIUVU9FUt qaLivn3hKoM3bFRuC11F/xHUx/S3lENs2fafZg4S0x4+N1m+Hjm+QmQ0ReYBFgYIN7m0 7gt8l7qjtPQgqNTy8uFtLYTdxcpWigOuT8zuIjgMiYivGib4xE0dEGQO3TVEkwgPG9jD nM0w== X-Gm-Message-State: AOJu0YxboKnFGsD4lla/2wkkzdKqMlYmSvpNpfUUh+nfATzgsM46QICo HAR/rC3+JJYrWs3vOdbuvmiyHdUEZlI7XjSrqxZThCeTp5zttpfoZYk4hMyVeN+A6DIv1jfCkge 5j1Gkg2hBIJfs7EMR9P+hNLT92YfDbUhBEV/JZVIMdzLy3H9qEB3vwVT9blKVEmQLwyaujV8X7D jWl/yD2bbw8zdQ7WlFdUA5qQQfCn8Gi5MJfCTALlMdYA== X-Gm-Gg: ASbGncuYuO20y9pM9dS/NrRKVuRLlA2kzhd2aCd3w+oAOxEua6LrOQDmaXjfFnGn/1n 6nyIxs4Ye0d82DfxIXVUMEn3UNwhZgw8d/HmgW2C/Br2H1uyjGiXmLSxEcWCj+GYsbbD8pxTw9U esbN82wd7M3LfalMnF5aC+iqF88P+xUDQFwCEudM/IVvnMUTsCz4+Z1ry2GVTm/hdsvx9g60Ehh gfnW/2MCDr82VH9eMGlRpXK6hjIaeRWxkX5e+9s98q8WZkkN4wLb3GYIttNxgPpPTstBeWpoJAn Udwb2b6SSfr6GwIfDYkT/SGxK4bsq4QxryfpJxAImOtucXfJT33kuWAV X-Google-Smtp-Source: AGHT+IEOnxIkYT3cpPEoJ0iYbY7e59Nd8dloYrQNQ1LRjgyeH0A6NED9nKlU6VgDOa09rr3uMZ07oA== X-Received: by 2002:a05:6a21:7882:b0:1ee:cd18:d400 with SMTP id adf61e73a8af0-1eef3c883ecmr23178823637.11.1740385475705; Mon, 24 Feb 2025 00:24:35 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7325c88d74esm17714914b3a.149.2025.02.24.00.24.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 00:24:35 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA Date: Mon, 24 Feb 2025 16:24:09 +0800 Message-Id: <20250224082417.31382-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250224082417.31382-1-yongxuan.wang@sifive.com> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 45 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index ff1211d2fe39..c7318f64cf12 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -132,6 +132,9 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, #define RISCV_GENERAL_CSR_REG(name) \ (KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(name)) +#define RISCV_AIA_CSR_REG(name) \ + (KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(name)) + #define KVM_RISCV_GET_CSR(cs, env, idx, reg) \ do { \ int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ @@ -644,9 +647,50 @@ static int kvm_riscv_put_regs_general_csr(CPUState *cs) return 0; } +static int kvm_riscv_get_regs_aia_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + uint64_t mask = MAKE_64BIT_MASK(32, 32); + uint64_t val; + + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); + + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(sieh), val); + env->sie = set_field(env->sie, mask, val); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siph), val); + riscv_cpu_update_mip(env, mask, val); + + return 0; +} + +static int kvm_riscv_put_regs_aia_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + uint64_t mask = MAKE_64BIT_MASK(32, 32); + uint64_t val; + + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); + + val = get_field(env->sie, mask); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(sieh), val); + val = get_field(env->mip, mask); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(siph), val); + + return 0; +} + static int kvm_riscv_get_regs_csr(CPUState *cs) { kvm_riscv_get_regs_general_csr(cs); + kvm_riscv_get_regs_aia_csr(cs); return 0; } @@ -654,6 +698,7 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) static int kvm_riscv_put_regs_csr(CPUState *cs) { kvm_riscv_put_regs_general_csr(cs); + kvm_riscv_put_regs_aia_csr(cs); return 0; } From patchwork Mon Feb 24 08:24:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13987571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C57AC021B5 for ; Mon, 24 Feb 2025 08:26:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmTln-0000HI-H2; Mon, 24 Feb 2025 03:24:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmTld-000081-Cf for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:45 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmTla-0001Av-La for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:45 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-221050f3f00so89196005ad.2 for ; Mon, 24 Feb 2025 00:24:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1740385481; x=1740990281; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=lxmKqqKswXlJbs5eaPNHVwiNA4X+9jY4AP8kBqT7664=; b=i9FdGUbosEC6/F9S2gss0jVXZ3cqSw13O1fNtHWZ0exO/CC6ANVkIC/iuM3oJDxFwA psMCzyyzrWpnPkJ/bo3OfpiGQRX3Ha4j7CxLlu23K4YYV4igD+gEQlDr9ZEgHZvxlwkr O0A5mhr01CQ4jZuxDDdn/lF1kY1AgGiA2rwnaigtAtTILK712nIXXXaeJRGFg5uPRwEA 3FDjOroP4INRKG2qQbMdkT25m1hgAkNgC5/tQlU7J8byzOj6I84npUbRMkd+JLvOtM19 rzfQHXfOqjR67+QIFntLST7Q8inKdFojqVOZlzBNAidirnrdlYHBSzF+QQ9pXXwfYRY1 vxLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740385481; x=1740990281; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=lxmKqqKswXlJbs5eaPNHVwiNA4X+9jY4AP8kBqT7664=; b=B0ERBcHQxUSzbVokUZ62uM1AX6whgidUkYDQ7izCOWctAVU9MTu3EsFWUclqLUGbV5 Z82HEPbHwyYQNj9LMrjkOL/zsTkZ27NduBHzZ2Gl5ZM9VWqXn4VVPx1SsHVn1KmTNrFQ HBloP7YO5B+hc72MhxWeuXj6W99ltfjNqBFB3xqBg9+puAnPUxMtsjyoHuXWMEh0UWHJ y9DnQJVwT/2+K5B6rAGSLgtADyZCXEcdiWOoS5ekywUPuAd9oj9IXinAfyZSh5GiujXq OvCGsLO/UAEtC8NuVD0nw0o5y9qguJR7Bb7lPE36raad3SwmYybcrCGj9/O5bRLNlR6v PoUw== X-Gm-Message-State: AOJu0Yx7uMOAqQKio+GFuJYw2lHrOJGC4mMojQtEYA7OLUDH5X4YZ17u pf4G6XtfyOU7+MwAfzCzsE23uA5ThHqvRsUc/1WQc2wt+J//CVtxnb9GCL6IaR4t/ae5chMMV9N nJfJufxjkXOQvny/1GSqjnAIRYpNQc5jCS/cdazrPNlKd3mLXbjBVwc8tai1ngJRyGt/8zlY3pF f96PREZbwxsr+6gPmbIE5Lt8WTvrGPptiDKmdHuaXoBQ== X-Gm-Gg: ASbGncuCpo18bK/CwJSSRe1hj0VlK/rg1i6bBosgIg+awYGHmd8IhrM3goGRmIOjLKj bWM0nyrZfnRsiSCfoc8EDfISd1TNFEvT6PEao4urUPc3JZ4GuIOwwGoc0czXf/KhSzzi90i6vBm WQQCZJBDBzk53hBl+RZeOORk9l1/zjZvRc9zQxxoF35iaCwuoCnRpRLkxfX9kCirZfyIo6wF3gU swsOwXwBQsGDrMr/umoQFDnPiM4/nRBs7umM0ZrJmzLFaGrMybP8o1KevcjI82u3qEtzoBCFbtp QAvMs3WZvtjyTZKnc4WYUdEGQxLd6C9pHp2sy04Tx8VNZl8BfMSG+OA5 X-Google-Smtp-Source: AGHT+IGQ7eju7iu6W5RoT1p96E/VQB3wy0f6AcRYFWl8cV1djL5uXEqVv3e65iwwjVJ+/O+2ydKSYg== X-Received: by 2002:a05:6a00:805:b0:730:75b1:7218 with SMTP id d2e1a72fcca58-73426d7782emr22451288b3a.16.1740385480586; Mon, 24 Feb 2025 00:24:40 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7325c88d74esm17714914b3a.149.2025.02.24.00.24.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 00:24:40 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN Date: Mon, 24 Feb 2025 16:24:10 +0800 Message-Id: <20250224082417.31382-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250224082417.31382-1-yongxuan.wang@sifive.com> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of Smstateen extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c7318f64cf12..d421c7a1b65d 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -135,6 +135,9 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, #define RISCV_AIA_CSR_REG(name) \ (KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(name)) +#define RISCV_SMSTATEEN_CSR_REG(name) \ + (KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(name)) + #define KVM_RISCV_GET_CSR(cs, env, idx, reg) \ do { \ int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ @@ -687,10 +690,31 @@ static int kvm_riscv_put_regs_aia_csr(CPUState *cs) return 0; } +static int kvm_riscv_get_regs_smstateen_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_GET_CSR(cs, env, + RISCV_SMSTATEEN_CSR_REG(sstateen0), env->sstateen[0]); + + return 0; +} + +static int kvm_riscv_put_regs_smstateen_csr(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_SET_CSR(cs, env, + RISCV_SMSTATEEN_CSR_REG(sstateen0), env->sstateen[0]); + + return 0; +} + static int kvm_riscv_get_regs_csr(CPUState *cs) { kvm_riscv_get_regs_general_csr(cs); kvm_riscv_get_regs_aia_csr(cs); + kvm_riscv_get_regs_smstateen_csr(cs); return 0; } @@ -699,6 +723,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) { kvm_riscv_put_regs_general_csr(cs); kvm_riscv_put_regs_aia_csr(cs); + kvm_riscv_put_regs_smstateen_csr(cs); return 0; } From patchwork Mon Feb 24 08:24:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13987567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BA4EC021B5 for ; Mon, 24 Feb 2025 08:26:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmTlm-0000Gb-1p; Mon, 24 Feb 2025 03:24:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmTlh-0000BT-DW for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:50 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmTlf-0001Bb-EN for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:49 -0500 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-22128b7d587so76086585ad.3 for ; Mon, 24 Feb 2025 00:24:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1740385485; x=1740990285; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=onlUINOp8JpvgGqdS5sWDC3DlUou1fW9JzejUaBAofM=; b=dvQ3QL6IZhvcLQL0ghsJrDsZ5O+e5odpfNnYrWEJaJ2AgLho7nQufB/CZJGDq6drh5 CM/JRbwe6JLpc2o/2zNbjG8DlsY6AclI8XLBwry4Z5C33OIt5HEhmOLyYD9qa7QltdFK nRQ7dSPeMw+Q8swiOM7PG9WAW236U7dT9ca0OOiOnBhvQdAGELJKGp1FdpWXOZVdMPq9 o2GLNpizgplldvqv4Gsq9SkYXTnB9Xrwgg1/1ECXHaPeWiYKphN8s2WFoS7QbcTSl2Md nY+udvmQCEmyBU3A52Bt1i2f/YENpQo/aaQqNU36Y5T3gbeQXnKGEpqVfux/aMqHFLrf 2ERA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740385485; x=1740990285; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=onlUINOp8JpvgGqdS5sWDC3DlUou1fW9JzejUaBAofM=; b=SyRXxKmAltfCLRIiVG+qeiodqj911IutxJELfjM0RtzQuoEiGlK6SfChveE+l3/nvV ZJN1m9k//wpzFEyVL7xrrlVX+kqJtsyWi/XQA5jVoHBzw8VcZODEkdWy6MMxyd8tpQmh q5QLVd1SLj1JNsZ8HJJX5lbQ/vOQbCHXszUyE+jF30355g1Zeqr0E2In1ACp1QWsGQIE FX+1XmruzZHcejRcBeHapOprF3gV3dq/U3NsWwg03oibgH30GPbzP1xM99H2O65fvPgd Hsg9PjSk2cCLoz1OuZHFSbLWhQhW6MWwSaW4LJVbmxZKpoFqvdEAkEop37WBadF6WnRa ZqYw== X-Gm-Message-State: AOJu0YyUqDXLpTxj0bwEYP5lqpgK2SC1E29eoMOOblCaWrAMclNmMyiJ TEIIVynlxwE5AwFHSWnBMzNTbagutJENZf9RELkVsxAcDLarcJVmImz1OkAf1/UR7gMmngLeE8g QOMccP8m1FeLZn6fZXKwtZRA5Wp9Vy80zMaXMcSZBpNP1rjBJpBBJVZMvYN/FzPjhfk6O4kyiUG /VzWQGyMXxEfRIMTCtFF9Qx9SxZkZ0pklRVOe/E4sjYw== X-Gm-Gg: ASbGncvPnJmc/6P0qxTqEU7TlhS+fH08Oa/ga75YNqqcBtgA9NB40tzJiwQnUfjR6C6 rEP7D19Ng+i3kZdKBiMeUZZVqE4dY83EgB4zRu8vlNyVAkZsOt74g0xJoXWOjToEbZrPTn2A9SZ dhwrcoX/QSUTFnTo2EQ5LEv8B/H2nf+kQnf/SvAOyqDUlGCA9R1kF5MMRqwlhWb5jL6VzOEfi1w vRqGKmMempDMVHa1UcLRlHXd/BFdCF53vLRHYwUBWglJSoWbxbe5o2Z1rgWDHLMQsZF4C7SpMZr u5O1LY3wKlUpEFhQeHjyS0OEq+2SyJjAMKteeYP3wOUX9Rc7asS/P5AS X-Google-Smtp-Source: AGHT+IFUB2NTRW56OIeSFM0J0s3sbM8xJzq+zvg3CSR8DFYSdfiwAVuzghlx2r0rdoYs+QjJxMyF6Q== X-Received: by 2002:a05:6a00:9283:b0:732:56cb:2f83 with SMTP id d2e1a72fcca58-73426d72adbmr19698817b3a.15.1740385484860; Mon, 24 Feb 2025 00:24:44 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7325c88d74esm17714914b3a.149.2025.02.24.00.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 00:24:44 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH v2 4/8] target/riscv: add helper to get CSR name Date: Mon, 24 Feb 2025 16:24:11 +0800 Message-Id: <20250224082417.31382-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250224082417.31382-1-yongxuan.wang@sifive.com> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add a helper function to get CSR name from CSR number. Signed-off-by: Yong-Xuan Wang --- target/riscv/cpu.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616c3bdc1c24..df10ff63474b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -920,8 +920,14 @@ extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); -void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +static inline const char *riscv_get_csr_name(int csr_no) +{ + g_assert(csr_no > 0 && csr_no < CSR_TABLE_SIZE); + return csr_ops[csr_no].name; +} + +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); target_ulong riscv_new_csr_seed(target_ulong new_value, target_ulong write_mask); From patchwork Mon Feb 24 08:24:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13987569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED4CAC021B9 for ; Mon, 24 Feb 2025 08:26:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmTlt-0000M0-6K; Mon, 24 Feb 2025 03:25:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmTlk-0000Fz-Vi for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:53 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmTlj-0001CH-1m for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:52 -0500 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2210d92292eso121843545ad.1 for ; Mon, 24 Feb 2025 00:24:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1740385489; x=1740990289; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=KrqoTxsIbTe1eFZuZfpt0EkzCEKWtzl1UCfgmQ9eTvw=; b=RIq80Msy5QGT+ggf86lshkCuaAAO3FUCTSFNMGFW+z7G+62n4d3/yZq2NXHZz7tZtq 3tGLMVj+YRDM9CDNZomESWXX9qbzgaf0+sOi7soLE6BDMIP/X4BtC+xOsLD6yEnZSVKo 28BitcAkArcDDN+OqUTkNZlwl0RdMycS8XG16t0ruIAEYrzBsoqLJv000GxWZCQ7rkjy a/y6O4eMOPhTLYmRyBuvW3xj7u7j+uYDwwwPZp+2OQvg0OXVgQxYh7FOiZHTor1NrVHc i4x/7lc7fi3EhQ4GQjByJ/Aq8WApl+553lmPnOqqcBO4Aeh37bMzDRg/sIMXFGSFSms7 lxpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740385489; x=1740990289; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=KrqoTxsIbTe1eFZuZfpt0EkzCEKWtzl1UCfgmQ9eTvw=; b=SrzKcar9s/MjoSGoG0VrQ09bP1gX1CSIrDUqhrtBgcKtzX2lYmSRJ5Gsa5Qsd7179A PxCf0GIsuh6nNecloBV8n4anPhn/MFh6dRjlEls8+DhMyGzes8moWBL66CkDc/37Sch7 kTpSGVPXX+BjvJNPueltv4cWNtv8Gzu1Xuapc6byjrC9ue+bs6t+9zEdcG1q7PLCzQiY 0ULbXRqtox69/b3mAXPl732m1PF2klDvKlXdkD/2kptpROwkzHr6Oxa3Oaq2+AnxU8Uu aoNK0MFANsyAZKF5Rjc4pmOwtOYw98AUc3RwClI2iSW0INnmsdaLhcCLiqxzUSeG1DP2 b1ug== X-Gm-Message-State: AOJu0YyqBSpkuvCO/3tnebaxL/1JZRcWz47zxHtw1ArBkQ4nULGjYB6S 8paTKihsh/a/QkXWuVEUNMMz7OhCfr9GUI0KBYjPWp6/BCbMvksJ1lYoyrtEp/6qFGFYBNicrUK 0X7kFGSDv1RL0lJ6klH+m4s8N0SrWLuinXG20uKIgtj2KmFOTPB5LLK7UTmMu4xyzGJHSsRzG5Q zEl53WVmGT3uPxPkchqampJtzWfTX3EZXY0gJCm0ZPoQ== X-Gm-Gg: ASbGncvauCRjc0WH0Fo3CK0UCZ1RUaJd+zAMuAPfdRpf8mZFg3k2HtcNIDfvTXnB4bj qLz8thf+e0Y3r1Nui3V8pjNKvDFQuWTXzj8cBOleUhoC6n6XG1c3cTqGln93YQZr8tHIYvvVBBF Z/Pkher/eA60eVGpxACfdBZZ//fQr5Gp6V3b5YJU/Jau2AHzs68mBc2NBdt3iFFgCMWp7bPDCxb PCOPjkvvAsYr8JQqfQRwM53OcTvYBuCMpwTiNpux537/78jUdl6JtWtDsGD/vYc0XbqA0P6sxKO +X4+odUb1x0IMtUAjKXQvoy/QY3F8QDRAsv7j7U0oABkb8NhWU/rPhiR X-Google-Smtp-Source: AGHT+IGjH/BQi3tAyYa2ZKm8trvfQ3aVH+LXY8Fjnh9aGJG61UkeaPcdTC2CdkykPoDwTSzfKFXGNQ== X-Received: by 2002:a05:6a00:2d07:b0:728:e906:e446 with SMTP id d2e1a72fcca58-73426daad0cmr19196912b3a.24.1740385489359; Mon, 24 Feb 2025 00:24:49 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7325c88d74esm17714914b3a.149.2025.02.24.00.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 00:24:48 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr Date: Mon, 24 Feb 2025 16:24:12 +0800 Message-Id: <20250224082417.31382-6-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250224082417.31382-1-yongxuan.wang@sifive.com> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rewrite the kvm_riscv_handle_csr() to support additional CSR emulation in user space with KVM acceleration. This update reuses the TCG CSR emulation function to simplify the implementation and reduce the redundant work. Also it introduces two hook functions for certain CSRs. Before emulation, the related VS mode context of the CSR can be loaded from host in context_load() hook. After the CSR handling, the modified VS context is written back in context_put() hook. Signed-off-by: Yong-Xuan Wang --- target/riscv/cpu.h | 2 -- target/riscv/csr.c | 18 +++------- target/riscv/kvm/kvm-cpu.c | 68 ++++++++++++++++++++++++++++++++------ 3 files changed, 61 insertions(+), 27 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index df10ff63474b..81b8081d81e0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -928,8 +928,6 @@ static inline const char *riscv_get_csr_name(int csr_no) } void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask); uint8_t satp_mode_max_from_map(uint32_t map); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d0068ce98c15..a2830888d010 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5389,8 +5389,10 @@ static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) #endif /* Crypto Extension */ -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask) +static RISCVException rmw_seed(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask) { uint16_t random_v; Error *random_e = NULL; @@ -5414,18 +5416,6 @@ target_ulong riscv_new_csr_seed(target_ulong new_value, rval = random_v | SEED_OPST_ES16; } - return rval; -} - -static RISCVException rmw_seed(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, - target_ulong write_mask) -{ - target_ulong rval; - - rval = riscv_new_csr_seed(new_value, write_mask); - if (ret_value) { *ret_value = rval; } diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index d421c7a1b65d..b088b947adae 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1626,26 +1626,72 @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) return ret; } +/* User-space CSR emulation */ +struct kvm_riscv_emu_csr_data { + target_ulong csr_num; + int (*context_load)(CPUState *cs); + int (*context_put)(CPUState *cs); +}; + +struct kvm_riscv_emu_csr_data kvm_riscv_emu_csr_data[] = { + { CSR_SEED, NULL, NULL }, +}; + static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) { + CPURISCVState *env = cpu_env(cs); target_ulong csr_num = run->riscv_csr.csr_num; target_ulong new_value = run->riscv_csr.new_value; target_ulong write_mask = run->riscv_csr.write_mask; - int ret = 0; + struct kvm_riscv_emu_csr_data *emu_csr_data = NULL; + target_ulong ret_value; + RISCVException ret_excp; + int i, ret; - switch (csr_num) { - case CSR_SEED: - run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); - break; - default: + for (i = 0; i < ARRAY_SIZE(kvm_riscv_emu_csr_data); i++) { + if (csr_num == kvm_riscv_emu_csr_data[i].csr_num) { + emu_csr_data = &kvm_riscv_emu_csr_data[i]; + + break; + } + } + + if (!emu_csr_data) { qemu_log_mask(LOG_UNIMP, - "%s: un-handled CSR EXIT for CSR %lx\n", - __func__, csr_num); - ret = -1; - break; + "%s: un-handled CSR EXIT for CSR %s\n", + __func__, riscv_get_csr_name(csr_num)); + + return -1; } - return ret; + if (emu_csr_data->context_load) { + ret = emu_csr_data->context_load(cs); + if (ret) { + goto handle_failed; + } + } + + ret_excp = riscv_csrrw(env, csr_num, &ret_value, new_value, write_mask); + if (ret_excp != RISCV_EXCP_NONE) { + goto handle_failed; + } + run->riscv_csr.ret_value = ret_value; + + if (emu_csr_data->context_put) { + ret = emu_csr_data->context_put(cs); + if (ret) { + goto handle_failed; + } + } + + return 0; + +handle_failed: + qemu_log_mask(LOG_UNIMP, + "%s: failed to handle CSR EXIT for CSR %s\n", + __func__, riscv_get_csr_name(csr_num)); + + return -1; } static bool kvm_riscv_handle_debug(CPUState *cs) From patchwork Mon Feb 24 08:24:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13987570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6A6FC021B5 for ; Mon, 24 Feb 2025 08:26:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmTls-0000Lf-6F; Mon, 24 Feb 2025 03:25:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmTlp-0000Kg-TZ for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:57 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmTln-0001D9-Ng for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:24:57 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-220d28c215eso60738285ad.1 for ; Mon, 24 Feb 2025 00:24:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1740385494; x=1740990294; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=i6yarlSFGT+UKPKTiZcWyZV6IpwfiTEwTc/5lhIQVPQ=; b=kSFvly8Js8m5VB5v52rP4KDY6Wv219JulweWb5Z0Q6/vKFscEni4rUwXydJypskdGn NOcWQhdUfbQnmW2i49L/yi7lkSj+P+T6reL2GyV9d5cdkxs6x+BtOL1EOIA7n6LZ4BdE LsV+BlShdMJLlWXWjHYhbpYWPe3XBH3q44VPGQpjwF9dFAjAUW3HbP1XD25YD0ztB3hd so3d+K25J9Z1Rf5+9aNtzIvagr0YP4UeNodzRGKLuYrPdfWy+Vd3P+FWDmHBHkFuD9mA wcGfBdwrvRXM/lsHm2FkbYqV5jujnXSm1PF/KrTBr9aY1s1jEvHKrh2FL5vMEDRgsadH yz6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740385494; x=1740990294; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=i6yarlSFGT+UKPKTiZcWyZV6IpwfiTEwTc/5lhIQVPQ=; b=I/oR8VYbdKJiBAVjuJNimADtBOpK1E0GX1DJqKKgqO4hO3HYrs6cV/NlZeC03ctpi8 1IWEJG7pI6Mk+7KCoqKCQYZlyMwHVZ+nMr1sALHGnRSw099QcOcEPitPuMn102YwbVTe HzzXjO/tPSEmlch7trpPTVK4tZg6suDOISkUP/nSsgdwPY255Rb2sH/yneIFvOgvJ2u1 NvJUY3q8yVz6fX42Bd/MSV3YwIBEI+yYFYf67WRr9IlUWFXsEuOfr2EBQG7prQdosIAL zK7kPNM/cRlMc76aozZWSkSHkklXH0GF2iLs6i1KX5n2k88rqogVQ6FMGDpZbOQGYTdZ GnVg== X-Gm-Message-State: AOJu0YzlPVXwj0uKVHcIwgqyIK9qb91bXStt5CSBEPC5ZJsi7SaC4p5p 2LfDikWx7gAx5nJ8W+RvC0KPx4r8amVx6P0IQfsJfkZzLtw33gclU1gf7MwmodhHYhEDzztWAXz tE2Fqbw/iVWlQEflHDM7IJfmu8kkuES9gLwr+bU2YxLg5/sH8nJ6/sAxn1I9brY/deVHrZ38Neq BLXk46ppBtf9BUoTee/ndnUrCg5VtsCNWlqkiyf5w0dg== X-Gm-Gg: ASbGnct56fjnNdYHlqAZFVb/67gdx2TSPTo+KSva10mZM8hoxjUx7PKEZZwhArDEP+U aVj0fZqQN5q4V5G+AvA6/JIBo3BRiW+BgzzKnm39w8y7wHD+vA0gfZ8KAi7ABfalj2oNAfsg1lK D4kdxdhEh5lW79I64iHg4w2Mv+xYtWIjzPK256MUZ6LkxBowYnH42ied5Jq9mgull9UfPKcxgcs LyhEEdX8xVohkMN6/sLEkq5lL9AqHdcLJlGKH0czoMd+OczLpHLMveEnpmu2eQKgokuGJfCBd8l n4e/OURxEBkdsw7WzRfdkFpwf7O6rCAgknEzXpcqovGSGIBIldE1gXch X-Google-Smtp-Source: AGHT+IEN6WhuDVC1opB9Lv1QBgB440dTOjy2ZAWhTt5CWVs2Ah8MeYPEpOdsvQxQx2BmvPaFIjYnCQ== X-Received: by 2002:a17:902:e552:b0:21f:3a7b:f4f1 with SMTP id d9443c01a7336-2219ffddf44mr222136295ad.32.1740385493680; Mon, 24 Feb 2025 00:24:53 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7325c88d74esm17714914b3a.149.2025.02.24.00.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 00:24:53 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation Date: Mon, 24 Feb 2025 16:24:13 +0800 Message-Id: <20250224082417.31382-7-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250224082417.31382-1-yongxuan.wang@sifive.com> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Support user-space emulation of SIREG and STOPEI CSR with KVM acceleration. For SIREG emulation, the SISELECT CSR value and iprio array must be loaded before handling, and since the iprio array might be modified, it must be written back after the emulation. When running with KVM acceleration, the machine lacks M-mode CSRs and does not report S-mode support in its environment configuration, even though some S-mode CSRs are accessible. This patch adds kvm_enabled() checks in relevant predicates to ensure proper handling and validation. Signed-off-by: Yong-Xuan Wang --- target/riscv/csr.c | 12 +++++++++--- target/riscv/kvm/kvm-cpu.c | 27 +++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a2830888d010..594df30c456a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -27,6 +27,7 @@ #include "exec/exec-all.h" #include "exec/tb-flush.h" #include "system/cpu-timers.h" +#include "system/kvm.h" #include "qemu/guest-random.h" #include "qapi/error.h" #include @@ -42,6 +43,11 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; } +static bool riscv_has_ext_s(CPURISCVState *env) +{ + return riscv_has_ext(env, RVS) || kvm_enabled(); +} + /* Predicates */ #if !defined(CONFIG_USER_ONLY) RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) @@ -52,7 +58,7 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) return RISCV_EXCP_NONE; } - if (!(env->mstateen[index] & bit)) { + if (!kvm_enabled() && !(env->mstateen[index] & bit)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -66,7 +72,7 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) } } - if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { + if (env->priv == PRV_U && riscv_has_ext_s(env)) { if (!(env->sstateen[index] & bit)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -326,7 +332,7 @@ static RISCVException csrind_or_aia_any(CPURISCVState *env, int csrno) static RISCVException smode(CPURISCVState *env, int csrno) { - if (riscv_has_ext(env, RVS)) { + if (riscv_has_ext_s(env)) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index b088b947adae..50b0e7c9ff7d 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1627,6 +1627,31 @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) } /* User-space CSR emulation */ +static int kvm_riscv_emu_sireg_ctx_load(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); + + return 0; +} + +static int kvm_riscv_emu_sireg_ctx_put(CPUState *cs) +{ + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); + + return 0; +} + struct kvm_riscv_emu_csr_data { target_ulong csr_num; int (*context_load)(CPUState *cs); @@ -1635,6 +1660,8 @@ struct kvm_riscv_emu_csr_data { struct kvm_riscv_emu_csr_data kvm_riscv_emu_csr_data[] = { { CSR_SEED, NULL, NULL }, + { CSR_SIREG, kvm_riscv_emu_sireg_ctx_load, kvm_riscv_emu_sireg_ctx_put }, + { CSR_STOPEI, NULL, NULL }, }; static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) From patchwork Mon Feb 24 08:24:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13987565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22A3CC021B5 for ; Mon, 24 Feb 2025 08:26:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmTlx-0000Qx-Fb; Mon, 24 Feb 2025 03:25:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmTlu-0000PO-ER for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:25:02 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmTlr-0001Dk-9m for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:25:01 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2211acda7f6so88002455ad.3 for ; Mon, 24 Feb 2025 00:24:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1740385498; x=1740990298; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=Avllbujkgt9jGISnFqk3eNbI7THZ3CoG/MVM08xKPXc=; b=W8fv9PZzCqws9eozHowe8oihEfIJQ6AXG5qmSOekS71HcoUEzdsrncpiENaPzqXJKB 2+t1BZzPT82Ta1V6ZsZBPl3CdbGR5+ER/nIlfUQjYcqqFf9jTiXP+Bbo3jGb2rZi1oxe KZMXe63JbS9TBydeA9lXlH5199SvL9ued00R1B7Gw72zJh+JO7y5i8uxD/oEkLTbauLG nJPXSWuN/IsOBK1DJbRdQpiuSRIShYN7cDHKkCuSbhUjMkHYHltXG+xh3huMmRzIZtPu y2RPr5QohXmG8OvahCpLCDibZmbEjD4Ow5Kmoiah3npWsNTTNzPhmRfDtNu1C/J86JYT DF7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740385498; x=1740990298; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Avllbujkgt9jGISnFqk3eNbI7THZ3CoG/MVM08xKPXc=; b=F7U/e7pR0cMIY9+1LllwgRj3BwHvHJOhOMH+YVhqN04VUOAo2XelriJfDBOqNF6Tc/ 5Yx1yK26mIJsokqbhy42Y1cr4g6saCIRf313BH7dhKiSEre2kaOQ/yVtlIr0bflVB8a7 undDl6VJZI0SDiGexxZ4Cx0Q2t9bYGvd0VuZfXq0CWKO+AxSN2yKREaGiuDbH14QTT96 jQVDQe42PrGsl1Cz158nQns8s+pXbKFc574LBtKLqLapQ+t2QA41wpfbWECx2AZ8sy/m H7NMCV+EmJSmR/9l26eb6k2F3jpPsK9mrvafBDiAPdRZXzYYTWaytCkiC+BBm0RGhKGP 8a0Q== X-Gm-Message-State: AOJu0YyX8gA+tMvWlqgDzexP+VNmckKJXLdfvT9XDbGq3GKgGTlVDJ11 hmzWsoS7iEXLgAZRImAtau7BYmEW72YHMNN+EarsAInj9jU+HhIgZbQkEqzQf59OKMC/EI8Of00 Vt95o8pGB47sVGHZwY6mZrFd4rLZfswMZEvom0Pyr/647ry+R3MMcwUqaEIYoRVY+BmsQ66L3XZ rEMNue1GEhWhoB7gpQhCxPPAUtsbHLme2sMUc+Ya9/pQ== X-Gm-Gg: ASbGnctWGtUKaJS4LzLOUnHwIHBIaO+6WzjTjENKPAjSr8SCEg7+DvXUv8cSUPzOH2b 1wk4qLOcA7LPjFNGyLnszo9Ze6Et+J8oH/qZ++Ujjw1gpQTVahLkmBvseUNWI8tYLdnSCNBwBFw Ulun6KiBkrmvzBSg1JLEYgoJM0hFxkhtPYofy4ynxZODS5eqsgkn7VE5OGJZT/MoBbCN5HK7dZ0 6OQFZbnpn3yty1Tx0v4+CNyqAntaKgjRV9IMx6Rqj5+fBwcaaoJd8LXi/fN4sSnv+IjccJt69rr trdW6WIEJyU5hL16Uogze9yUGw50N7gE7L4OfL6OKBoA9nZHj7QeixOj X-Google-Smtp-Source: AGHT+IHXVNbKiuaZi5hJilq5rfYkqfKJ1saB7u7EBGsYNKFH9pNciLVoY4TdM/LgkpwmuBmpcrzx9Q== X-Received: by 2002:a05:6a00:2e87:b0:732:2269:a15c with SMTP id d2e1a72fcca58-73426d8f207mr18199720b3a.20.1740385497562; Mon, 24 Feb 2025 00:24:57 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7325c88d74esm17714914b3a.149.2025.02.24.00.24.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 00:24:57 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Alistair Francis , Daniel Henrique Barboza Subject: [PATCH v2 7/8] docs: update the description about RISC-V AIA Date: Mon, 24 Feb 2025 16:24:14 +0800 Message-Id: <20250224082417.31382-8-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250224082417.31382-1-yongxuan.wang@sifive.com> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the description about "-accel kvm,kernel-irqchip=off" into docs/specs/riscv-aia.rst and docs/system/riscv/virt.rst. Signed-off-by: Yong-Xuan Wang --- docs/specs/riscv-aia.rst | 24 ++++++++++++++++++------ docs/system/riscv/virt.rst | 10 ++++++---- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/docs/specs/riscv-aia.rst b/docs/specs/riscv-aia.rst index 8097e2f89744..38797cca4998 100644 --- a/docs/specs/riscv-aia.rst +++ b/docs/specs/riscv-aia.rst @@ -25,11 +25,16 @@ When running KVM: - no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation regardless of the AIA mode chosen - with "aia=aplic", s-mode APLIC will be emulated by userspace -- with "aia=aplic-imsic" there are two possibilities. If no additional KVM option - is provided there will be no APLIC or IMSIC emulation in userspace, and the virtual - machine will use the provided in-kernel APLIC and IMSIC controllers. If the user - chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=split", - s-mode APLIC will be emulated while using the s-mode IMSIC from the irqchip +- with "aia=aplic-imsic" there are three possibilities. + - If no additional KVM option is provided there will be no APLIC or IMSIC emulation + in userspace, and the virtual machine will use the provided in-kernel APLIC and + IMSIC controllers. + - If the user chooses to use the irqchip in split mode via + "-accel kvm,kernel-irqchip=split", s-mode APLIC will be emulated while using + the s-mode IMSIC from the irqchip. + - If the user disables the in-kernel irqchip via "-accel kvm,kernel-irqchip=off", + both s-mode APLIC and IMSIC controller will be emulated. + The following table summarizes how the AIA and accelerator options defines what we will emulate in userspace: @@ -75,9 +80,16 @@ we will emulate in userspace: - in-kernel - in-kernel * - kvm - - irqchip=split + - kernel-irqchip=split - aplic-imsic - n/a - n/a - emul - in-kernel + * - kvm + - kernel-irqchip=off + - aplic-imsic + - n/a + - n/a + - emul + - emul diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 60850970ce83..96d7ee1ebc64 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -129,12 +129,14 @@ The following machine-specific options are supported: MSIs. When not specified, this option is assumed to be "none" which selects SiFive PLIC to handle wired interrupts. - This option also interacts with '-accel kvm'. When using "aia=aplic-imsic" - with KVM, it is possible to set the use of the kernel irqchip in split mode + This option also interacts with '-accel kvm', when using "aia=aplic-imsic" + with KVM. It is possible to set the use of the kernel irqchip in split mode by using "-accel kvm,kernel-irqchip=split". In this case the ``virt`` machine will emulate the APLIC controller instead of using the APLIC controller from - the irqchip. See :ref:`riscv-aia` for more details on all available AIA - modes. + the in-kernel irqchip. Or the kernel irqchip can be disabled by using + "-accel kvm,kernel-irqchip=off". In this case the ``virt`` machine will + emulate the APLIC and IMSIC controller in user-space instead of using in-kernel + irqchip. See :ref:`riscv-aia` for more details on all available AIA modes. - aia-guests=nnn From patchwork Mon Feb 24 08:24:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13987568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E7F6C021B6 for ; Mon, 24 Feb 2025 08:26:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmTmD-0000io-Hr; Mon, 24 Feb 2025 03:25:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmTlx-0000Uf-7s for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:25:05 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmTlv-0001Em-DE for qemu-devel@nongnu.org; Mon, 24 Feb 2025 03:25:04 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2211acda7f6so88003185ad.3 for ; Mon, 24 Feb 2025 00:25:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1740385502; x=1740990302; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=YYEOMkvva/1IHr6h82yrTDeY/QvDiMhqXdSRY7LyxdI=; b=ZzjgeGeniXjW/8do6Mn39fmhsG2KwTK6mdByVxEoFtFeN3kFRqv1V6YU9kUAMcQHsi W6rrRF66/RxGwi3kSn2+Y8aFAOr8KqNsobVrNeDYEF0PSgdSasQHk6yZW0a4tssnvJ5M UZ8H0YmZ9O+RmXHal/DsV9AHhH6iiR1R8RxIMhw1aBJNMA8flThbrlTlkF2N4/Lc2St/ wExBxmti5a4BmuGCogOEjpbfqGaoDSGnCITmgg4P07Dt3n+ynodozKIZeMSX06djvyP7 xFd+oR1M3sL7cK/a0r9ARLMTo8h3Wnb9fSPYz9NuSpJ3KRKRn8Sed86rEDiMV9ueTN6d /m0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740385502; x=1740990302; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YYEOMkvva/1IHr6h82yrTDeY/QvDiMhqXdSRY7LyxdI=; b=VbkSO1mjyOG6gSnfdU02b95BANMhaamOKrjvljmbg5gJ0+Q4PQReqNvfk5Qh0Vxk0C Oz0UrLhfmGu70/6ZGj4fnsh8hM4wRnqW/BZoRCPLfc1DpGKzDgYKf7arSod4HPTzZfiE 0+1l4j6mRQ/dV4PAl4HIC51syRCoP+7kvZAehCu7CjCX7tkLhrbFsTjJn0jIwn7CvHAN /Xe0myD730ZpD5J9JQ+1CSReeG6u/SINcpj8mkxpFAVTg7A4DGxc9ShUlSGPJaQKEtxE 5dn8uzJYbqcaPepqUmolOodE9/CK9gySLoLSeQxj7YVcPY8q2wTE4COqvL8WKLCJCuAL 1AOA== X-Gm-Message-State: AOJu0YylSJfwFxNmfGo6PD9MUPuJHkg24PTWLShKvn3Jv9K8N0p/BzGs CU0oIBu59i9Kig3d3fyGdONSifmVJSuHrAPMTJabkYkwdsiDP4l6Gaq0dOM/eM/z/rqqAI8gsPw B0SJSOLMSJPl9PaDOvmVPQbWAHm8mP2g3uUsPywWzWInXMdmrucKRsCimMhrd950RYsvmjs6AfP uuNX0M2Bib5N4IAeKyT3ieUIKxf11X4FtSpsuPlNmlCQ== X-Gm-Gg: ASbGncubO6S3GCHtkyJkwCjokT1BIPWNG/2dOV//gt6woZ/L3rdzRjdSuoizr4JfMkz b6Ax0rihjCLmJCjrEJXSYieFmc4Pyc9xJUa7ZriN06OdKSDZbzAx9Fti0xwN3q0mz06ZsZM/Q0V 5dOSn1mFBfCaQPe2k8VlcPP/x0oP66JYRofA/dMO+l93GnPlwlWQhUMmJNr0xd8uRbZ8Okcylch YXsRSBsRrHs96+mdCFCqm4GlxM4z/6GhuOLG3dP2c/LQ1Q5H5u49UEgM95xe85GkLHmjE4Uux50 WueMF3LuihWPYh/F9NqgFd9A1b6CdCEArM3NFvzqb65WkXD016JUUuhc X-Google-Smtp-Source: AGHT+IHqru5QSjb9BmEx2XWBaNez57R75JTp0uS3W11selVagBhbIoeymiUkALT2yo/ICfOQA+nkcA== X-Received: by 2002:a05:6a00:8c2:b0:730:7d3f:8c6c with SMTP id d2e1a72fcca58-73426d9002cmr18051654b3a.22.1740385501536; Mon, 24 Feb 2025 00:25:01 -0800 (PST) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7325c88d74esm17714914b3a.149.2025.02.24.00.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 00:25:01 -0800 (PST) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH v2 8/8] hw/intc/imsic: prevent to use IMSIC when host doesn't support AIA extension Date: Mon, 24 Feb 2025 16:24:15 +0800 Message-Id: <20250224082417.31382-9-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250224082417.31382-1-yongxuan.wang@sifive.com> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently QEMU will continue to create the IMSIC devices and enable the AIA extension for guest OS when the host kernel doesn't support the AIA extension. This will cause an illegal instruction exception when the guest OS access the AIA CSRs. Add additional checks to ensure the guest OS only uses the IMSIC devices when the host kernel supports the AIA extension. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_imsic.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index dc8162c0a7c9..8c64f2c21274 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -375,12 +375,21 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp) /* Force select AIA feature and setup CSR read-modify-write callback */ if (env) { - if (!imsic->mmode) { - rcpu->cfg.ext_ssaia = true; - riscv_cpu_set_geilen(env, imsic->num_pages - 1); + if (kvm_enabled()) { + if (!rcpu->cfg.ext_ssaia) { + error_report("Host machine doesn't support AIA extension. " + "Do not use IMSIC as interrupt controller."); + exit(1); + } } else { - rcpu->cfg.ext_smaia = true; + if (!imsic->mmode) { + rcpu->cfg.ext_ssaia = true; + riscv_cpu_set_geilen(env, imsic->num_pages - 1); + } else { + rcpu->cfg.ext_smaia = true; + } } + riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, riscv_imsic_rmw, imsic); }