From patchwork Mon Feb 24 11:15:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4228C3ABA0 for ; Mon, 24 Feb 2025 11:16:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWQx-0005lG-U2; Mon, 24 Feb 2025 06:15:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWQv-0005k7-GE for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:33 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWQs-00016K-Sk for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:33 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-439350f1a0bso24832235e9.0 for ; Mon, 24 Feb 2025 03:15:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395729; x=1741000529; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HZT+zqMwNV0ANCeiQYhCRnbICr4LNPcjXGyJPDnAa04=; b=g0ngLrcvBffh3xAy9M9AIzHL0gI5xMvtwyzXU/+wrRlJTk5PwajB2m/1qU1INwpYFp D10X7pJIvuA6AMWKk6zsBoDCof8m1D09mBm3AUHnmqg2RYAuQfWGlNygsKuMV/HcE8zJ /v0suUuHxCbLua30RAEsi/EDILbzPwQ3+0wKyLsW5uC59AjEXfmbDg1i5U2ST6Y8E3CF ODp1PHHKQ3qRMg2hwRx/wVBMS8Lqx50rsfWxU2DOfATqzgK8ln+jUl3QcEPB2gjOF+Yz N7LweDNqSOTVxzG/tNnNL/ZMgEqn19XAZtYmhdZE+/vFcrxulA/pzt2e9qbPcVyY5BMi yCvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395729; x=1741000529; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HZT+zqMwNV0ANCeiQYhCRnbICr4LNPcjXGyJPDnAa04=; b=pUNkC5SJPJ1VmPtwHAGsbM063/P++qfQlDHYnvK6tmPAwSTe7k0AcAC+ehIG4GFGaD g4AeyyCb0bxLHI0k/sSAp8v1wVb9Js5PkZwA2vJ2TMjILi0iEuHrOYI84uz1c/oTP0/Y zXyIkhQBqYnpsz9Ra0c6jf4ynxGDgJoSQR5dss6Nd8tGVtMUxN9JTPrPAhxMQHZtK9ws T/SPYe0b5XXK/2EK6Z8e/B8j7rfrXZi4voZQJXs9ibQOQi41DC9rgf8BRZHcC+ug+pFL A91Tv9OrPdq+jIS7BwmIDTy+Z6Mk6g3lKFUcxFoCIhNaGnEpo1Bt6fB9WCKRnANaVdqt PKlQ== X-Gm-Message-State: AOJu0YzxlVMyOdROxzikgpuAqMgNieXufJrkWXcaQURtMQ0TH6HTnQzo IpbbPZ/T5QG8H8ZttxwUne1dI7aj+xYcPccZvcsnZOrygvNnqNZeTlDLRXsOYfDsLy/tSpp0GUu Y X-Gm-Gg: ASbGncuDY1vS0ahxc+y/YjPbpd+tJ7NPsnxAFMjAxr33C/kf+GnJgbKC2uwx344GexQ jsovnzk2JIosB1qcYRzhtd2xAGr8SCSskSDAKAgy8lRTaiEseG1kEOidW1buTehKEs1In0Bpu2b RmTgr890QgA8P6R4c/S0+GwSOwJpFJnipg6LxCo+4PCwGweclOqiUmGgT5bELNAvrPMuL9aMj2k LU1kpIgpKFNb8D6gXAfDPlYIQ0OBrI17jUrrWXWRXA6vktEX0yQaLWvAVIJeyCjJ8TWtjWG2GNY dqBERgUsOsCkmQYNHVyKqWH+qfJQQCHp X-Google-Smtp-Source: AGHT+IGCAiMd1THK1R2i4UpG2QOn/WRHxFgUW0bCidS2Xyji3RaWrwlLya1asNloMW/Gi6jFxiMJVQ== X-Received: by 2002:a05:600c:4e8d:b0:439:892c:dfd0 with SMTP id 5b1f17b1804b1-439a30e91femr142071915e9.14.1740395729114; Mon, 24 Feb 2025 03:15:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 01/12] fpu: Make targets specify floatx80 default Inf at runtime Date: Mon, 24 Feb 2025 11:15:13 +0000 Message-ID: <20250224111524.1101196-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently we hardcode at compile time whether the floatx80 default Infinity value has the explicit integer bit set or not (x86 sets it; m68k does not). To be able to compile softfloat once for all targets we'd like to move this setting to runtime. Define a new FloatX80Behaviour enum which is a set of flags that define the target's floatx80 handling. Initially we define just one flag, for whether the default Infinity has the Integer bit set or not, but we will expand this in future commits to cover the other floatx80 target specifics that we currently make compile-time settings. Define a new function floatx80_default_inf() which returns the appropriate default Infinity value of the given sign, and use it in the code that was previously directly using the compile-time constant floatx80_infinity_{low,high} values when packing an infinity into a floatx80. Since floatx80 is highly unlikely to be supported in any new architecture, and the existing code is generally written as "default to like x87, with an ifdef for m68k", we make the default value for the floatx80 behaviour flags be "what x87 does". This means we only need to change the m68k target to specify the behaviour flags. (Other users of floatx80 are the Arm NWFPE emulation, which is obsolete and probably not actually doing the right thing anyway, and the PPC xsrqpxp insn. Making the default be "like x87" avoids our needing to review and test for behaviour changes there.) We will clean up the remaining uses of the floatx80_infinity global constant in subsequent commits. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250217125055.160887-2-peter.maydell@linaro.org --- include/fpu/softfloat-helpers.h | 12 ++++++++++++ include/fpu/softfloat-types.h | 13 +++++++++++++ include/fpu/softfloat.h | 1 + fpu/softfloat.c | 7 +++---- target/m68k/cpu.c | 6 ++++++ fpu/softfloat-specialize.c.inc | 10 ++++++++++ 6 files changed, 45 insertions(+), 4 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 8983c2748ec..90862f5cd22 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -75,6 +75,12 @@ static inline void set_floatx80_rounding_precision(FloatX80RoundPrec val, status->floatx80_rounding_precision = val; } +static inline void set_floatx80_behaviour(FloatX80Behaviour b, + float_status *status) +{ + status->floatx80_behaviour = b; +} + static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, float_status *status) { @@ -151,6 +157,12 @@ get_floatx80_rounding_precision(const float_status *status) return status->floatx80_rounding_precision; } +static inline FloatX80Behaviour +get_floatx80_behaviour(const float_status *status) +{ + return status->floatx80_behaviour; +} + static inline Float2NaNPropRule get_float_2nan_prop_rule(const float_status *status) { diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 53d5eb85210..dd22ecdbe60 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -320,6 +320,18 @@ typedef enum __attribute__((__packed__)) { float_ftz_before_rounding = 1, } FloatFTZDetection; +/* + * floatx80 is primarily used by x86 and m68k, and there are + * differences in the handling, largely related to the explicit + * Integer bit which floatx80 has and the other float formats do not. + * These flag values allow specification of the target's requirements + * and can be ORed together to set floatx80_behaviour. + */ +typedef enum __attribute__((__packed__)) { + /* In the default Infinity value, is the Integer bit 0 ? */ + floatx80_default_inf_int_bit_is_zero = 1, +} FloatX80Behaviour; + /* * Floating Point Status. Individual architectures may maintain * several versions of float_status for different functions. The @@ -331,6 +343,7 @@ typedef struct float_status { uint16_t float_exception_flags; FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; + FloatX80Behaviour floatx80_behaviour; Float2NaNPropRule float_2nan_prop_rule; Float3NaNPropRule float_3nan_prop_rule; FloatInfZeroNaNRule float_infzeronan_rule; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 09a40b43106..afae3906024 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -961,6 +961,7 @@ float128 floatx80_to_float128(floatx80, float_status *status); | The pattern for an extended double-precision inf. *----------------------------------------------------------------------------*/ extern const floatx80 floatx80_infinity; +floatx80 floatx80_default_inf(bool zSign, float_status *status); /*---------------------------------------------------------------------------- | Software IEC/IEEE extended double-precision operations. diff --git a/fpu/softfloat.c b/fpu/softfloat.c index f4fed9bfda9..b12ad2b42a9 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1860,7 +1860,8 @@ static floatx80 floatx80_round_pack_canonical(FloatParts128 *p, case float_class_inf: /* x86 and m68k differ in the setting of the integer bit. */ - frac = floatx80_infinity_low; + frac = s->floatx80_behaviour & floatx80_default_inf_int_bit_is_zero ? + 0 : (1ULL << 63); exp = fmt->exp_max; break; @@ -5144,9 +5145,7 @@ floatx80 roundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign, ) { return packFloatx80( zSign, 0x7FFE, ~ roundMask ); } - return packFloatx80(zSign, - floatx80_infinity_high, - floatx80_infinity_low); + return floatx80_default_inf(zSign, status); } if ( zExp <= 0 ) { isTiny = status->tininess_before_rounding diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 41dfdf58045..df66e8ba22a 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -107,6 +107,12 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); /* Default NaN: sign bit clear, all frac bits set */ set_float_default_nan_pattern(0b01111111, &env->fp_status); + /* + * m68k-specific floatx80 behaviour: + * * default Infinity values have a zero Integer bit + */ + set_floatx80_behaviour(floatx80_default_inf_int_bit_is_zero, + &env->fp_status); nan = floatx80_default_nan(&env->fp_status); for (i = 0; i < 8; i++) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index cbbbab52ba3..73789e97d77 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -227,6 +227,16 @@ floatx80 floatx80_default_nan(float_status *status) | The pattern for a default generated extended double-precision inf. *----------------------------------------------------------------------------*/ +floatx80 floatx80_default_inf(bool zSign, float_status *status) +{ + /* + * Whether the Integer bit is set in the default Infinity is + * target dependent. + */ + bool z = status->floatx80_behaviour & floatx80_default_inf_int_bit_is_zero; + return packFloatx80(zSign, 0x7fff, z ? 0 : (1ULL << 63)); +} + #define floatx80_infinity_high 0x7FFF #if defined(TARGET_M68K) #define floatx80_infinity_low UINT64_C(0x0000000000000000) From patchwork Mon Feb 24 11:15:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D962C021A4 for ; Mon, 24 Feb 2025 11:18:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWR1-0005le-Ci; Mon, 24 Feb 2025 06:15:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWQw-0005kU-OW for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:34 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWQu-00016T-IV for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:34 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4397e5d5d99so25587055e9.1 for ; Mon, 24 Feb 2025 03:15:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395731; x=1741000531; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hQQOJkRUKcXKg+lYwbMPTfL+5pbfMb4jgTyc1o/Pekg=; b=wfb9VwSTLT1S6WJyRl96MWRVjrY1osZH5TaRd5o8XJPvn2v1LUpfKilGmtNhkU8DOU +2kxU4eHFx72r56P+WHsj7VshzD6PpeqpsdYE/G0SNaCctJWpAG8jEmTsgDpwC7mq8Y2 IisKSQGEI2US+BMekd8opLKyvbgTJlgdh+Nl9L5wpMNJ4j1rpPkODuT0P6x9kgwGj2cv qxwfQRXOs91gYpFPJDl+HNirwHtmPet7QGJA9Awuu3X7c+9xIrKHGVXTJ8VRuIyjRu1+ 6rtOWd7XVCXa65MqLFoGSJwMr9ESqMzDPa1p+oNpqAJGUx/kvGlyBHuAQJA06UszfEl5 ztTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395731; x=1741000531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hQQOJkRUKcXKg+lYwbMPTfL+5pbfMb4jgTyc1o/Pekg=; b=I1xjZbWhEvAKNIrSLsegp4MnMB9x5lISMb1uTNcqdavezdz8z6e3iLyeUSlrt/ADmA xGt3NfQR9gVfDpnwC/fMChmeUnx5/9dHknTqeaHKj1oDFlXursjxty4Vk1woAFEoVnKX RzwybFwZccYgxSGVjmx+pFuE3NZCXZLZ8VMUeYRAt/4pxrJPzAFhszOmBrGQzVIrKrt4 Id/CN0hoXnIAsg4zbf5g02FwrPD1B+za83xIjbM3ct5TGqRZ4l+WmHKS2DPo2zeetkYL o+FaQ4BoorAfktK0ayJvmGW1K56k1klwFeWJSJ9mA62xngUPCySLKoI8VuYwIVJe7Dly Rjug== X-Gm-Message-State: AOJu0YwaudKT3pUmyWjVNcyEWUzb/PRPSXMWJfwLQ6nKakI8bkKLYh+k WWfWRr3I2B+LX2cjeeNQTB16uOdbouHwbEwPO5s2zZ16fTr+5h8lDAOQcLld0ISsJ8T1iSbjM0C 0 X-Gm-Gg: ASbGncsTURkvRgylLrdKNfS2xqbJzJzuReAjyBS1OeAzsqfbIJWr8QnbJiMGETkwzVE MoDKZ4HgWzus5S/0n/byg7vpvC6JF0eKSM2SMIwYP9jm215AMcbXNcVZ3/QWqseMQ95k8Qi+JoY 0ZVe/G+fzSx0bztUVA+uONt2iZScXxgLkDAyhrc51sDsVOgAjmZtnrFAhHj2DH/kuMTZjYa7SJr 6aSMR0hmR0GxkBFS/KrFk0GHRyVagPIM6CNqMZDwStM9GCM9LQZbVQU6HT8r1tm2aP/kd5HVYfl Paqahzolo6wgBgAlH/ymJivGd4vV56An X-Google-Smtp-Source: AGHT+IGpI9FhhRyXvGbb/DLnbHbcLRtd+7sIr/hM5hfPWVeY0JCBenbyh8nlhnjl20Hi4xIjG1dzGg== X-Received: by 2002:a05:600c:4f02:b0:439:9828:c425 with SMTP id 5b1f17b1804b1-439ae1e5b56mr101768765e9.7.1740395730219; Mon, 24 Feb 2025 03:15:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 02/12] target/m68k: Avoid using floatx80_infinity global const Date: Mon, 24 Feb 2025 11:15:14 +0000 Message-ID: <20250224111524.1101196-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The global const floatx80_infinity is (unlike all the other float*_infinity values) target-specific, because whether the explicit Integer bit is set or not varies between m68k and i386. We want to be able to compile softfloat once for multiple targets, so we can't continue to use a single global whose value needs to be different between targets. Replace the direct uses of floatx80_infinity in target/m68k with calls to the new floatx80_default_inf() function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250217125055.160887-3-peter.maydell@linaro.org --- target/m68k/softfloat.c | 47 ++++++++++++++--------------------------- 1 file changed, 16 insertions(+), 31 deletions(-) diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index 02dcc03d15d..d1f150e641f 100644 --- a/target/m68k/softfloat.c +++ b/target/m68k/softfloat.c @@ -142,8 +142,7 @@ floatx80 floatx80_scale(floatx80 a, floatx80 b, float_status *status) if ((uint64_t) (aSig << 1)) { return propagateFloatx80NaN(a, b, status); } - return packFloatx80(aSign, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(aSign, status); } if (aExp == 0) { if (aSig == 0) { @@ -245,7 +244,7 @@ floatx80 floatx80_lognp1(floatx80 a, float_status *status) float_raise(float_flag_invalid, status); return floatx80_default_nan(status); } - return packFloatx80(0, floatx80_infinity.high, floatx80_infinity.low); + return floatx80_default_inf(0, status); } if (aExp == 0 && aSig == 0) { @@ -255,8 +254,7 @@ floatx80 floatx80_lognp1(floatx80 a, float_status *status) if (aSign && aExp >= one_exp) { if (aExp == one_exp && aSig == one_sig) { float_raise(float_flag_divbyzero, status); - return packFloatx80(aSign, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(aSign, status); } float_raise(float_flag_invalid, status); return floatx80_default_nan(status); @@ -442,8 +440,7 @@ floatx80 floatx80_logn(floatx80 a, float_status *status) propagateFloatx80NaNOneArg(a, status); } if (aSign == 0) { - return packFloatx80(0, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(0, status); } } @@ -452,8 +449,7 @@ floatx80 floatx80_logn(floatx80 a, float_status *status) if (aExp == 0) { if (aSig == 0) { /* zero */ float_raise(float_flag_divbyzero, status); - return packFloatx80(1, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(1, status); } if ((aSig & one_sig) == 0) { /* denormal */ normalizeFloatx80Subnormal(aSig, &aExp, &aSig); @@ -610,15 +606,13 @@ floatx80 floatx80_log10(floatx80 a, float_status *status) propagateFloatx80NaNOneArg(a, status); } if (aSign == 0) { - return packFloatx80(0, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(0, status); } } if (aExp == 0 && aSig == 0) { float_raise(float_flag_divbyzero, status); - return packFloatx80(1, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(1, status); } if (aSign) { @@ -668,16 +662,14 @@ floatx80 floatx80_log2(floatx80 a, float_status *status) propagateFloatx80NaNOneArg(a, status); } if (aSign == 0) { - return packFloatx80(0, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(0, status); } } if (aExp == 0) { if (aSig == 0) { float_raise(float_flag_divbyzero, status); - return packFloatx80(1, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(1, status); } normalizeFloatx80Subnormal(aSig, &aExp, &aSig); } @@ -740,8 +732,7 @@ floatx80 floatx80_etox(floatx80 a, float_status *status) if (aSign) { return packFloatx80(0, 0, 0); } - return packFloatx80(0, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(0, status); } if (aExp == 0 && aSig == 0) { @@ -924,8 +915,7 @@ floatx80 floatx80_twotox(floatx80 a, float_status *status) if (aSign) { return packFloatx80(0, 0, 0); } - return packFloatx80(0, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(0, status); } if (aExp == 0 && aSig == 0) { @@ -1075,8 +1065,7 @@ floatx80 floatx80_tentox(floatx80 a, float_status *status) if (aSign) { return packFloatx80(0, 0, 0); } - return packFloatx80(0, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(0, status); } if (aExp == 0 && aSig == 0) { @@ -2260,8 +2249,7 @@ floatx80 floatx80_atanh(floatx80 a, float_status *status) if (compact >= 0x3FFF8000) { /* |X| >= 1 */ if (aExp == one_exp && aSig == one_sig) { /* |X| == 1 */ float_raise(float_flag_divbyzero, status); - return packFloatx80(aSign, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(aSign, status); } else { /* |X| > 1 */ float_raise(float_flag_invalid, status); return floatx80_default_nan(status); @@ -2320,8 +2308,7 @@ floatx80 floatx80_etoxm1(floatx80 a, float_status *status) if (aSign) { return packFloatx80(aSign, one_exp, one_sig); } - return packFloatx80(0, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(0, status); } if (aExp == 0 && aSig == 0) { @@ -2687,8 +2674,7 @@ floatx80 floatx80_sinh(floatx80 a, float_status *status) if ((uint64_t) (aSig << 1)) { return propagateFloatx80NaNOneArg(a, status); } - return packFloatx80(aSign, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(aSign, status); } if (aExp == 0 && aSig == 0) { @@ -2774,8 +2760,7 @@ floatx80 floatx80_cosh(floatx80 a, float_status *status) if ((uint64_t) (aSig << 1)) { return propagateFloatx80NaNOneArg(a, status); } - return packFloatx80(0, floatx80_infinity.high, - floatx80_infinity.low); + return floatx80_default_inf(0, status); } if (aExp == 0 && aSig == 0) { From patchwork Mon Feb 24 11:15:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1B82C021A4 for ; Mon, 24 Feb 2025 11:16:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWR0-0005lr-K3; Mon, 24 Feb 2025 06:15:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWQw-0005kV-P9 for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:34 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWQu-00016c-SI for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:34 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4394036c0efso25741625e9.2 for ; Mon, 24 Feb 2025 03:15:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395731; x=1741000531; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9DbKOvjmlaa+eK1MxGX4jbLYMxjD78KrF+C7Cfab4aQ=; b=bSjtL5+THtnPiuPJAuWhlqnOAIM8bHkhP1gwdFuzmtUXe+PY3QDHestA1qJpIPerCt 6cmWx7IlsHvFPGCu93zEniU+O3GzuNn7F9f5j2FHrmb/z199ZEduOpHMHRB2A3BrpOX2 dlWZujhgMNOO0cmVa2wsBpTVKBEoCW7t4HQiaknQd53WNvJ4prDXDfZVz1jrU/oHzGYi EAnO7VRLsqnpaFPpxowODycIS6iJNiSyMoP0dhFyY5Pbl4ers7rbOvjJce50iHMsiRS2 CvvWK9bd8m/n1dF2xX6F48Wkuz2A9XD5Pt2scnUCg5PgxPBMA0v0m/VvEu9Supy5H94l GmJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395731; x=1741000531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9DbKOvjmlaa+eK1MxGX4jbLYMxjD78KrF+C7Cfab4aQ=; b=rmzWRUtozGsF0f/mQiC9psCzUjIBuRfmazYpOjygFDYjtZcgktaq4UPvF1pzzdu7WN DQ93k0yVK0kTRsZB1Lw+AxtgaVzVuYh1faJNmG0F6x3UnY25kV6EF7i2B1bpetJMcuyb fRjCM+lWYFImAYnqpBGF3RORKDrtpXnNbwEc/8MHnDdZZl8sCpsUpI7LW2fA6GqRdbso hOdhqqx2HoyQ2cgHnKrTA/HmduHgTygvxYJbrXXwoeItJy+9tCUut4aEMxnKecuodMGC mzn8iw3/OR/yFiAWhdai/MmtejblmCtGHs+6/x+HVoqMPYrKOTqbPbEqKLdXhE1KWUw3 stYQ== X-Gm-Message-State: AOJu0YyQEaLI4rGxGfuE9EOqjhfrYOpcuxfAWTrptm28Bc33YtdKt4BZ LDJYU9Oas1m7VsoJvxiNzX1s/rqBQdrBj7ETV6YHRqBRBU+psw69YjXGCqd8hKiqRwX9hBScq/F s X-Gm-Gg: ASbGncuTUSbVeClShmaZbOEgNI8qmkyf39aWJYJEDPJ2b2f2Z5Id8pQnwh7qwhIgUQC mspgQDLKOnee/P3caloentrP+R2Yw3GzO3b4W9aJk3VYlBIxeAvlBDBaO1GCaykD2BqEhYBhDHN M1HyyB2V7PdVG7GwOoNTM5SBsY0WkPfpeCuk5w0+xrG2Y5FPrnIz2e8XjNXrRXlSu/JXv7XSrFA cyvwykYtPP+jK6CKMryrfCbCGKkKB3rvz3Uh7I1IsfAYXhVEMu6TVW5+k2DkHUzgdUyR/HDjfmf szH8RwwxSmicr5HvJcDv9QYp1lnPMrjd X-Google-Smtp-Source: AGHT+IFqa9cvjdMXpfNqTskBMd1pB+u7MuX2hjWWcEPLUN/nBD6I098848BdMBYmacPpNIzr9a7MIA== X-Received: by 2002:a05:600c:1c85:b0:439:8346:505f with SMTP id 5b1f17b1804b1-439ae212980mr93119685e9.20.1740395731147; Mon, 24 Feb 2025 03:15:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 03/12] target/i386: Avoid using floatx80_infinity global const Date: Mon, 24 Feb 2025 11:15:15 +0000 Message-ID: <20250224111524.1101196-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The global const floatx80_infinity is (unlike all the other float*_infinity values) target-specific, because whether the explicit Integer bit is set or not varies between m68k and i386. We want to be able to compile softfloat once for multiple targets, so we can't continue to use a single global whose value needs to be different between targets. Replace the direct uses of floatx80_infinity in target/i386 with calls to the new floatx80_default_inf() function. Note that because we can ask the function for either a negative or positive infinity, we don't need to change the sign of a positive infinity via floatx80_chs() for the negative-Inf case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250217125055.160887-4-peter.maydell@linaro.org --- target/i386/tcg/fpu_helper.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index f112c6c6737..741af09f908 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -1832,7 +1832,7 @@ void helper_fxtract(CPUX86State *env) } else if (floatx80_is_infinity(ST0)) { fpush(env); ST0 = ST1; - ST1 = floatx80_infinity; + ST1 = floatx80_default_inf(0, &env->fp_status); } else { int expdif; @@ -2358,9 +2358,8 @@ void helper_fscale(CPUX86State *env) float_raise(float_flag_invalid, &env->fp_status); ST0 = floatx80_default_nan(&env->fp_status); } else { - ST0 = (floatx80_is_neg(ST0) ? - floatx80_chs(floatx80_infinity) : - floatx80_infinity); + ST0 = floatx80_default_inf(floatx80_is_neg(ST0), + &env->fp_status); } } } else { From patchwork Mon Feb 24 11:15:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06A60C021A4 for ; Mon, 24 Feb 2025 11:16:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWR2-0005n5-By; Mon, 24 Feb 2025 06:15:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWQx-0005lH-W5 for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:36 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWQw-00017C-0v for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:35 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4398ec2abc2so37231415e9.1 for ; Mon, 24 Feb 2025 03:15:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395732; x=1741000532; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UAfkc5L9phFc4GuGJcjEeCq2ljrLeE9IXM1AAE+CUQ4=; b=nINMGQsqopHQwGq102mHWfJ/y7t3kgSv7wEn4jEREBSxlvuX2eNlop/7/VSdAEq5cA l0SK/77JrdV/x30wOQeYfbE6dVIWotcCCZBP1b/X5+yWguyaYsYcmVJqvKcxJkKs/nyP 4SI/dznoHfwIY31tOaOXnm31W0Upv+F6y3LitfXuJapsHmaHOrN/klwigMcE78Eo/Ohe wofTE23KYDH+T4GLH2hU1pTYknzjXuKFUhnSzw8j/FONm68TFmCJinKQEQk84RWrVQ2/ kKLA7lO2tIAOU5lYTRkT4Y2vZRwlkn+HxvDJ29s+rxmB0x33ITxdWjPWBnEbrALmVXzq 0sCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395732; x=1741000532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UAfkc5L9phFc4GuGJcjEeCq2ljrLeE9IXM1AAE+CUQ4=; b=Mo0zUKZCBHj6T9RpE9HRQ5QXzefdAS6pzYiD9XejLjwpaBjzHrA/raUQtfjHcuQwmy jIVOpy1Rw+PVGkEa9WUTsLKKlo+tGJ1+TBr8POaEJER5cQs1vdD6TompMC1pkPmAVjWE hTwlIfxtFOyI0UpH5yAVYfil4WJ4RVErAt1STKyuNoLZD6c4zJ4OboD51rvYm05YZAkn xHlW4sdfj3QgZxvvA3rK5K9qPwU5Y1jHh8tk0jwk6AC58YdaPgPsy5qdKCbOLrqcBUBG sqq4GvW875PU/WOX54dBneRyGyCOOR7+chINQ2bl2uT3l3rqODaL2DohVI0CpSRr92Kj W1XQ== X-Gm-Message-State: AOJu0Yyz8BikTanbdMu44FEMVsGTbgwx+Gdxy4Bv8XS9H/+q5w89PolS NkWhUqxufevH+rweJIB6R8qU5IiTB3uZnnmPbIE49lj0MKdcaFkKUq/obdCGAVAchIEUQTkVGfk l X-Gm-Gg: ASbGnct/PL+JLwAoeXGBGQgi1eI/gAXYQHxMeFXfvd93Q5isB8hXcrU90IBsa4/PJ3N KIDpMo/obvREPzIaCN+llC1SC8BLhE/vMcIkk+2bYKiRkcLnxyju4/W7jy6+BZGkwe1/G3Hno9K FkUg62zsUrdtW+BfsqXFhFHNIzfSIsaeTptL6hcZEwocpv9zS2ResWveajeVrL8ctRSgLsDSEAR QCRmC7TVzU8SfPubuO9GPCS7n+fZolMmqiCoHBnWXbxtNiDIxlkpNjbfYW85fmrRTiv+R1W1Bx4 nzypYMgC/X3ZNge0+gr9+GSU4Kv6hIVv X-Google-Smtp-Source: AGHT+IG04jQnVU67aSrrf9WAiusmPeaa8yIHqvAHB0cvQut7NYCEOl+FY8aasrW4pTNPV2qTfjBaIg== X-Received: by 2002:a05:600c:4e8c:b0:439:6712:643d with SMTP id 5b1f17b1804b1-439ae1e6c15mr90435965e9.9.1740395732095; Mon, 24 Feb 2025 03:15:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 04/12] fpu: Pass float_status to floatx80_is_infinity() Date: Mon, 24 Feb 2025 11:15:16 +0000 Message-ID: <20250224111524.1101196-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Unlike the other float formats, whether a floatx80 value is considered to be an Infinity is target-dependent. (On x86 if the explicit integer bit is clear this is a "pseudo-infinity" and not a valid infinity; m68k does not care about the value of the integer bit.) Currently we select this target-specific logic at compile time with an ifdef. We're going to want to do this at runtime, so change the floatx80_is_infinity() function to take a float_status. This commit doesn't change any logic; we'll do that in the next commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/fpu/softfloat.h | 2 +- target/i386/tcg/fpu_helper.c | 20 +++++++++++--------- target/m68k/fpu_helper.c | 2 +- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index afae3906024..3c83d703baf 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -996,7 +996,7 @@ static inline floatx80 floatx80_chs(floatx80 a) return a; } -static inline bool floatx80_is_infinity(floatx80 a) +static inline bool floatx80_is_infinity(floatx80 a, float_status *status) { #if defined(TARGET_M68K) return (a.high & 0x7fff) == floatx80_infinity.high && !(a.low << 1); diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 741af09f908..3b79bc049d1 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -1393,7 +1393,8 @@ void helper_fpatan(CPUX86State *env) /* Pass this NaN through. */ } else if (floatx80_is_zero(ST1) && !arg0_sign) { /* Pass this zero through. */ - } else if (((floatx80_is_infinity(ST0) && !floatx80_is_infinity(ST1)) || + } else if (((floatx80_is_infinity(ST0, &env->fp_status) && + !floatx80_is_infinity(ST1, &env->fp_status)) || arg0_exp - arg1_exp >= 80) && !arg0_sign) { /* @@ -1442,8 +1443,8 @@ void helper_fpatan(CPUX86State *env) rexp = pi_exp; rsig0 = pi_sig_high; rsig1 = pi_sig_low; - } else if (floatx80_is_infinity(ST1)) { - if (floatx80_is_infinity(ST0)) { + } else if (floatx80_is_infinity(ST1, &env->fp_status)) { + if (floatx80_is_infinity(ST0, &env->fp_status)) { if (arg0_sign) { rexp = pi_34_exp; rsig0 = pi_34_sig_high; @@ -1462,7 +1463,8 @@ void helper_fpatan(CPUX86State *env) rexp = pi_2_exp; rsig0 = pi_2_sig_high; rsig1 = pi_2_sig_low; - } else if (floatx80_is_infinity(ST0) || arg0_exp - arg1_exp >= 80) { + } else if (floatx80_is_infinity(ST0, &env->fp_status) || + arg0_exp - arg1_exp >= 80) { /* ST0 is negative. */ rexp = pi_exp; rsig0 = pi_sig_high; @@ -1829,7 +1831,7 @@ void helper_fxtract(CPUX86State *env) } fpush(env); ST0 = ST1; - } else if (floatx80_is_infinity(ST0)) { + } else if (floatx80_is_infinity(ST0, &env->fp_status)) { fpush(env); ST0 = ST1; ST1 = floatx80_default_inf(0, &env->fp_status); @@ -2173,7 +2175,7 @@ void helper_fyl2x(CPUX86State *env) } else if (arg0_sign && !floatx80_is_zero(ST0)) { float_raise(float_flag_invalid, &env->fp_status); ST1 = floatx80_default_nan(&env->fp_status); - } else if (floatx80_is_infinity(ST1)) { + } else if (floatx80_is_infinity(ST1, &env->fp_status)) { FloatRelation cmp = floatx80_compare(ST0, floatx80_one, &env->fp_status); switch (cmp) { @@ -2188,7 +2190,7 @@ void helper_fyl2x(CPUX86State *env) ST1 = floatx80_default_nan(&env->fp_status); break; } - } else if (floatx80_is_infinity(ST0)) { + } else if (floatx80_is_infinity(ST0, &env->fp_status)) { if (floatx80_is_zero(ST1)) { float_raise(float_flag_invalid, &env->fp_status); ST1 = floatx80_default_nan(&env->fp_status); @@ -2341,11 +2343,11 @@ void helper_fscale(CPUX86State *env) float_raise(float_flag_invalid, &env->fp_status); ST0 = floatx80_silence_nan(ST0, &env->fp_status); } - } else if (floatx80_is_infinity(ST1) && + } else if (floatx80_is_infinity(ST1, &env->fp_status) && !floatx80_invalid_encoding(ST0) && !floatx80_is_any_nan(ST0)) { if (floatx80_is_neg(ST1)) { - if (floatx80_is_infinity(ST0)) { + if (floatx80_is_infinity(ST0, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST0 = floatx80_default_nan(&env->fp_status); } else { diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 339b73ad7dc..eb1cb8c6872 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -455,7 +455,7 @@ void HELPER(ftst)(CPUM68KState *env, FPReg *val) if (floatx80_is_any_nan(val->d)) { cc |= FPSR_CC_A; - } else if (floatx80_is_infinity(val->d)) { + } else if (floatx80_is_infinity(val->d, &env->fp_status)) { cc |= FPSR_CC_I; } else if (floatx80_is_zero(val->d)) { cc |= FPSR_CC_Z; From patchwork Mon Feb 24 11:15:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE992C021B5 for ; Mon, 24 Feb 2025 11:16:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWR1-0005mc-Od; Mon, 24 Feb 2025 06:15:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWQy-0005lR-Mr for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:37 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWQw-00017g-Q9 for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:36 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4399a1eada3so36925325e9.2 for ; Mon, 24 Feb 2025 03:15:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395733; x=1741000533; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HT/5CXTpTfkZBoP5otQyKvyxP6tWeoEhm9JG+aMYihU=; b=aVomeXZzWt37/kDMYx/1OeDeqX485vf/A0A8/3wSY+60Rb2MARFrdlxtjOll3y2OmR 7HuwKnl/BxzPnmT4hqtIaaO5egv2cA+tnZ5Qgp+yuZoZnz04GgmaGkvPb21SSOSf1+IY LngA4vlwU89ZrS7c8vLVg3Dmk4+rHJOBPsjkQlU3fvQN9pwnvY3yjb9nEL0oIM80keDF I1AcTJs2/1MLcluyAHnSHHrE82Hx3LkFQnDVEFyj5ALkVlHC1Fz/ATt1x0FfxuqBHyA1 Wrca78MECiva+EE2Wgr0Icyjncby51/un1hNNtoeooPB7CBNuiFjdXjGrzDM8TuGCPL+ jpjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395733; x=1741000533; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HT/5CXTpTfkZBoP5otQyKvyxP6tWeoEhm9JG+aMYihU=; b=kNJU4d2L2LnBFqSkzlB7sCxeWlSvuD1dKNNJdIHo0VLWmmL/lLhnSWTufDoHJgRwgv zKOp788mXVYyfblBTB2D9lj/kMuY1kJSMwX9NhQPlUWQLfnhPvtOwwyCvCjKEZkamhSN 4Ml9H6skW4wfYuN8PCNYV9hvADxTC5oM75IsVOeTEHvVdV7+V+vDDecWQ2Q6xnWfqMM7 AVoF59yiHqAHYlseIskDE/KhP/aPY+QkEvLHDXYno8rXT2m73rH+XrQDSoRf1iZHx7TZ o+M4v6c122vlHd2sIyYfG/y6CSw42EPj3KW2tXDgYUnkTSIAFZKu8k6P+KRg25gB4/XQ TL7w== X-Gm-Message-State: AOJu0Yw4B0ze+0vgTustR62iczF5MzizB13rU+2h8WPsn84nNtDwd3Xk 0mO/5KQulFTO0MgyK/39UqmO7Lasg9D3VBNKeXD36ADR2GsiSHVBNe9GkRoXTJsYm4ld+dP9mhb r X-Gm-Gg: ASbGncuiPHE/T9ueq7RQ0KxYw5D4nGUnABOAveoDZqMNCM63h5YVe9f/BhDNMTccnBP 4XnlTMOzByxwpon6jEnDsgb8fPONJrn2HY4cU6mxmp+1yFDikag71nh5VVnY4R2EJGiuuFxOMC3 SAdzx9fm4KMcR3X9E+RhufbnvLu2GoI3fA/xlMGWWXCbsBpLcZXt8oSguGluzz/k27w3cIys/VV W71+4S/hU8ZiAQbwtHxAEXMxaVXHx4/IM7gKANOkATDZpPSIfummpo8+eOJDMYHBYkIgg/6CjKY CTg6lDn2zs8jcQZvrAT9f89il3IUtsG8 X-Google-Smtp-Source: AGHT+IEGkiBprksplIni65kczOVCuM1w5azksObh2vzFrCeRxF6/WXItn0+saSbbdBJHiYZEIPbSbw== X-Received: by 2002:a05:600c:1396:b0:439:6d7c:48fd with SMTP id 5b1f17b1804b1-439ae1d877dmr107638155e9.4.1740395732994; Mon, 24 Feb 2025 03:15:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 05/12] fpu: Make targets specify whether floatx80 Inf can have Int bit clear Date: Mon, 24 Feb 2025 11:15:17 +0000 Message-ID: <20250224111524.1101196-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In Intel terminology, a floatx80 Infinity with the explicit integer bit clear is a "pseudo-infinity"; for x86 these are not valid infinity values. m68k is looser and does not care whether the Integer bit is set or clear in an infinity. Move this setting to runtime rather than using an ifdef in floatx80_is_infinity(). Since this was the last use of the floatx80_infinity global constant, we remove it and its definition here. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250217125055.160887-5-peter.maydell@linaro.org --- include/fpu/softfloat-types.h | 5 +++++ include/fpu/softfloat.h | 18 +++++++++++------- target/m68k/cpu.c | 4 +++- fpu/softfloat-specialize.c.inc | 10 ---------- 4 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index dd22ecdbe60..e1732beba4f 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -330,6 +330,11 @@ typedef enum __attribute__((__packed__)) { typedef enum __attribute__((__packed__)) { /* In the default Infinity value, is the Integer bit 0 ? */ floatx80_default_inf_int_bit_is_zero = 1, + /* + * Are Pseudo-infinities (Inf with the Integer bit zero) valid? + * If so, floatx80_is_infinity() will return true for them. + */ + floatx80_pseudo_inf_valid = 2, } FloatX80Behaviour; /* diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 3c83d703baf..07259c59303 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -960,7 +960,6 @@ float128 floatx80_to_float128(floatx80, float_status *status); /*---------------------------------------------------------------------------- | The pattern for an extended double-precision inf. *----------------------------------------------------------------------------*/ -extern const floatx80 floatx80_infinity; floatx80 floatx80_default_inf(bool zSign, float_status *status); /*---------------------------------------------------------------------------- @@ -998,12 +997,17 @@ static inline floatx80 floatx80_chs(floatx80 a) static inline bool floatx80_is_infinity(floatx80 a, float_status *status) { -#if defined(TARGET_M68K) - return (a.high & 0x7fff) == floatx80_infinity.high && !(a.low << 1); -#else - return (a.high & 0x7fff) == floatx80_infinity.high && - a.low == floatx80_infinity.low; -#endif + /* + * It's target-specific whether the Integer bit is permitted + * to be 0 in a valid Infinity value. (x86 says no, m68k says yes). + */ + bool intbit = a.low >> 63; + + if (!intbit && + !(status->floatx80_behaviour & floatx80_pseudo_inf_valid)) { + return false; + } + return (a.high & 0x7fff) == 0x7fff && !(a.low << 1); } static inline bool floatx80_is_neg(floatx80 a) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index df66e8ba22a..56b23de21fe 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -110,8 +110,10 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) /* * m68k-specific floatx80 behaviour: * * default Infinity values have a zero Integer bit + * * input Infinities may have the Integer bit either 0 or 1 */ - set_floatx80_behaviour(floatx80_default_inf_int_bit_is_zero, + set_floatx80_behaviour(floatx80_default_inf_int_bit_is_zero | + floatx80_pseudo_inf_valid, &env->fp_status); nan = floatx80_default_nan(&env->fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 73789e97d77..8327f727861 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -237,16 +237,6 @@ floatx80 floatx80_default_inf(bool zSign, float_status *status) return packFloatx80(zSign, 0x7fff, z ? 0 : (1ULL << 63)); } -#define floatx80_infinity_high 0x7FFF -#if defined(TARGET_M68K) -#define floatx80_infinity_low UINT64_C(0x0000000000000000) -#else -#define floatx80_infinity_low UINT64_C(0x8000000000000000) -#endif - -const floatx80 floatx80_infinity - = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); - /*---------------------------------------------------------------------------- | Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. From patchwork Mon Feb 24 11:15:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 645EAC021A4 for ; Mon, 24 Feb 2025 11:17:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWR1-0005mC-E4; Mon, 24 Feb 2025 06:15:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWQz-0005lZ-Kx for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:38 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWQx-00017q-Pd for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:37 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4398e3dfc66so37346785e9.0 for ; Mon, 24 Feb 2025 03:15:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395734; x=1741000534; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=38r/ruH5r/FXqSo0EoeLtJC+So+c2+K0n3Kb1+Fekw8=; b=ndWEUvNZZnpVByRf2Yp46OzJSRhxY41qDdfgNW1IaZZjGASEEe5QysizClb7YPxDLU Q7QqqWrH6W/NPWWXO20QKVCiVi1SueC4Wg0oZ8b06/G3pdLuHkioPGxIjohsq32OjrIu 4dWLk6wLhNB8CzkvEGMp/b9USe22yV2vrfwEWxfjVxJW2reO3N/y+o6Z36bnag6x0nX5 BDfWJM9PEb6DdUcEPF8iGd/l38zseGQRowaOGW4NoHwV25/sotpUxfO/nHvDgPSRKeyp S8Ef2tMdpjkfu2wiTJSIw+A9Soa4/Lh0tbUYpRniyrLXupxWSfjpL5gzwfgSfqphF/e0 24mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395734; x=1741000534; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=38r/ruH5r/FXqSo0EoeLtJC+So+c2+K0n3Kb1+Fekw8=; b=Q0HbypAyfKVEwdGp4My8J9CC247i33VGSUgj8dxgaR3oPI2YY/a3KFd/p7EviGbxAM l9JyKrGRBRm/gr9i4FC58eNWOG4FdYVl/kOsUSlog1YVsuvLDT/sfYxkIVM1UrTKoeOx oYUaUKk6M2Gy4iGzrn5eLxPD2h+6wEjMU1DIdUtJjsMs6DPLMonlAbGv4YILOIiDlqNv d6kXDC+qdApOdTlVm946cH+hKeD9w0PJmiX+OJ6pleNASPDAsxwDkDSt/oyvisQmzt5n wUN1yrnM6U87FW4F6baHdK6H5VQMN1bIAaUCakG2RTW4bJeOkbxO41Q2kMPBkg/fDAdr E7xA== X-Gm-Message-State: AOJu0YyuX2zaUJo0kEA0bCK4TibInKQ6M9BO6e7Yx9wPAw0hcUlBLDep YVMXoTiBALfAA6HasmYe71nVIe7WJbUHCSkY3Fw3POl0TvTIlVCqwEF2lbaRkE+FtkWIp1JDRUx A X-Gm-Gg: ASbGncv21LURdenpJvv9Q2+eifZW1A/hOtirOorYxjpcA3TRoNC5nVoJdfc0Dn0MJtu NMZddA7851to1xgQEbjsVvRS7ib0qNX9IpVquea5BP6b1youGG0CfWW6opR7hJpRpoQD8yrzW5K sEzd/tXLX9hP3bCzsri1TFZdIfLoy8fUQnRrHperXSwt/MsJ/3CxdjLbpW4oeYSyo7WhWk4BxVt EQ70dQiOUYNgX1TXL53F7hHMFm/W/Sn3EK2PAPGDyfIrRXp9lWyM0VC+4IehHJYNRAepdPutYLV v5h+ft+NUea/aypgcb3A5lo6XTdK+z+p X-Google-Smtp-Source: AGHT+IHWo/gU9Cj/o0eSoZsSuN2l1N9VJL8TqcL5/EqJ+BufcOl7Qt16DH1o4Fcrtfk+YeKN2rQC7g== X-Received: by 2002:a05:600c:1390:b0:439:8bc3:a697 with SMTP id 5b1f17b1804b1-439ae1d7e97mr107091045e9.4.1740395733983; Mon, 24 Feb 2025 03:15:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 06/12] fpu: Pass float_status to floatx80_invalid_encoding() Date: Mon, 24 Feb 2025 11:15:18 +0000 Message-ID: <20250224111524.1101196-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The definition of which floatx80 encodings are invalid is target-specific. Currently we handle this with an ifdef, but we would like to defer this decision to runtime. In preparation, pass a float_status argument to floatx80_invalid_encoding(). We will change the implementation from ifdef to looking at the status argument in the following commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/fpu/softfloat.h | 2 +- fpu/softfloat.c | 2 +- target/i386/tcg/fpu_helper.c | 24 +++++++++++++----------- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 07259c59303..1c8f3cbb78d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -1081,7 +1081,7 @@ static inline bool floatx80_unordered_quiet(floatx80 a, floatx80 b, | pseudo-denormals, which must still be correctly handled as inputs even | if they are never generated as outputs. *----------------------------------------------------------------------------*/ -static inline bool floatx80_invalid_encoding(floatx80 a) +static inline bool floatx80_invalid_encoding(floatx80 a, float_status *s) { #if defined(TARGET_M68K) /*------------------------------------------------------------------------- diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b12ad2b42a9..2a20ae871eb 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1810,7 +1810,7 @@ static bool floatx80_unpack_canonical(FloatParts128 *p, floatx80 f, g_assert_not_reached(); } - if (unlikely(floatx80_invalid_encoding(f))) { + if (unlikely(floatx80_invalid_encoding(f, s))) { float_raise(float_flag_invalid, s); return false; } diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 3b79bc049d1..4858ae9a5fb 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -1141,7 +1141,7 @@ void helper_f2xm1(CPUX86State *env) int32_t exp = extractFloatx80Exp(ST0); bool sign = extractFloatx80Sign(ST0); - if (floatx80_invalid_encoding(ST0)) { + if (floatx80_invalid_encoding(ST0, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST0 = floatx80_default_nan(&env->fp_status); } else if (floatx80_is_any_nan(ST0)) { @@ -1383,8 +1383,8 @@ void helper_fpatan(CPUX86State *env) } else if (floatx80_is_signaling_nan(ST1, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 = floatx80_silence_nan(ST1, &env->fp_status); - } else if (floatx80_invalid_encoding(ST0) || - floatx80_invalid_encoding(ST1)) { + } else if (floatx80_invalid_encoding(ST0, &env->fp_status) || + floatx80_invalid_encoding(ST1, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 = floatx80_default_nan(&env->fp_status); } else if (floatx80_is_any_nan(ST0)) { @@ -1819,7 +1819,7 @@ void helper_fxtract(CPUX86State *env) &env->fp_status); fpush(env); ST0 = temp.d; - } else if (floatx80_invalid_encoding(ST0)) { + } else if (floatx80_invalid_encoding(ST0, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST0 = floatx80_default_nan(&env->fp_status); fpush(env); @@ -1870,7 +1870,8 @@ static void helper_fprem_common(CPUX86State *env, bool mod) env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ if (floatx80_is_zero(ST0) || floatx80_is_zero(ST1) || exp0 == 0x7fff || exp1 == 0x7fff || - floatx80_invalid_encoding(ST0) || floatx80_invalid_encoding(ST1)) { + floatx80_invalid_encoding(ST0, &env->fp_status) || + floatx80_invalid_encoding(ST1, &env->fp_status)) { ST0 = floatx80_modrem(ST0, ST1, mod, "ient, &env->fp_status); } else { if (exp0 == 0) { @@ -2066,8 +2067,8 @@ void helper_fyl2xp1(CPUX86State *env) } else if (floatx80_is_signaling_nan(ST1, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 = floatx80_silence_nan(ST1, &env->fp_status); - } else if (floatx80_invalid_encoding(ST0) || - floatx80_invalid_encoding(ST1)) { + } else if (floatx80_invalid_encoding(ST0, &env->fp_status) || + floatx80_invalid_encoding(ST1, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 = floatx80_default_nan(&env->fp_status); } else if (floatx80_is_any_nan(ST0)) { @@ -2164,8 +2165,8 @@ void helper_fyl2x(CPUX86State *env) } else if (floatx80_is_signaling_nan(ST1, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 = floatx80_silence_nan(ST1, &env->fp_status); - } else if (floatx80_invalid_encoding(ST0) || - floatx80_invalid_encoding(ST1)) { + } else if (floatx80_invalid_encoding(ST0, &env->fp_status) || + floatx80_invalid_encoding(ST1, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 = floatx80_default_nan(&env->fp_status); } else if (floatx80_is_any_nan(ST0)) { @@ -2331,7 +2332,8 @@ void helper_frndint(CPUX86State *env) void helper_fscale(CPUX86State *env) { uint8_t old_flags = save_exception_flags(env); - if (floatx80_invalid_encoding(ST1) || floatx80_invalid_encoding(ST0)) { + if (floatx80_invalid_encoding(ST1, &env->fp_status) || + floatx80_invalid_encoding(ST0, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST0 = floatx80_default_nan(&env->fp_status); } else if (floatx80_is_any_nan(ST1)) { @@ -2344,7 +2346,7 @@ void helper_fscale(CPUX86State *env) ST0 = floatx80_silence_nan(ST0, &env->fp_status); } } else if (floatx80_is_infinity(ST1, &env->fp_status) && - !floatx80_invalid_encoding(ST0) && + !floatx80_invalid_encoding(ST0, &env->fp_status) && !floatx80_is_any_nan(ST0)) { if (floatx80_is_neg(ST1)) { if (floatx80_is_infinity(ST0, &env->fp_status)) { From patchwork Mon Feb 24 11:15:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987828 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76D84C021A4 for ; Mon, 24 Feb 2025 11:18:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWRO-0005qb-PL; Mon, 24 Feb 2025 06:16:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWR1-0005ly-06 for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:39 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWQy-00018B-Nn for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:38 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-38dcac27bcbso3252346f8f.0 for ; Mon, 24 Feb 2025 03:15:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395735; x=1741000535; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3ajZ80sJdOGH3k+29+o4N7kSCTpNRDBlyRWkxI9EVY8=; b=wEgDikF73w5EJcaQLy9bLuUiiGqBFm1TqaIL7n4Y5VpjLHtye3Irwh3IOpkC3c7IFU gbLpUjB6aC1o4JzNzYQPuJGsalXLuAnbiS/jSzPqDJ51RS6LN0Jcs+Ioydc8AOC2NjqR ByXi04dBVU083IU98xn2IO0Jq6Lesxp+Bx72Tbg7b4g3ZziZhBQtQ79iWGBF9LwKI5VI RYMp9X6ziIrW4DvEf0PDTl1t7ZF0aIN3Wq3+Rn3jREyYuJIDPWe0+c60XD/T0UV/UGWY jPnHw2ngoZsACG7b0KFy/dPCaIzXSHmsu+ESkNNDNKglQaQUF3v7w/zRQS7N9DcEhnrD zgDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395735; x=1741000535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3ajZ80sJdOGH3k+29+o4N7kSCTpNRDBlyRWkxI9EVY8=; b=Kw5zB5DslTBzkTKRJaaCGbzkFDIkLyUs5Q7IrK5siNdsQDucRebwRzKnSXgkSRJpop iZtCGG9+n+GVXPkBc7icXWAsLO/EDaFM/4hkXI9aiMzJOc8Wvp/0uMgezaSTHz2HDAnM 30BToOufG3VQqObXwiwm8X19dPSufAJiajuI51dYKJeZBEquuoLjKHDx3W38Fs418bb4 2TvqLBLNhzTuiGq2n8b7DfL7ZAFihtErpUEI3y3SpvwP4mXZS4IqqxHncIc8DAsmlRGk 0FIJyEN8gqHgXM/SHqNgvlx+M+7cVdofWZU7cxGHxginUeeTPtvWYjMGtN4iMiLjvcHn kDGA== X-Gm-Message-State: AOJu0YwS9lrupj4XiYvhi5LCSfKW7Nn4cLXep+3e8FPXmW+K3Uu+UeIW tnX/5Nk6rPb+2l6U5MCD2dphprBmAeJXYa/WYbEF3fqslNrW9sUuFWI5sfJQh8meBYz1OhPT3bq 9 X-Gm-Gg: ASbGnctZekquSGXFvdIGqsItAJ0Hic6TEuUxpnkaCDSEb/DVjVLTB8vr4otf0X7ItOY OqHVoOHGDvAyJ7FMv3rQ4XIA+3rYjqBU4xVXSWgLIpVct1LvS7OPKp6lrN8Bh7HoQ7nFvfnULw2 f1W178NnukvG5xc0x8u6CQH2p1/i2WzNK9bEX6W94/PUz69/MqNUiiVW7jIflqoV8Za8ktG5l/v ih4fCIQmxfaJwjaeTa0NOcGW2A6yXzhAj8EcT+eIGYryY4L4fBFqBpL6jrFoRw0LLPyFa9RHCqX aTTGQ7/tzndOA7I6HBmUnN8232fK/+9J X-Google-Smtp-Source: AGHT+IFGMc01xXSWKVFevOmmgMnodERzFMICfmYep/ekALoZhOueFgQywCVVrGnQMpB7TiPwTl+Xbg== X-Received: by 2002:a05:6000:4712:b0:38f:32d5:3a92 with SMTP id ffacd0b85a97d-38f614b827bmr14284352f8f.12.1740395735039; Mon, 24 Feb 2025 03:15:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 07/12] fpu: Make floatx80 invalid encoding settable at runtime Date: Mon, 24 Feb 2025 11:15:19 +0000 Message-ID: <20250224111524.1101196-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Because floatx80 has an explicit integer bit, this permits some odd encodings where the integer bit is not set correctly for the floating point value type. In In Intel terminology the categories are: exp == 0, int = 0, mantissa == 0 : zeroes exp == 0, int = 0, mantissa != 0 : denormals exp == 0, int = 1 : pseudo-denormals 0 < exp < 0x7fff, int = 0 : unnormals 0 < exp < 0x7fff, int = 1 : normals exp == 0x7fff, int = 0, mantissa == 0 : pseudo-infinities exp == 0x7fff, int = 1, mantissa == 0 : infinities exp == 0x7fff, int = 0, mantissa != 0 : pseudo-NaNs exp == 0x7fff, int = 1, mantissa == 0 : NaNs The usual IEEE cases of zero, denormal, normal, inf and NaN are always valid. x87 permits as input also pseudo-denormals. m68k permits all those and also pseudo-infinities, pseudo-NaNs and unnormals. Currently we have an ifdef in floatx80_invalid_encoding() to select the x86 vs m68k behaviour. Add new floatx80_behaviour flags to select whether pseudo-NaN and unnormal are valid, and use these (plus the existing pseudo_inf_valid flag) to decide whether these encodings are invalid at runtime. We leave pseudo-denormals as always-valid, since both x86 and m68k accept them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250217125055.160887-6-peter.maydell@linaro.org --- include/fpu/softfloat-types.h | 14 ++++++++ include/fpu/softfloat.h | 68 ++++++++++++++++++----------------- target/m68k/cpu.c | 28 ++++++++++++++- 3 files changed, 77 insertions(+), 33 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index e1732beba4f..b1941384aef 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -333,8 +333,22 @@ typedef enum __attribute__((__packed__)) { /* * Are Pseudo-infinities (Inf with the Integer bit zero) valid? * If so, floatx80_is_infinity() will return true for them. + * If not, floatx80_invalid_encoding will return false for them, + * and using them as inputs to a float op will raise Invalid. */ floatx80_pseudo_inf_valid = 2, + /* + * Are Pseudo-NaNs (NaNs where the Integer bit is zero) valid? + * If not, floatx80_invalid_encoding() will return false for them, + * and using them as inputs to a float op will raise Invalid. + */ + floatx80_pseudo_nan_valid = 4, + /* + * Are Unnormals (0 < exp < 0x7fff, Integer bit zero) valid? + * If not, floatx80_invalid_encoding() will return false for them, + * and using them as inputs to a float op will raise Invalid. + */ + floatx80_unnormal_valid = 8, } FloatX80Behaviour; /* diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 1c8f3cbb78d..c18ab2cb609 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -1073,41 +1073,45 @@ static inline bool floatx80_unordered_quiet(floatx80 a, floatx80 b, /*---------------------------------------------------------------------------- | Return whether the given value is an invalid floatx80 encoding. -| Invalid floatx80 encodings arise when the integer bit is not set, but -| the exponent is not zero. The only times the integer bit is permitted to -| be zero is in subnormal numbers and the value zero. -| This includes what the Intel software developer's manual calls pseudo-NaNs, -| pseudo-infinities and un-normal numbers. It does not include -| pseudo-denormals, which must still be correctly handled as inputs even -| if they are never generated as outputs. +| Invalid floatx80 encodings may arise when the integer bit is not set +| correctly; this is target-specific. In Intel terminology the +| categories are: +| exp == 0, int = 0, mantissa == 0 : zeroes +| exp == 0, int = 0, mantissa != 0 : denormals +| exp == 0, int = 1 : pseudo-denormals +| 0 < exp < 0x7fff, int = 0 : unnormals +| 0 < exp < 0x7fff, int = 1 : normals +| exp == 0x7fff, int = 0, mantissa == 0 : pseudo-infinities +| exp == 0x7fff, int = 1, mantissa == 0 : infinities +| exp == 0x7fff, int = 0, mantissa != 0 : pseudo-NaNs +| exp == 0x7fff, int = 1, mantissa == 0 : NaNs +| +| The usual IEEE cases of zero, denormal, normal, inf and NaN are always valid. +| x87 permits as input also pseudo-denormals. +| m68k permits all those and also pseudo-infinities, pseudo-NaNs and unnormals. +| +| Since we don't have a target that handles floatx80 but prohibits +| pseudo-denormals in input, we don't currently have a floatx80_behaviour +| flag for that case, but instead always accept it. Conveniently this +| means that all cases with either exponent 0 or the integer bit set are +| valid for all targets. *----------------------------------------------------------------------------*/ static inline bool floatx80_invalid_encoding(floatx80 a, float_status *s) { -#if defined(TARGET_M68K) - /*------------------------------------------------------------------------- - | With m68k, the explicit integer bit can be zero in the case of: - | - zeros (exp == 0, mantissa == 0) - | - denormalized numbers (exp == 0, mantissa != 0) - | - unnormalized numbers (exp != 0, exp < 0x7FFF) - | - infinities (exp == 0x7FFF, mantissa == 0) - | - not-a-numbers (exp == 0x7FFF, mantissa != 0) - | - | For infinities and NaNs, the explicit integer bit can be either one or - | zero. - | - | The IEEE 754 standard does not define a zero integer bit. Such a number - | is an unnormalized number. Hardware does not directly support - | denormalized and unnormalized numbers, but implicitly supports them by - | trapping them as unimplemented data types, allowing efficient conversion - | in software. - | - | See "M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL", - | "1.6 FLOATING-POINT DATA TYPES" - *------------------------------------------------------------------------*/ - return false; -#else - return (a.low & (1ULL << 63)) == 0 && (a.high & 0x7FFF) != 0; -#endif + if ((a.low >> 63) || (a.high & 0x7fff) == 0) { + /* Anything with the Integer bit set or the exponent 0 is valid */ + return false; + } + + if ((a.high & 0x7fff) == 0x7fff) { + if (a.low) { + return !(s->floatx80_behaviour & floatx80_pseudo_nan_valid); + } else { + return !(s->floatx80_behaviour & floatx80_pseudo_inf_valid); + } + } else { + return !(s->floatx80_behaviour & floatx80_unnormal_valid); + } } #define floatx80_zero make_floatx80(0x0000, 0x0000000000000000LL) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 56b23de21fe..505fa97a53f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -111,9 +111,35 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) * m68k-specific floatx80 behaviour: * * default Infinity values have a zero Integer bit * * input Infinities may have the Integer bit either 0 or 1 + * * pseudo-denormals supported for input and output + * * don't raise Invalid for pseudo-NaN/pseudo-Inf/Unnormal + * + * With m68k, the explicit integer bit can be zero in the case of: + * - zeros (exp == 0, mantissa == 0) + * - denormalized numbers (exp == 0, mantissa != 0) + * - unnormalized numbers (exp != 0, exp < 0x7FFF) + * - infinities (exp == 0x7FFF, mantissa == 0) + * - not-a-numbers (exp == 0x7FFF, mantissa != 0) + * + * For infinities and NaNs, the explicit integer bit can be either one or + * zero. + * + * The IEEE 754 standard does not define a zero integer bit. Such a number + * is an unnormalized number. Hardware does not directly support + * denormalized and unnormalized numbers, but implicitly supports them by + * trapping them as unimplemented data types, allowing efficient conversion + * in software. + * + * See "M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL", + * "1.6 FLOATING-POINT DATA TYPES" + * + * Note though that QEMU's fp emulation does directly handle both + * denormal and unnormal values, and does not trap to guest software. */ set_floatx80_behaviour(floatx80_default_inf_int_bit_is_zero | - floatx80_pseudo_inf_valid, + floatx80_pseudo_inf_valid | + floatx80_pseudo_nan_valid | + floatx80_unnormal_valid, &env->fp_status); nan = floatx80_default_nan(&env->fp_status); From patchwork Mon Feb 24 11:15:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13B3CC021A4 for ; Mon, 24 Feb 2025 11:16:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWRL-0005pT-VQ; Mon, 24 Feb 2025 06:15:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWR2-0005n4-6s for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:40 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWR0-00018x-5S for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:39 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4399deda38cso25180025e9.1 for ; Mon, 24 Feb 2025 03:15:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395737; x=1741000537; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oqXeXRoWaJ3QKZJ6jrqg2FahLEljcBiEpPgYa/U9aIk=; b=sjMPmDmdrCOEQ6VEueSOQo39KclZbLqFrPryYe666ds4ttMtUGNjoFZ8rYJBwYiEOC 6Hj+wC4OD2hncJJ6J0aOh3uyE3a87Z35Zvsb8NzAaew3uGT169hhF4yJttt8En9wDgua goRst6ORbDgsQE/zxkR7iG1e4LR8oyRfYF1/VadcipK7UIDY//94A+o7bjUMIOimhQdI 0I9jQpXnXtY663elFTxn1oDgT1iaUqVTo88IwtsGjkClZ/JHH2DBshO38gBRwHYB2nqi Clmo5bRLo5zhm/GVAzKVR+Fw3kLVJtItAvG7tOI/WlPiigI4/Sc49wuce3+aW577o2lx o57A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395737; x=1741000537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oqXeXRoWaJ3QKZJ6jrqg2FahLEljcBiEpPgYa/U9aIk=; b=VPVJ8MppsywdpI1IfBRbeuGg6UPn/T8HiZTfnxAjXxtO9TERyaMkPiYI2wit1/PlW0 HxZNy80RwAApas1GbojE5iRfmGeZLWDBjm4cO0TfiBpoOGyabweG9B0CRJ1hSiw7AAuO R5miaySeVp40bqOuh1rjhhtjY460tmyWf6YQgeGkwwVQz4Zt3t3O4FEBcvl5st3QC3RJ LoNglQMqmRxJR1drXHequwhG3aCkwmrqq3GXYqpg361LNgmZOOSJUTIa33hJy9gBYsy7 xmGy9P5CWjHo+fL+geGyPqWdE49PNHx6dqZVUtA0GVzesB38IFUvaLUt+Zrj1Rlp50A7 TQ5Q== X-Gm-Message-State: AOJu0YximThg6U2+kv4AY/XN8BNY5G8Ad10+PlTon2dqg+ysmJ3/1neN Fq1D0Nz7JOWWysXjYZcJT94dM7xDgR4Yb1i17EpWf081T8o0VuPGwF5wYXyFYvDDcLy7GiGOH8+ m X-Gm-Gg: ASbGncv0ACRS+tlM32VVzCe0o96t0O/lVB2pvLAoCDxbKcV1Gt91ZCN+x3GF4QFFUA2 nvIXY5dWEF70WA74gr5saaSdwQbrLBAufYxuEeF19JfIu1VdrBY1yXq55YXVroNUBmTaZQZThGn u6z1QI5NY1Qa3mTdyNIcPHnWPVzI2kC9bXdZSpV/nH4Z11BEtBtdSp9VZofJnaFE/cm8gi26FDe sU0TK7K8yVX543o+G/4AERgetWyYgCuCqVv34V6LpiEYKCYY8tTwuYvgC8NbrTMRFKUWprcoXhl /x55yk9lpBhSG2j2C7/Dh+7my0up+8Oy X-Google-Smtp-Source: AGHT+IHKrUtm8nDC4mB4T6pWXNR12sBYJkdtlG3hQTtihGebc/UngvQ0QcxmY3WbZeJGyujLi7NmuA== X-Received: by 2002:a05:600c:5246:b0:439:9c3a:bba7 with SMTP id 5b1f17b1804b1-439ae21d280mr98358935e9.28.1740395736631; Mon, 24 Feb 2025 03:15:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 08/12] fpu: Move m68k_denormal fmt flag into floatx80_behaviour Date: Mon, 24 Feb 2025 11:15:20 +0000 Message-ID: <20250224111524.1101196-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently we compile-time set an 'm68k_denormal' flag in the FloatFmt for floatx80 for m68k. This controls our handling of what the Intel documentation calls a "pseudo-denormal": a value where the exponent field is zero and the explicit integer bit is set. For x86, the x87 FPU is supposed to accept a pseudo-denormal as input, but never generate one on output. For m68k, these values are permitted on input and may be produced on output. Replace the flag in the FloatFmt with a flag indicating whether the float format has an explicit bit (which will be true for floatx80 for all targets, and false for every other float type). Then we can gate the handling of these pseudo-denormals on the setting of a floatx80_behaviour flag. As far as I can see from the code we don't actually handle the x86-mandated "accept on input but don't generate" behaviour, because the handling in partsN(canonicalize) looked at fmt->m68k_denormal. So I have added TODO comments to that effect. This commit doesn't change any behaviour for any target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20250217125055.160887-7-peter.maydell@linaro.org --- include/fpu/softfloat-types.h | 19 +++++++++++++++++++ fpu/softfloat.c | 9 ++++----- target/m68k/cpu.c | 3 ++- fpu/softfloat-parts.c.inc | 27 ++++++++++++++++++++++++--- 4 files changed, 49 insertions(+), 9 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index b1941384aef..1af2a0cb14b 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -349,6 +349,25 @@ typedef enum __attribute__((__packed__)) { * and using them as inputs to a float op will raise Invalid. */ floatx80_unnormal_valid = 8, + + /* + * If the exponent is 0 and the Integer bit is set, Intel call + * this a "pseudo-denormal"; x86 supports that only on input + * (treating them as denormals by ignoring the Integer bit). + * For m68k, the integer bit is considered validly part of the + * input value when the exponent is 0, and may be 0 or 1, + * giving extra range. They may also be generated as outputs. + * (The m68k manual actually calls these values part of the + * normalized number range, not the denormalized number range.) + * + * By default you get the Intel behaviour where the Integer + * bit is ignored; if this is set then the Integer bit value + * is honoured, m68k-style. + * + * Either way, floatx80_invalid_encoding() will always accept + * pseudo-denormals. + */ + floatx80_pseudo_denormal_valid = 16, } FloatX80Behaviour; /* diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 2a20ae871eb..b299cfaf860 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -537,7 +537,8 @@ typedef struct { * round_mask: bits below lsb which must be rounded * The following optional modifiers are available: * arm_althp: handle ARM Alternative Half Precision - * m68k_denormal: explicit integer bit for extended precision may be 1 + * has_explicit_bit: has an explicit integer bit; this affects whether + * the float_status floatx80_behaviour handling applies */ typedef struct { int exp_size; @@ -547,7 +548,7 @@ typedef struct { int frac_size; int frac_shift; bool arm_althp; - bool m68k_denormal; + bool has_explicit_bit; uint64_t round_mask; } FloatFmt; @@ -600,9 +601,7 @@ static const FloatFmt floatx80_params[3] = { [floatx80_precision_d] = { FLOATX80_PARAMS(52) }, [floatx80_precision_x] = { FLOATX80_PARAMS(64), -#ifdef TARGET_M68K - .m68k_denormal = true, -#endif + .has_explicit_bit = true, }, }; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 505fa97a53f..2617d8f6ede 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -139,7 +139,8 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) set_floatx80_behaviour(floatx80_default_inf_int_bit_is_zero | floatx80_pseudo_inf_valid | floatx80_pseudo_nan_valid | - floatx80_unnormal_valid, + floatx80_unnormal_valid | + floatx80_pseudo_denormal_valid, &env->fp_status); nan = floatx80_default_nan(&env->fp_status); diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 1d09f066c5d..171bfd06e3a 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -195,6 +195,25 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, static void partsN(canonicalize)(FloatPartsN *p, float_status *status, const FloatFmt *fmt) { + /* + * It's target-dependent how to handle the case of exponent 0 + * and Integer bit set. Intel calls these "pseudodenormals", + * and treats them as if the integer bit was 0, and never + * produces them on output. This is the default behaviour for QEMU. + * For m68k, the integer bit is considered validly part of the + * input value when the exponent is 0, and may be 0 or 1, + * giving extra range. They may also be generated as outputs. + * (The m68k manual actually calls these values part of the + * normalized number range, not the denormalized number range, + * but that distinction is not important for us, because + * m68k doesn't care about the input_denormal_used status flag.) + * floatx80_pseudo_denormal_valid selects the m68k behaviour, + * which changes both how we canonicalize such a value and + * how we uncanonicalize results. + */ + bool has_pseudo_denormals = fmt->has_explicit_bit && + (status->floatx80_behaviour & floatx80_pseudo_denormal_valid); + if (unlikely(p->exp == 0)) { if (likely(frac_eqz(p))) { p->cls = float_class_zero; @@ -206,7 +225,7 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status, int shift = frac_normalize(p); p->cls = float_class_denormal; p->exp = fmt->frac_shift - fmt->exp_bias - - shift + !fmt->m68k_denormal; + - shift + !has_pseudo_denormals; } } else if (likely(p->exp < fmt->exp_max) || fmt->arm_althp) { p->cls = float_class_normal; @@ -342,13 +361,15 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, frac_clear(p); } else { bool is_tiny = s->tininess_before_rounding || exp < 0; + bool has_pseudo_denormals = fmt->has_explicit_bit && + (s->floatx80_behaviour & floatx80_pseudo_denormal_valid); if (!is_tiny) { FloatPartsN discard; is_tiny = !frac_addi(&discard, p, inc); } - frac_shrjam(p, !fmt->m68k_denormal - exp); + frac_shrjam(p, !has_pseudo_denormals - exp); if (p->frac_lo & round_mask) { /* Need to recompute round-to-even/round-to-odd. */ @@ -379,7 +400,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, p->frac_lo &= ~round_mask; } - exp = (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) && !fmt->m68k_denormal; + exp = (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) && !has_pseudo_denormals; frac_shr(p, frac_shift); if (is_tiny) { From patchwork Mon Feb 24 11:15:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEB47C021A6 for ; Mon, 24 Feb 2025 11:18:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWRP-0005rF-Tv; Mon, 24 Feb 2025 06:16:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWR5-0005nj-EK for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:57 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWR2-00019J-74 for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:41 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-439350f1a0bso24833035e9.0 for ; Mon, 24 Feb 2025 03:15:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395737; x=1741000537; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DTW+guxKto4jsRU3T6f5JGrwIUxjIeZwYhIwDRM/nu8=; b=K5Hi0qCFYPHAdtAcDE1CyPNiaWaTGOsspUfGckBcH3EPKW6lHJiOaE+WgXmaLOixL1 NwvUZKt9keWtwTzEjOsln/Ci4wyy4qaMm7C42EUfq7j3ms5MqS8h7kZ+4EPeN4aGturx 6Is70NOY2b3LkCRjyrCa+uhTK0+ragZp5/xTUADV37pTzsNIOG+n980wb9uv/dguQKeA 1i5Uh+gCfo+x/29/lqXwj+JmnrHZ8VjsDFe8YCnxFTnNQ+NP5wfxd7jxbVrAXgysvT3e O5yLyP7hbGyO+Ee56DbhR1d8YwYJHAnwWjrQHMMSS1xETnehwbgvnWFqcNZXy6NcVovt zcoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395737; x=1741000537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DTW+guxKto4jsRU3T6f5JGrwIUxjIeZwYhIwDRM/nu8=; b=dtzU+cjHIUBTC7yeGpwTOybqk/J+nvxxkT4OYKpWVZT6uHoLOkA5v5dSVYdFb00A5g Rt+vRGj2EV6S6HaISVqiKSWuy+2SWcnlv/Gl4OaE+6o031khLIc6keTmknBkznkgmeic eFS7s1OzqcuJJR98ogYqVM7LlIwvRBY610+ZUVXdigVa5PgzjXiccvZAiJpqMy4m4ESS aRIpGscnoFTwrBWIJomrVRN/eLwD26AuRrQUp+T7kSEuIUdLi3IJNGVV5bg519zBiXas WCFaAy8Ft4oz3bvs351tT8R3UNrnHf/WzNhvp7MP82jP5BQgMUv5wxne6hlh1K7Iez8r oe2Q== X-Gm-Message-State: AOJu0YxNnBebY5OV3MYMj4CXUTLcaipl6taSgY/NfMgHTHu+A99kw7/y muemy6wKDZt/JirHmJ6F+maRTyMAjPtbIvXZq48MLQLlxEJ81tTSX8IBtGn2pi7MmYz3lI0UKbP x X-Gm-Gg: ASbGncubJoAsPtSLkeCpJG81nG3KzBzdxBGYtdzT2kUjOW76DMfX+uBrmycSmbNz5c8 lqe3vpZJUCg9bdYAXuBBXQQopt7huM2j2+KHJK6hPapJO3DfHfw55Y2AIYoG72GG0+B5HZWzKdE gnQmUv0SQYzSK9u9U5gNKPCL3uli3RxQw6e3wEJKUGc5GoiE3cNXMw94MMxXFpE/4U408Oqp/Sg pv4aet0UHz8GkCqFolFlwH08Ow0kD1hkPfpvXyJWAi+40JsGsVRvTiJI7P8/eeyp4/ZopSFwkBW Ufvl5/vTrd/PbMSJkrjgNZjFRIpl2bMf X-Google-Smtp-Source: AGHT+IG08KRwDYDl3Eca/M/8HaBNJFxvYjEOQHCH2Utkv4RtOym9hjubqe/nvBxLIy/wgdS7JacjWQ== X-Received: by 2002:a05:600c:1d0b:b0:439:98fd:a4b6 with SMTP id 5b1f17b1804b1-439ae33cb6bmr105188825e9.15.1740395737687; Mon, 24 Feb 2025 03:15:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 09/12] fpu: Always decide no_signaling_nans() at runtime Date: Mon, 24 Feb 2025 11:15:21 +0000 Message-ID: <20250224111524.1101196-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently we have a compile-time shortcut where we return false from no_signaling_nans() on everything except Xtensa, because we know that's the only target that might ever set status->no_signaling_nans. Remove the ifdef, so we always look at the status flag; this has no behavioural change, but will be necessary if we want to build softfloat once for all targets. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20250217125055.160887-8-peter.maydell@linaro.org --- fpu/softfloat-specialize.c.inc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 8327f727861..a2c6afad5da 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -85,11 +85,7 @@ this code that are retained. */ static inline bool no_signaling_nans(float_status *status) { -#if defined(TARGET_XTENSA) return status->no_signaling_nans; -#else - return false; -#endif } /* Define how the architecture discriminates signaling NaNs. From patchwork Mon Feb 24 11:15:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B957CC021A6 for ; Mon, 24 Feb 2025 11:18:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWRP-0005qn-DX; Mon, 24 Feb 2025 06:16:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWR5-0005nk-FC for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:57 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWR2-00019u-7l for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:41 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4399deda38cso25180275e9.1 for ; Mon, 24 Feb 2025 03:15:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395739; x=1741000539; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nf5bfpfYc3QDe9rpAHEHV/dGaYf8w2BaIghlHVtGZRU=; b=FWtX7nLEShH+rN3uhY7B9NQdu0HLeCSfThKJDj+1HQA1aZBoq9N6qq0tI0moAeDgSW MYUNDvw45nDFgrtM3WXQXjndoacoC4uBSBg+bZqD8vniAWo3dkdVo1j/aC1jBw7Wtz0z HJykWFfCsjc+9bJ78XVL+JcP9lkBN/PMwfPotUB7Zb5ykhkNl/hLOH+1d9d/KUMq2Y5Y gr1JofMUbjVYtD11uqAlCLt9/a8Rr6KGWllG0lDuvAedEydD34L7fNKmbspd4o6bASZW CCdo8trSGjRgsAmjmjjkaCWSTBgQOrGGd3z47JMVkAvGnoKJKysXsX/cbUDFCFuC52jN bxQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395739; x=1741000539; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nf5bfpfYc3QDe9rpAHEHV/dGaYf8w2BaIghlHVtGZRU=; b=cEpL11etfOMplSZZVGmctf7HAy4RUm0VjNUJHmKeYvpa7IMDFFATOcO8Kv0nabN1cX 4DsI4LqCjBhDa81KmxCIJS1qrhl/tZhE6Q0g126VYu8kHTLIt/a1LBUJhDMiPrsp4pYY 1PWQYoasg8nT/EVMPxajrFlCNez4Dw60/xkrDMTmXLSiL8XlxbFLLrLQSAOXkGQRRgEH nAa/cG+gAz3HSxG5ulqPEZyUTK6BXu4CGGiyEUPdOtQAaOfxfp53yPRyO5CVflADijNy Me3AM+DdiIgccrkMWiXw4xcRDN4vKdllHhZMBFID13dzrF0P+MV/RxzuL69N56lmnBwh HBHQ== X-Gm-Message-State: AOJu0YyD4sGu4+VW64NbUrR42Sgvu9sOUJ5AWt6jycDhfbAG02zV0DTb V9SdD3sMJqD8o7r7uCpTphdlUHFjt6A8Y7QJ6ZqbyuhgBjjFQnQGdG58MxHRjVwM/XOmsvzqs/M H X-Gm-Gg: ASbGncvsrKawi//xeIosTr9H6j/pkFh950Fp/HTCE2qXS5lYu1TLZp9AM7V4Hpy5RZI HCTtRpwHeQUdsP14yxYbgyvv50hIrz8eB5VpIsKtPBIvCXaCEzT7or+0DQRsQ7A6vUfZP20Ilic vI/cSgre+hI9C7mPkLAdX61KC48QgxcWOPPEWeRgL5coUHyvzATtJAUAYcFjA6IQ9s3QJ9rRBMS /1+F2ASOR75WUWT6qMN36kOAzyR1zbwEEt3RIU0Q4efQSuWvF2xdPNjm23yfmJp9JVIUvrZ3MYJ SNp0QRzViY0VMlmNACNiJ9BlTciuSIT4 X-Google-Smtp-Source: AGHT+IH0uKs7neb0QCox+REk+ODpnHaGL9XwHuZZNVVUR+kXl9/pdowBNlm3nNcknr7Xo0S0+mD+aA== X-Received: by 2002:a05:600c:458e:b0:439:8340:637 with SMTP id 5b1f17b1804b1-439ae21e4c8mr125849215e9.30.1740395738577; Mon, 24 Feb 2025 03:15:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 10/12] fpu: Always decide snan_bit_is_one() at runtime Date: Mon, 24 Feb 2025 11:15:22 +0000 Message-ID: <20250224111524.1101196-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently we have a compile-time shortcut where we return a hardcode value from snan_bit_is_one() on everything except MIPS, because we know that's the only target that needs to change status->no_signaling_nans at runtime. Remove the ifdef, so we always look at the status flag. This means we must update the two targets (HPPA and SH4) that were previously hardcoded to return true so that they set the status flag correctly. This has no behavioural change, but will be necessary if we want to build softfloat once for all targets. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20250217125055.160887-9-peter.maydell@linaro.org --- target/hppa/fpu_helper.c | 1 + target/sh4/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 7 ------- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 8ff4b448049..a62d9d30831 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -67,6 +67,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); /* Default NaN: sign bit clear, msb-1 frac bit set */ set_float_default_nan_pattern(0b00100000, &env->fp_status); + set_snan_bit_is_one(true, &env->fp_status); /* * "PA-RISC 2.0 Architecture" says it is IMPDEF whether the flushing * enabled by FPSR.D happens before or after rounding. We pick "before" diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 4ac693d99bd..ccfe222bdf3 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -128,6 +128,7 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); + set_snan_bit_is_one(true, &env->fp_status); /* sign bit clear, set all frac bits other than msb */ set_float_default_nan_pattern(0b00111111, &env->fp_status); /* diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index a2c6afad5da..ba4fa08b7be 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -93,17 +93,10 @@ static inline bool no_signaling_nans(float_status *status) * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 * the msb must be zero. MIPS is (so far) unique in supporting both the * 2008 revision and backward compatibility with their original choice. - * Thus for MIPS we must make the choice at runtime. */ static inline bool snan_bit_is_one(float_status *status) { -#if defined(TARGET_MIPS) return status->snan_bit_is_one; -#elif defined(TARGET_HPPA) || defined(TARGET_SH4) - return 1; -#else - return 0; -#endif } /*---------------------------------------------------------------------------- From patchwork Mon Feb 24 11:15:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46522C021B5 for ; Mon, 24 Feb 2025 11:18:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWRM-0005qK-MF; Mon, 24 Feb 2025 06:16:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWR7-0005oE-0p for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:58 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWR5-0001A7-91 for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:44 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4399deda4bfso28555415e9.0 for ; Mon, 24 Feb 2025 03:15:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395739; x=1741000539; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c/xq2A3p4R19qNhPGzZgnSRkmfAVMySHI9mTT7PkVAQ=; b=onBsQBQi2ckBFDTEBg3Vvxbc48MOr/v1HRLrUfww/uU6mJ4QV6vlM4y28keB2UlALC ftRV4GTyuLIvIEWB5ZIQOdEUe2R4Gof8Eb3TOSeQmvE1/OCoYekWLJ0dZUXgsxwXwrv4 7IgZMAfnJwehdxT46G7ZD+0iU6G8l1iPR7yB3vcouaX0Qhv9LwRAi2RAmajp1rcDyBu8 VIHlIelYQryqG9Vc9hbVL4el0DJmUwb9PORsWIczkIbAVPyavBpBC6qGrynSbmm6HcJ3 MD3eLYy9o8EW9MxioFhrgMQLWAa5adb8KVb6Z7oZaatS7k+cwiu+ZdnSajcN34dN1DSN HXNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395739; x=1741000539; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c/xq2A3p4R19qNhPGzZgnSRkmfAVMySHI9mTT7PkVAQ=; b=Dt+VvWI+Oht1cd34FCscfSFuT69FNsiebDQETmnGk9Oq9JBd0Hcz9ZNJI54ucLbjwx wgQuTDDEoVzOXepqJZXiOkfcU3vL+ersHDNR/DhO19WAKt1ML+BdT7mgTyt5eVLc9XMl P/rWpC5tIFFrA+BgGFfbwwiWM9NjF2h4HCd1SZQ6eA1FxVuBNRNSXvGUAU4n61/OxMCM qcgfbBI2QHLL3cL8BA5uc7T/Kru9DTg5flbm3+xuRXJCaJz0wLEeTSJLiDcFq3BqQr1f SQCMzrrXnefB8Xo7WI68NVpqE9toSKJjRK9J/3bXzyKpv7clKYyxHgJWMSPq2X/MVYbP t4AQ== X-Gm-Message-State: AOJu0YwSpE4E0qQvcBKvoa6DauiPVJSgjglgpUKFP7jDBsuMUXCmHYwF H2N6Q329Gewiv+7M3GqTSLvd4H5yHrBs+zw9dOf0UgVzeuady7Z39vpWED0pjhP0hdYH+eoFedg F X-Gm-Gg: ASbGncub6aQ2+EnDGvfK77cLQNYwOuFgY7G2Q4jOgWmS+Oz1XJxoMiQnaHk2VEObcvl W/uVL6mLjYwzcadeWydT50hmT/0FdCZ/zirgIJ0RbhGnUKDpZk5mu57gTcFoEWxDf4LKZtHx9RE 2/0cbCXTcjCdB8Jws326F1kSSaTllFPc8W/3wfS+vdLgIJvTUa3AOw7Trvz3Dvxx9kg/N0S1UIw TJcqRYbO7DOtEIN0VbEVL+3hJlD0IxRcWZvWb5e45UBwYFXfzca1rBr6XNqMUw7cnVZ1XBs4LBb vaxkEpalT/z+P1VU2nfx6k5rSmLBDPdP X-Google-Smtp-Source: AGHT+IErOKIMxJ7z8Prhwwcxg/G6mO/1mbw/q3xeCK5+GWToGSyXHyYG113tntOqe2KVodehdeY5KQ== X-Received: by 2002:a05:600c:1c83:b0:434:a4b3:5ebe with SMTP id 5b1f17b1804b1-439ae21ce20mr83506775e9.24.1740395739490; Mon, 24 Feb 2025 03:15:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 11/12] fpu: Don't compile-time disable hardfloat for PPC targets Date: Mon, 24 Feb 2025 11:15:23 +0000 Message-ID: <20250224111524.1101196-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We happen to know that for the PPC target the FP status flags (and in particular float_flag_inexact) will always be cleared before a floating point operation, and so can_use_fpu() will always return false. So we speed things up a little by forcing QEMU_NO_HARDFLOAT to true on that target. We would like to build softfloat once for all targets; that means removing target-specific ifdefs. Remove the check for TARGET_PPC; this won't change behaviour because can_use_fpu() will see that float_flag_inexact is clear and take the softfloat path anyway. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250217125055.160887-10-peter.maydell@linaro.org --- fpu/softfloat.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b299cfaf860..b38eea8d879 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -220,11 +220,9 @@ GEN_INPUT_FLUSH3(float64_input_flush3, float64) * the use of hardfloat, since hardfloat relies on the inexact flag being * already set. */ -#if defined(TARGET_PPC) || defined(__FAST_MATH__) # if defined(__FAST_MATH__) # warning disabling hardfloat due to -ffast-math: hardfloat requires an exact \ IEEE implementation -# endif # define QEMU_NO_HARDFLOAT 1 # define QEMU_SOFTFLOAT_ATTR QEMU_FLATTEN #else From patchwork Mon Feb 24 11:15:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13987822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C89AC021A4 for ; Mon, 24 Feb 2025 11:16:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmWRO-0005qZ-Ge; Mon, 24 Feb 2025 06:16:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmWR7-0005oF-0x for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:57 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tmWR4-0001AF-Ge for qemu-devel@nongnu.org; Mon, 24 Feb 2025 06:15:44 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-43995b907cfso25514195e9.3 for ; Mon, 24 Feb 2025 03:15:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740395740; x=1741000540; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4UDGq1/nftyfWIeWE3zhkfJ5qF1yxDplS+dEScuvFz8=; b=B7lLdMqyYY4f4XzJ2CT7jIEDkIQ1HeL8LkDRuIsWJ6eGfThRBU1G1zFEFOM8erV9+B hpSwvDSNGE57SNQpEZgMSLXsdspdWYGm85Beq9wkqAueurr6q+iFJ57K25s6fDLoCyHV EmSzQigfGA1V68/yhFg4PFY7kmTrctcKMhpESF2fvLWk07tUXxliXLaqY3+pNqE8d1BJ ufp3fJ/bMKRaLDJK1OzZ+yFxyfxLk1QbpUlyD4qBTNKPZO58Iu//GEEB+CSqADG4KTjz U2KVMQLj6e/smfLyzrLFRfdXK5hzP2hXaRSOddvmJTJmVoBuQCwI/9GZpi2drgNxRFi1 LsHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740395740; x=1741000540; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4UDGq1/nftyfWIeWE3zhkfJ5qF1yxDplS+dEScuvFz8=; b=inKAmfE7JWYskhcQIPh8LHJgY0R7Fh6SIxc3ViEw6SwnK8TaEKMpJ/pVWG6s2rYtME qjtLhyMajq3cyW9+Tpq7jDrZVIbiiVGFt1nBsEwcKl+GbVhBXB+wsnODkuChzkE88MOv 9ba2HFuFn8op4ejUAvWpjT8GZDzrkNdBXtMPFwJ4aWpi6JePQND48KCyvirSrcCZlY9T RwlPHnN5pVa7l1QqlANxU25t4HFVzVaBhD46Nhg9KKX3i9QMFtvjStfO2UGjyQb3frd4 o4gkO8iVheXzr1KXkyJzmECuLMwt/YmgeHDtYymQStMokMITc0rK+j/uXzJuXphFA6Nd wEPg== X-Gm-Message-State: AOJu0Ywk0p3cJn0UFP/dvtrUA9EBYvnzS/8W0x0tSBhwNiaiARL5DwXK j9CCH2zuMFYeohdkfMy2YiBtE3NsZL0LAuN/revELNxYZYPB2ygdbVAbrZ3yOq02BH0FhAgToYZ l X-Gm-Gg: ASbGnctMGsQYfKWjBLigIM9lqZU5StvbtdxDlw5CPm2KG0T0jJ59FRz/AZEGC8GAFLo pdWv/Azx2hjL+/a6e4vq0NZdvkO4WoZGJZtHK2R7zo6eIXDuLx+RPtBKm/pKiSpbQjVfPdq6E6F DMzGrd6VJn15r7hmp2DAaO7jEyAG/+5FeQz8jlwyat9DJeawYGVvyhb0YeRzbYGyraIVuxXniII lGBUz8URvKKbmtDCYc3SUWimjH6E6EwhoU0SHZ/ChvCiu0u+TtKptDRju81hrxsOfm+LH3ugGgr TxU2hfDJcz3ZqtqDiHYl4Lg3eYGAMJkU X-Google-Smtp-Source: AGHT+IEDuyTkS81O1UdbaFlosz8KvxAoiInng2rPvJzcNgQKDUCuU5NcwztStQKuxlfnPxF27YsPZQ== X-Received: by 2002:a05:600c:548b:b0:439:89e9:4f06 with SMTP id 5b1f17b1804b1-439ae1f1873mr121508685e9.14.1740395740487; Mon, 24 Feb 2025 03:15:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b037214asm101447705e9.38.2025.02.24.03.15.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 03:15:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 12/12] fpu: Build only once Date: Mon, 24 Feb 2025 11:15:24 +0000 Message-ID: <20250224111524.1101196-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250224111524.1101196-1-peter.maydell@linaro.org> References: <20250224111524.1101196-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now we have removed all the target-specifics from the softfloat code, we can switch to building it once for the whole system rather than once per target. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20250217125055.160887-11-peter.maydell@linaro.org --- fpu/softfloat.c | 3 --- fpu/meson.build | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b38eea8d879..34c962d6bd9 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -79,9 +79,6 @@ this code that are retained. * version 2 or later. See the COPYING file in the top-level directory. */ -/* softfloat (and in particular the code in softfloat-specialize.h) is - * target-dependent and needs the TARGET_* macros. - */ #include "qemu/osdep.h" #include #include "qemu/bitops.h" diff --git a/fpu/meson.build b/fpu/meson.build index 1a9992ded56..646c76f0c69 100644 --- a/fpu/meson.build +++ b/fpu/meson.build @@ -1 +1 @@ -specific_ss.add(when: 'CONFIG_TCG', if_true: files('softfloat.c')) +common_ss.add(when: 'CONFIG_TCG', if_true: files('softfloat.c'))