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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b02d6837sm109356675e9.13.2025.02.24.08.07.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 08:07:11 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 690c9190-f2c9-11ef-9aae-95dc52dad729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1740413233; x=1741018033; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JvCaSQyWyY+FfA/0O37EX9qIMHCSri3oO6tt1sgXoWI=; b=ViPtUzDw465K6WlJUNmHTgZlKAFWw57mV/QMQg/C/L8PIkWGIbIhW7X2gsPOLyPvJv u+yBnnJDnm1pbuq8PzL20LJEhyocObxgRI5DceeBdAe1kdV0rILOhb89p/u3A5IGcjTM iM6j0Ypgbc/0w6JuNXD3tiaq5e0bjQnaTvaBE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740413233; x=1741018033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JvCaSQyWyY+FfA/0O37EX9qIMHCSri3oO6tt1sgXoWI=; b=m90XipnWIA7mwKNOc410GNZmZIm8s00Av5fuiciIA9TwP6MP5l1bXmdMQkzRccj6iF GOkIYYXGznk/+wFdQSM3IBBQrScunRvw3jnNEVpxjUvTm9mN05zk/oJK6N1jq420rhWv ru9oVS4H5licaMSslbSdkMKYd0ebSyFigGhiskUncj00xS1Odd+o712u45mA0nI0dXsw 3jLNhzUOfkV/fSYhILG9Kp7Spi2pAcw54Z6AQUoFxerXLuEqgJd82k+QBvuZhgg/m5st PsmASslXX8WrrRv2i0KnB3RSaXDQtPID5D28gmgGluxAZPYPUQgsUcC7OUfL2lHdWADg VZGA== X-Gm-Message-State: AOJu0YxtDalCEfJu/PoBIoGTndsVXE1YPNno7ZmNN8sNzkFf/jOQT0iE 3XZT9SuvF8V1KRwMNYglYIeN6NVgd+OxlPVh07lvI9CwBcH2f7ufo5QO9CueRE9VD7FFf9SUWaY 8 X-Gm-Gg: ASbGncvid2eo6T4kBP3JHHc6Of9+xD0bGGezvEdC3J0+s7a254NtIy1MB53lXPSDcQ7 SJF8rDdbGCevDvvCF2LFnchLN5CTaGFtiYyn1aPuIc6uvqD1SoQPBMjnOrdoV2sUd9MCrawHzMn 0lO1wQ5NhqlONxhCmFOMKFphemdQQwsDEXPg9XM2m6zmvCkj3qCHHc+oNFr2C7+/+pb7pHnRq56 CKm8PZ/Pd0Hpi+WihAQgHzYvh1FAJw1lSDz0ppYMIN1aaagD8D6QMAT4XTUjozy57GSuYBQqVVb cWCBRwncmoqin1Ego2SGEzRz5JRbzIhrP6EVNNoLtt5BoXcien43WRM4SmFL2YJgxHPE0GPoVaL cB9Z5Gg== X-Google-Smtp-Source: AGHT+IHpCNuKguKsVgryvYncGdJmySmys+0NiLMW5l1uYv1H3AVOCvOB6AXKqOdatQ8d1+juBkhxyw== X-Received: by 2002:a05:600c:1c83:b0:434:a4b3:5ebe with SMTP id 5b1f17b1804b1-439ae21ce20mr91851365e9.24.1740413232063; Mon, 24 Feb 2025 08:07:12 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 1/8] x86: Sort includes in various files Date: Mon, 24 Feb 2025 16:05:02 +0000 Message-Id: <20250224160509.1117847-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250224160509.1117847-1-andrew.cooper3@citrix.com> References: <20250224160509.1117847-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 FRED support involves quite a lot of header file shuffling and cleanup. Start by sorting the includes of impacted files, and dropping duplciates. domain.c: Double asm/spec_ctrl.h power.c: Double xen/sched.h setup.c: Double xen/serial.h mm.c: Double xen/mm.h No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné No difference in compiled binary either, except for embedded line numbers. --- xen/arch/x86/acpi/power.c | 19 ++++---- xen/arch/x86/cpu/common.c | 15 ++++--- xen/arch/x86/crash.c | 32 +++++++------- xen/arch/x86/domain.c | 84 ++++++++++++++++++------------------ xen/arch/x86/hvm/vmx/vmcs.c | 25 +++++------ xen/arch/x86/machine_kexec.c | 5 ++- xen/arch/x86/mm.c | 54 ++++++++++++----------- xen/arch/x86/setup.c | 84 ++++++++++++++++++------------------ xen/arch/x86/smpboot.c | 22 +++++----- xen/arch/x86/traps.c | 79 +++++++++++++++++---------------- xen/arch/x86/x86_64/traps.c | 25 ++++++----- 11 files changed, 229 insertions(+), 215 deletions(-) diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c index 08a7fc250800..d0b67614d521 100644 --- a/xen/arch/x86/acpi/power.c +++ b/xen/arch/x86/acpi/power.c @@ -11,28 +11,29 @@ */ #include +#include +#include +#include #include #include +#include #include #include -#include -#include #include -#include -#include -#include -#include #include -#include -#include -#include + +#include #include #include +#include #include #include #include +#include #include +#include + #include uint32_t system_reset_counter = 1; diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 067d855badf0..1cc4adccb471 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -1,24 +1,25 @@ -#include -#include #include +#include #include #include +#include #include +#include #include #include #include -#include -#include -#include #include #include -#include +#include +#include #include #include #include #include -#include /* for XEN_INVALID_{SOCKET,CORE}_ID */ +#include + +#include #include "cpu.h" #include "mcheck/x86_mca.h" diff --git a/xen/arch/x86/crash.c b/xen/arch/x86/crash.c index 26057c71d3c9..4afe0ad859a7 100644 --- a/xen/arch/x86/crash.c +++ b/xen/arch/x86/crash.c @@ -8,27 +8,29 @@ * - Magnus Damm */ -#include -#include -#include -#include -#include -#include +#include +#include #include #include -#include -#include -#include +#include +#include #include -#include #include -#include -#include +#include +#include +#include +#include +#include + #include -#include -#include +#include +#include #include -#include +#include +#include +#include + +#include static cpumask_t waiting_to_crash; static unsigned int crashing_cpu; diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 78a13e6812c9..7b2549091fd3 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -11,66 +11,68 @@ * Gareth Hughes , May 2000 */ -#include -#include -#include -#include -#include -#include +#include +#include +#include +#include #include -#include +#include +#include +#include #include +#include +#include +#include #include +#include #include -#include +#include +#include #include -#include -#include -#include -#include -#include -#include -#include #include -#include +#include +#include +#include +#include +#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include + +#include +#include #include -#include -#include +#include +#include #include #include #include #include -#include +#include +#include +#include +#include +#include +#include #include +#include +#include +#include +#include +#include +#include #include +#include #include -#include -#include -#include -#include +#include #include +#include + +#include +#include +#include + #ifdef CONFIG_COMPAT #include #endif -#include -#include -#include -#include -#include DEFINE_PER_CPU(struct vcpu *, curr_vcpu); diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 8c0ea789c1a3..fa9d8b3267ea 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -4,33 +4,34 @@ * Copyright (c) 2004, Intel Corporation. */ -#include -#include -#include -#include -#include #include +#include #include +#include #include #include +#include +#include +#include #include -#include + +#include #include -#include -#include -#include +#include +#include #include #include #include +#include #include #include -#include -#include #include +#include +#include #include #include #include -#include +#include static bool __read_mostly opt_vpid_enabled = true; boolean_param("vpid", opt_vpid_enabled); diff --git a/xen/arch/x86/machine_kexec.c b/xen/arch/x86/machine_kexec.c index d50772ad6ca3..e20e8d0b1563 100644 --- a/xen/arch/x86/machine_kexec.c +++ b/xen/arch/x86/machine_kexec.c @@ -15,14 +15,15 @@ * Version 2. See the file COPYING for more details. */ -#include #include #include #include +#include + #include #include -#include #include +#include /* * Add a mapping for a page to the page tables used during kexec. diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index fa21903eb25a..6b34b908efcd 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -87,51 +87,53 @@ * doing the final put_page(), and remove it from the iommu if so. */ +#include +#include +#include +#include +#include +#include +#include #include +#include #include +#include #include #include #include #include #include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include #include +#include +#include +#include #include #include -#include -#include -#include -#include -#include -#include + +#include +#include #include +#include #include +#include #include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include -#include #include #include +#include +#include +#include #include +#include + +#include +#include + +#include #ifdef CONFIG_PV #include "pv/mm.h" diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 8ebe5a9443f3..143749e5da5b 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1,68 +1,70 @@ -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include #include +#include +#include +#include +#include +#include +#include +#include +#include #include +#include +#include #include -#include #include #include #include -#include -#include -#include -#include #include -#include -#include #include -#include -#include -#include -#include #include -#include -#include -#include #include #include -#include -#ifdef CONFIG_COMPAT -#include -#include -#endif -#include -#include -#include -#include -#include + +#include #include -#include +#include +#include +#include #include -#include #include -#include #include -#include -#include -#include /* for bzimage_headroom */ #include +#include +#include #include -#include -#include -#include -#include -#include #include -#include -#include -#include -#include #include +#include +#include +#include +#include +#include #include #include +#include +#include +#include +#include #include +#include + +#include +#ifdef CONFIG_COMPAT +#include +#include +#endif + /* opt_nosmp: If true, secondary processors are ignored. */ static bool __initdata opt_nosmp; boolean_param("nosmp", opt_nosmp); diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 891a29fca146..f904d5623272 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -7,39 +7,39 @@ * (c) 1998, 1999, 2000 Ingo Molnar */ +#include +#include +#include +#include #include +#include #include #include -#include -#include +#include #include -#include -#include +#include #include #include -#include -#include -#include #include -#include #include #include -#include #include #include #include #include +#include +#include +#include #include #include #include #include #include #include -#include #include +#include #include -#include uint32_t __ro_after_init trampoline_phys; enum ap_boot_method __read_mostly ap_boot_method = AP_BOOT_NORMAL; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index dca11a613dbd..e8d5aa9fd46b 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -12,68 +12,71 @@ * Gareth Hughes , May 2000 */ +#include #include -#include -#include -#include +#include +#include +#include #include #include +#include +#include #include +#include +#include +#include +#include +#include +#include #include +#include #include -#include -#include -#include -#include -#include -#include -#include -#include #include +#include +#include #include -#include +#include #include -#include -#include -#include #include -#include +#include #include #include -#include -#include -#include + +#include #include -#include -#include +#include #include -#include -#include +#include #include -#include +#include +#include +#include #include -#include +#include +#include +#include +#include #include #include -#include +#include +#include +#include +#include #include -#include +#include +#include +#include #include -#include -#include -#include -#include -#include +#include #include +#include +#include +#include + #include #include -#include + #include -#include -#include -#include -#include -#include /* * opt_nmi: one of 'ignore', 'dom0', or 'fatal'. diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index 02fdb3637d09..93f32ac66c92 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -1,28 +1,27 @@ - -#include +#include +#include +#include +#include #include -#include +#include #include -#include #include -#include -#include -#include #include #include -#include +#include +#include #include -#include + #include -#include -#include #include #include -#include +#include +#include #include +#include #include #include -#include +#include static void print_xen_info(void) From patchwork Mon Feb 24 16:05:03 2025 Content-Type: text/plain; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b02d6837sm109356675e9.13.2025.02.24.08.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 08:07:12 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 69429b96-f2c9-11ef-9aae-95dc52dad729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1740413233; x=1741018033; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mSib/EZ8nx2SutdLKPSjtycKdGYhGJ9Th7LeAr9+rZg=; b=Tzo17SChrOR55/xre0GA5ooioj2s8YPNoINE/8+Na4lO+8GcNnrtZFDJgcYjw2NnDM fQMUoQadqxBOyxv7l5aRqrG1wHxIi/bjD5hwDBAYPNp0imcgzN1kj5kN6idl5yCjwXCL 5JvqXktkA6FqthKSzKi+in2R8IQIA5DB2Y4E4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740413233; x=1741018033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mSib/EZ8nx2SutdLKPSjtycKdGYhGJ9Th7LeAr9+rZg=; b=Xz++5rGVR1cuYwyr/MNc6+7ZX20fBnrOyD0Edj4WfcTy/57ufLeSL6/GgeRMozfHvf VYs6EKbXJ15rj+0wkzmf9V1uSxf7yMwHoxhSC7G2I04J0Dtqm56Q2VzISTQQCXZpc72L zBw6iItLp5gCquBGjuSGmXKmyPUHk4huuMbB2jcCKox3YVELw/LHjUv+cDtqiNYZJDnp kJUAjmddbxC2a7m5AU21QPccLqgqBFkP5/Pyx/ReJKwvY/VEBRnIchlTEExeYt2Tkg28 sqxkPPv0knojp4rN4KRiVVO/QacSOx1aQ3JaEw8LgWvxgXKQWvqqNy+c/k5mki4OuaEQ uE+A== X-Gm-Message-State: AOJu0YxjFUAomSMdWvhKxVqDDYUenPhubnhbhEkzlr7d8e5F4G9hW+w6 STRTPGwaSc/2GBsrQ4GinibKiopNUpmNURBS6XEG3LRqMXk5RBa7RFf0l7ymhhKi4YUrdQGgENh j X-Gm-Gg: ASbGnctc+BDERw8jyYzECULJQR69s1NX2kKYSsiuxrBXuQHUnpPIgbjjoMA/6l8If3B dv9R0wUcG5/YtlAxIrHukveDoEABE8McckfJtO0mVJwe/g5sQJ6FqvR7gFtbnIXtgm2OusmJPc3 943G6OO7zfx1+bIAWiPxSyyJ6xH61FcqZ4tj5aUNsk6cJ/wftVYSYbyBsNJVefWx7ZQBysiyWHO UZDX5Yd8s1ZWCw749AgmFan1v3E5Rp8kHxabma3F4BxHw9XX/18O9A80G7MR1Rt3mA1OdUb5JTZ h6PAhsrkFtxDE6aaM8oexmLu2PZTXeiSNTgRStbdqH/lAK7MaliZyKMrlisO09FDlX+c//BCl4O UFH+Lug== X-Google-Smtp-Source: AGHT+IFqiZjcx54aS0d8m6rMm6a0JZlZM8YL4Z03n29WxxFUBcrA3joDJSEXAa/m9b7miLumtpU8Sw== X-Received: by 2002:a05:600c:1c08:b0:434:f0df:9f6 with SMTP id 5b1f17b1804b1-439ae1d97fbmr116167785e9.3.1740413232912; Mon, 24 Feb 2025 08:07:12 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 2/8] x86/IDT: Collect IDT related content idt.h Date: Mon, 24 Feb 2025 16:05:03 +0000 Message-Id: <20250224160509.1117847-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250224160509.1117847-1-andrew.cooper3@citrix.com> References: <20250224160509.1117847-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Logic concerning the IDT is somewhat different to the other system tables, and in particular ought not to be in asm/processor.h. Collect it together a new header. While doing so, make a few minor adjustments: * Make set_ist() use volatile rather than ACCESS_ONCE(), as _write_gate_lower() already does, removing the need for xen/lib.h. * Move the BUILD_BUG_ON() from subarch_percpu_traps_init() into mm.c's build_assertions(), rather than including idt.h into x86_64/traps.c. * Drop UL from IST constants. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/cpu/common.c | 1 + xen/arch/x86/crash.c | 1 + xen/arch/x86/domain.c | 1 + xen/arch/x86/hvm/svm/svm.c | 1 + xen/arch/x86/hvm/vmx/vmcs.c | 1 + xen/arch/x86/include/asm/desc.h | 76 ---------------- xen/arch/x86/include/asm/idt.h | 125 +++++++++++++++++++++++++++ xen/arch/x86/include/asm/processor.h | 37 -------- xen/arch/x86/machine_kexec.c | 1 + xen/arch/x86/mm.c | 4 + xen/arch/x86/pv/traps.c | 1 + xen/arch/x86/smpboot.c | 1 + xen/arch/x86/traps.c | 1 + xen/arch/x86/x86_64/traps.c | 3 - 14 files changed, 138 insertions(+), 116 deletions(-) create mode 100644 xen/arch/x86/include/asm/idt.h diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 1cc4adccb471..1540ab0007a0 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/crash.c b/xen/arch/x86/crash.c index 4afe0ad859a7..5f7d7b392a1f 100644 --- a/xen/arch/x86/crash.c +++ b/xen/arch/x86/crash.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 7b2549091fd3..d3db76833f3c 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 62905c2c7acd..ea78da4f4210 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index fa9d8b3267ea..0136830ebcb7 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/include/asm/desc.h b/xen/arch/x86/include/asm/desc.h index a1e0807d97ed..85fae6b2f9ae 100644 --- a/xen/arch/x86/include/asm/desc.h +++ b/xen/arch/x86/include/asm/desc.h @@ -115,82 +115,6 @@ typedef union { }; } seg_desc_t; -typedef union { - struct { - uint64_t a, b; - }; - struct { - uint16_t addr0; - uint16_t cs; - uint8_t ist; /* :3, 5 bits rsvd, but this yields far better code. */ - uint8_t type:4, s:1, dpl:2, p:1; - uint16_t addr1; - uint32_t addr2; - /* 32 bits rsvd. */ - }; -} idt_entry_t; - -/* Write the lower 64 bits of an IDT Entry. This relies on the upper 32 - * bits of the address not changing, which is a safe assumption as all - * functions we are likely to load will live inside the 1GB - * code/data/bss address range. - * - * Ideally, we would use cmpxchg16b, but this is not supported on some - * old AMD 64bit capable processors, and has no safe equivalent. - */ -static inline void _write_gate_lower(volatile idt_entry_t *gate, - const idt_entry_t *new) -{ - ASSERT(gate->b == new->b); - gate->a = new->a; -} - -#define _set_gate(gate_addr,type,dpl,addr) \ -do { \ - (gate_addr)->a = 0; \ - smp_wmb(); /* disable gate /then/ rewrite */ \ - (gate_addr)->b = \ - ((unsigned long)(addr) >> 32); \ - smp_wmb(); /* rewrite /then/ enable gate */ \ - (gate_addr)->a = \ - (((unsigned long)(addr) & 0xFFFF0000UL) << 32) | \ - ((unsigned long)(dpl) << 45) | \ - ((unsigned long)(type) << 40) | \ - ((unsigned long)(addr) & 0xFFFFUL) | \ - ((unsigned long)__HYPERVISOR_CS << 16) | \ - (1UL << 47); \ -} while (0) - -static inline void _set_gate_lower(idt_entry_t *gate, unsigned long type, - unsigned long dpl, void *addr) -{ - idt_entry_t idte; - idte.b = gate->b; - idte.a = - (((unsigned long)(addr) & 0xFFFF0000UL) << 32) | - ((unsigned long)(dpl) << 45) | - ((unsigned long)(type) << 40) | - ((unsigned long)(addr) & 0xFFFFUL) | - ((unsigned long)__HYPERVISOR_CS << 16) | - (1UL << 47); - _write_gate_lower(gate, &idte); -} - -/* Update the lower half handler of an IDT Entry, without changing any - * other configuration. */ -static inline void _update_gate_addr_lower(idt_entry_t *gate, void *addr) -{ - idt_entry_t idte; - idte.a = gate->a; - - idte.b = ((unsigned long)(addr) >> 32); - idte.a &= 0x0000FFFFFFFF0000ULL; - idte.a |= (((unsigned long)(addr) & 0xFFFF0000UL) << 32) | - ((unsigned long)(addr) & 0xFFFFUL); - - _write_gate_lower(gate, &idte); -} - #define _set_tssldt_desc(desc,addr,limit,type) \ do { \ (desc)[0].b = (desc)[1].b = 0; \ diff --git a/xen/arch/x86/include/asm/idt.h b/xen/arch/x86/include/asm/idt.h new file mode 100644 index 000000000000..4ef52050a11b --- /dev/null +++ b/xen/arch/x86/include/asm/idt.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef X86_ASM_IDT_H +#define X86_ASM_IDT_H + +#include +#include + +#include + +#define IST_NONE 0 +#define IST_MCE 1 +#define IST_NMI 2 +#define IST_DB 3 +#define IST_DF 4 +#define IST_MAX 4 + +typedef union { + struct { + uint64_t a, b; + }; + struct { + uint16_t addr0; + uint16_t cs; + uint8_t ist; /* :3, 5 bits rsvd, but this yields far better code. */ + uint8_t type:4, s:1, dpl:2, p:1; + uint16_t addr1; + uint32_t addr2; + /* 32 bits rsvd. */ + }; +} idt_entry_t; + +#define IDT_ENTRIES 256 +extern idt_entry_t idt_table[]; +extern idt_entry_t *idt_tables[]; + +/* + * Set the Interrupt Stack Table used by a particular IDT entry. Typically + * used on a live IDT, so volatile to disuade clever optimisations. + */ +static inline void set_ist(volatile idt_entry_t *idt, unsigned int ist) +{ + /* IST is a 3 bit field, 32 bits into the IDT entry. */ + ASSERT(ist <= IST_MAX); + + idt->ist = ist; +} + +static inline void enable_each_ist(idt_entry_t *idt) +{ + set_ist(&idt[X86_EXC_DF], IST_DF); + set_ist(&idt[X86_EXC_NMI], IST_NMI); + set_ist(&idt[X86_EXC_MC], IST_MCE); + set_ist(&idt[X86_EXC_DB], IST_DB); +} + +static inline void disable_each_ist(idt_entry_t *idt) +{ + set_ist(&idt[X86_EXC_DF], IST_NONE); + set_ist(&idt[X86_EXC_NMI], IST_NONE); + set_ist(&idt[X86_EXC_MC], IST_NONE); + set_ist(&idt[X86_EXC_DB], IST_NONE); +} + +/* + * Write the lower 64 bits of an IDT Entry. This relies on the upper 32 + * bits of the address not changing, which is a safe assumption as all + * functions we are likely to load will live inside the 1GB + * code/data/bss address range. + */ +static inline void _write_gate_lower(volatile idt_entry_t *gate, + const idt_entry_t *new) +{ + ASSERT(gate->b == new->b); + gate->a = new->a; +} + +#define _set_gate(gate_addr,type,dpl,addr) \ +do { \ + (gate_addr)->a = 0; \ + smp_wmb(); /* disable gate /then/ rewrite */ \ + (gate_addr)->b = \ + ((unsigned long)(addr) >> 32); \ + smp_wmb(); /* rewrite /then/ enable gate */ \ + (gate_addr)->a = \ + (((unsigned long)(addr) & 0xFFFF0000UL) << 32) | \ + ((unsigned long)(dpl) << 45) | \ + ((unsigned long)(type) << 40) | \ + ((unsigned long)(addr) & 0xFFFFUL) | \ + ((unsigned long)__HYPERVISOR_CS << 16) | \ + (1UL << 47); \ +} while (0) + +static inline void _set_gate_lower(idt_entry_t *gate, unsigned long type, + unsigned long dpl, void *addr) +{ + idt_entry_t idte; + idte.b = gate->b; + idte.a = + (((unsigned long)(addr) & 0xFFFF0000UL) << 32) | + ((unsigned long)(dpl) << 45) | + ((unsigned long)(type) << 40) | + ((unsigned long)(addr) & 0xFFFFUL) | + ((unsigned long)__HYPERVISOR_CS << 16) | + (1UL << 47); + _write_gate_lower(gate, &idte); +} + +/* + * Update the lower half handler of an IDT entry, without changing any other + * configuration. + */ +static inline void _update_gate_addr_lower(idt_entry_t *gate, void *addr) +{ + idt_entry_t idte; + idte.a = gate->a; + + idte.b = ((unsigned long)(addr) >> 32); + idte.a &= 0x0000FFFFFFFF0000ULL; + idte.a |= (((unsigned long)(addr) & 0xFFFF0000UL) << 32) | + ((unsigned long)(addr) & 0xFFFFUL); + + _write_gate_lower(gate, &idte); +} + +#endif /* X86_ASM_IDT_H */ diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/asm/processor.h index d247ef8dd226..86174cce5821 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -353,43 +353,6 @@ struct tss_page { }; DECLARE_PER_CPU(struct tss_page, tss_page); -#define IST_NONE 0UL -#define IST_MCE 1UL -#define IST_NMI 2UL -#define IST_DB 3UL -#define IST_DF 4UL -#define IST_MAX 4UL - -/* Set the Interrupt Stack Table used by a particular IDT entry. */ -static inline void set_ist(idt_entry_t *idt, unsigned int ist) -{ - /* IST is a 3 bit field, 32 bits into the IDT entry. */ - ASSERT(ist <= IST_MAX); - - /* Typically used on a live idt. Disuade any clever optimisations. */ - ACCESS_ONCE(idt->ist) = ist; -} - -static inline void enable_each_ist(idt_entry_t *idt) -{ - set_ist(&idt[X86_EXC_DF], IST_DF); - set_ist(&idt[X86_EXC_NMI], IST_NMI); - set_ist(&idt[X86_EXC_MC], IST_MCE); - set_ist(&idt[X86_EXC_DB], IST_DB); -} - -static inline void disable_each_ist(idt_entry_t *idt) -{ - set_ist(&idt[X86_EXC_DF], IST_NONE); - set_ist(&idt[X86_EXC_NMI], IST_NONE); - set_ist(&idt[X86_EXC_MC], IST_NONE); - set_ist(&idt[X86_EXC_DB], IST_NONE); -} - -#define IDT_ENTRIES 256 -extern idt_entry_t idt_table[]; -extern idt_entry_t *idt_tables[]; - DECLARE_PER_CPU(root_pgentry_t *, root_pgt); extern void write_ptbase(struct vcpu *v); diff --git a/xen/arch/x86/machine_kexec.c b/xen/arch/x86/machine_kexec.c index e20e8d0b1563..f775e526d59b 100644 --- a/xen/arch/x86/machine_kexec.c +++ b/xen/arch/x86/machine_kexec.c @@ -22,6 +22,7 @@ #include #include +#include #include #include diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 6b34b908efcd..bfdc8fb01949 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -115,6 +115,7 @@ #include #include #include +#include #include #include #include @@ -6639,6 +6640,9 @@ static void __init __maybe_unused build_assertions(void) * using different PATs will not work. */ BUILD_BUG_ON(XEN_MSR_PAT != 0x050100070406ULL); + + /* IST_MAX IST pages + at least 1 guard page + primary stack. */ + BUILD_BUG_ON((IST_MAX + 1) * PAGE_SIZE + PRIMARY_STACK_SIZE > STACK_SIZE); } /* diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index fd1597d0bdea..77b034e4dc73 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index f904d5623272..f3d60d5bae35 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index e8d5aa9fd46b..1a53bb4aa481 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index 93f32ac66c92..8b9f0949d348 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -342,9 +342,6 @@ void subarch_percpu_traps_init(void) unsigned char *stub_page; unsigned int offset; - /* IST_MAX IST pages + at least 1 guard page + primary stack. */ - BUILD_BUG_ON((IST_MAX + 1) * PAGE_SIZE + PRIMARY_STACK_SIZE > STACK_SIZE); - /* No PV guests? No need to set up SYSCALL/SYSENTER infrastructure. */ if ( !IS_ENABLED(CONFIG_PV) ) return; From patchwork Mon Feb 24 16:05:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13988433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B20EC021A4 for ; Mon, 24 Feb 2025 16:07:39 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.895266.1303874 (Exim 4.92) (envelope-from ) id 1tmazF-0004DD-FK; Mon, 24 Feb 2025 16:07:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 895266.1303874; Mon, 24 Feb 2025 16:07:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tmazF-0004Al-AI; Mon, 24 Feb 2025 16:07:17 +0000 Received: by outflank-mailman (input) for mailman id 895266; Mon, 24 Feb 2025 16:07:16 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tmazE-0003oc-81 for xen-devel@lists.xenproject.org; Mon, 24 Feb 2025 16:07:16 +0000 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [2a00:1450:4864:20::331]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 69aa6914-f2c9-11ef-9aae-95dc52dad729; Mon, 24 Feb 2025 17:07:14 +0100 (CET) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-43996e95114so29965215e9.3 for ; Mon, 24 Feb 2025 08:07:14 -0800 (PST) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. 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Make the existing constant more precise. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/hvm/vlapic.c | 4 ++-- xen/arch/x86/hvm/vmx/intr.c | 4 ++-- xen/arch/x86/hvm/vmx/vmcs.c | 2 +- xen/arch/x86/hvm/vmx/vmx.c | 6 +++--- xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 4 ++-- xen/arch/x86/include/asm/irq.h | 4 ++-- xen/arch/x86/include/asm/x86-defns.h | 2 +- xen/arch/x86/io_apic.c | 2 +- xen/arch/x86/irq.c | 12 ++++++------ xen/arch/x86/pv/callback.c | 4 ++-- xen/arch/x86/pv/domain.c | 4 ++-- xen/arch/x86/traps.c | 4 ++-- xen/arch/x86/x86_64/entry.S | 2 +- 13 files changed, 27 insertions(+), 27 deletions(-) diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index 3363926b487b..91fc45716514 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -72,7 +72,7 @@ static void vlapic_do_init(struct vlapic *vlapic); static int vlapic_find_highest_vector(const void *bitmap) { const uint32_t *word = bitmap; - unsigned int word_offset = X86_NR_VECTORS / 32; + unsigned int word_offset = X86_IDT_VECTORS / 32; /* Work backwards through the bitmap (first 32-bit word in every four). */ while ( (word_offset != 0) && (word[(--word_offset)*4] == 0) ) @@ -665,7 +665,7 @@ int guest_rdmsr_x2apic(const struct vcpu *v, uint32_t msr, uint64_t *val) REG(LVT0) | REG(LVT1) | REG(LVTERR) | REG(TMICT) | REG(TMCCT) | REG(TDCR) | #undef REG -#define REGBLOCK(x) (((1UL << (X86_NR_VECTORS / 32)) - 1) << (APIC_ ## x >> 4)) +#define REGBLOCK(x) (((1UL << (X86_IDT_VECTORS / 32)) - 1) << (APIC_ ## x >> 4)) REGBLOCK(ISR) | REGBLOCK(TMR) | REGBLOCK(IRR) #undef REGBLOCK }; diff --git a/xen/arch/x86/hvm/vmx/intr.c b/xen/arch/x86/hvm/vmx/intr.c index 1a4dfb499bcd..91b407e6bcc2 100644 --- a/xen/arch/x86/hvm/vmx/intr.c +++ b/xen/arch/x86/hvm/vmx/intr.c @@ -356,7 +356,7 @@ void asmlinkage vmx_intr_assist(void) { word = (const void *)&vlapic->regs->data[APIC_IRR]; printk(XENLOG_ERR "vIRR:"); - for ( i = X86_NR_VECTORS / 32; i-- ; ) + for ( i = X86_IDT_VECTORS / 32; i-- ; ) printk(" %08x", word[i*4]); printk("\n"); } @@ -366,7 +366,7 @@ void asmlinkage vmx_intr_assist(void) { word = (const void *)&pi_desc->pir; printk(XENLOG_ERR " PIR:"); - for ( i = X86_NR_VECTORS / 32; i-- ; ) + for ( i = X86_IDT_VECTORS / 32; i-- ; ) printk(" %08x", word[i]); printk("\n"); } diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 0136830ebcb7..20ab2d0f266f 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -1219,7 +1219,7 @@ static int construct_vmcs(struct vcpu *v) unsigned int i; /* EOI-exit bitmap */ - bitmap_zero(v->arch.hvm.vmx.eoi_exit_bitmap, X86_NR_VECTORS); + bitmap_zero(v->arch.hvm.vmx.eoi_exit_bitmap, X86_IDT_VECTORS); for ( i = 0; i < ARRAY_SIZE(v->arch.hvm.vmx.eoi_exit_bitmap); ++i ) __vmwrite(EOI_EXIT_BITMAP(i), 0); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index eee1d4b47a13..ff0ea9cf0e1d 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2199,7 +2199,7 @@ static void cf_check vmx_process_isr(int isr, struct vcpu *v) * is acceptable because the subsequent interrupts will set up the eoi * bitmap correctly. */ - for ( i = 0x10; i < X86_NR_VECTORS; ++i ) + for ( i = 0x10; i < X86_IDT_VECTORS; ++i ) if ( vlapic_test_vector(i, &vlapic->regs->data[APIC_IRR]) || vlapic_test_vector(i, &vlapic->regs->data[APIC_ISR]) ) set_bit(i, v->arch.hvm.vmx.eoi_exit_bitmap); @@ -2316,7 +2316,7 @@ static void cf_check vmx_sync_pir_to_irr(struct vcpu *v) { struct vlapic *vlapic = vcpu_vlapic(v); unsigned int group, i; - DECLARE_BITMAP(pending_intr, X86_NR_VECTORS); + DECLARE_BITMAP(pending_intr, X86_IDT_VECTORS); if ( !pi_test_and_clear_on(&v->arch.hvm.vmx.pi_desc) ) return; @@ -2324,7 +2324,7 @@ static void cf_check vmx_sync_pir_to_irr(struct vcpu *v) for ( group = 0; group < ARRAY_SIZE(pending_intr); group++ ) pending_intr[group] = pi_get_pir(&v->arch.hvm.vmx.pi_desc, group); - bitmap_for_each ( i, pending_intr, X86_NR_VECTORS ) + bitmap_for_each ( i, pending_intr, X86_IDT_VECTORS ) vlapic_set_vector(i, &vlapic->regs->data[APIC_IRR]); } diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h index e1d339814143..bfb234101154 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -71,7 +71,7 @@ struct vmx_msr_bitmap { }; struct pi_desc { - DECLARE_BITMAP(pir, X86_NR_VECTORS); + DECLARE_BITMAP(pir, X86_IDT_VECTORS); union { struct { u16 on : 1, /* bit 256 - Outstanding Notification */ @@ -138,7 +138,7 @@ struct vmx_vcpu { unsigned int host_msr_count; unsigned long eoi_exitmap_changed; - DECLARE_BITMAP(eoi_exit_bitmap, X86_NR_VECTORS); + DECLARE_BITMAP(eoi_exit_bitmap, X86_IDT_VECTORS); struct pi_desc pi_desc; unsigned long host_cr0; diff --git a/xen/arch/x86/include/asm/irq.h b/xen/arch/x86/include/asm/irq.h index 354868ba31ab..f9ed5dc86cb3 100644 --- a/xen/arch/x86/include/asm/irq.h +++ b/xen/arch/x86/include/asm/irq.h @@ -23,7 +23,7 @@ extern unsigned int nr_irqs; #define LEGACY_VECTOR(irq) ((irq) + FIRST_LEGACY_VECTOR) typedef struct { - DECLARE_BITMAP(_bits, X86_NR_VECTORS); + DECLARE_BITMAP(_bits, X86_IDT_VECTORS); } vmask_t; struct irq_desc; @@ -96,7 +96,7 @@ struct arch_irq_desc { #define IRQ_VECTOR_UNASSIGNED (-1) -typedef int vector_irq_t[X86_NR_VECTORS]; +typedef int vector_irq_t[X86_IDT_VECTORS]; DECLARE_PER_CPU(vector_irq_t, vector_irq); extern bool opt_noirqbalance; diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h index 2493ec277f58..61b0cea8f37c 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -155,7 +155,7 @@ #define X86_INVPCID_ALL_INCL_GLOBAL 2 #define X86_INVPCID_ALL_NON_GLOBAL 3 -#define X86_NR_VECTORS 256 +#define X86_IDT_VECTORS 256 /* Exception Vectors */ #define X86_EXC_DE 0 /* Divide Error */ diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c index 68680c102f58..776dd57720a2 100644 --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -101,7 +101,7 @@ static void share_vector_maps(unsigned int src, unsigned int dst) return; bitmap_or(vector_map[src]->_bits, vector_map[src]->_bits, - vector_map[dst]->_bits, X86_NR_VECTORS); + vector_map[dst]->_bits, X86_IDT_VECTORS); for (pin = 0; pin < nr_ioapic_entries[dst]; ++pin) { int irq = apic_pin_2_gsi_irq(dst, pin); diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c index ff3ac832f4b9..f35894577bb0 100644 --- a/xen/arch/x86/irq.c +++ b/xen/arch/x86/irq.c @@ -51,7 +51,7 @@ static vmask_t global_used_vector_map; struct irq_desc __read_mostly *irq_desc = NULL; -static DECLARE_BITMAP(used_vectors, X86_NR_VECTORS); +static DECLARE_BITMAP(used_vectors, X86_IDT_VECTORS); static DEFINE_SPINLOCK(vector_lock); @@ -155,7 +155,7 @@ static int __init _bind_irq_vector(struct irq_desc *desc, int vector, cpumask_t online_mask; int cpu; - BUG_ON((unsigned)vector >= X86_NR_VECTORS); + BUG_ON((unsigned)vector >= X86_IDT_VECTORS); cpumask_and(&online_mask, cpu_mask, &cpu_online_map); if (cpumask_empty(&online_mask)) @@ -423,7 +423,7 @@ int __init init_irq_data(void) struct irq_desc *desc; int irq, vector; - for ( vector = 0; vector < X86_NR_VECTORS; ++vector ) + for ( vector = 0; vector < X86_IDT_VECTORS; ++vector ) this_cpu(vector_irq)[vector] = INT_MIN; irq_desc = xzalloc_array(struct irq_desc, nr_irqs); @@ -745,7 +745,7 @@ void setup_vector_irq(unsigned int cpu) unsigned int irq, vector; /* Clear vector_irq */ - for ( vector = 0; vector < X86_NR_VECTORS; ++vector ) + for ( vector = 0; vector < X86_IDT_VECTORS; ++vector ) per_cpu(vector_irq, cpu)[vector] = INT_MIN; /* Mark the inuse vectors */ for ( irq = 0; irq < nr_irqs; ++irq ) @@ -972,7 +972,7 @@ uint8_t alloc_hipriority_vector(void) return next++; } -static void (*direct_apic_vector[X86_NR_VECTORS])(void); +static void (*direct_apic_vector[X86_IDT_VECTORS])(void); void set_direct_apic_vector(uint8_t vector, void (*handler)(void)) { BUG_ON(direct_apic_vector[vector] != NULL); @@ -2572,7 +2572,7 @@ static void cf_check dump_irqs(unsigned char key) process_pending_softirqs(); printk("Direct vector information:\n"); - for ( i = FIRST_DYNAMIC_VECTOR; i < X86_NR_VECTORS; ++i ) + for ( i = FIRST_DYNAMIC_VECTOR; i < X86_IDT_VECTORS; ++i ) if ( direct_apic_vector[i] ) printk(" %#02x -> %ps()\n", i, direct_apic_vector[i]); diff --git a/xen/arch/x86/pv/callback.c b/xen/arch/x86/pv/callback.c index caec4fb16fab..38b819b56626 100644 --- a/xen/arch/x86/pv/callback.c +++ b/xen/arch/x86/pv/callback.c @@ -347,7 +347,7 @@ long do_set_trap_table(XEN_GUEST_HANDLE_PARAM(const_trap_info_t) traps) /* If no table is presented then clear the entire virtual IDT. */ if ( guest_handle_is_null(traps) ) { - memset(dst, 0, X86_NR_VECTORS * sizeof(*dst)); + memset(dst, 0, X86_IDT_VECTORS * sizeof(*dst)); return 0; } @@ -393,7 +393,7 @@ int compat_set_trap_table(XEN_GUEST_HANDLE(trap_info_compat_t) traps) /* If no table is presented then clear the entire virtual IDT. */ if ( guest_handle_is_null(traps) ) { - memset(dst, 0, X86_NR_VECTORS * sizeof(*dst)); + memset(dst, 0, X86_IDT_VECTORS * sizeof(*dst)); return 0; } diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index 7aef628f55be..9334da1dab93 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -312,9 +312,9 @@ int pv_vcpu_initialise(struct vcpu *v) if ( rc ) return rc; - BUILD_BUG_ON(X86_NR_VECTORS * sizeof(*v->arch.pv.trap_ctxt) > + BUILD_BUG_ON(X86_IDT_VECTORS * sizeof(*v->arch.pv.trap_ctxt) > PAGE_SIZE); - v->arch.pv.trap_ctxt = xzalloc_array(struct trap_info, X86_NR_VECTORS); + v->arch.pv.trap_ctxt = xzalloc_array(struct trap_info, X86_IDT_VECTORS); if ( !v->arch.pv.trap_ctxt ) { rc = -ENOMEM; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 1a53bb4aa481..a8a4fdaeb59c 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2196,7 +2196,7 @@ static void __init init_ler(void) setup_force_cpu_cap(X86_FEATURE_XEN_LBR); } -extern void (*const autogen_entrypoints[X86_NR_VECTORS])(void); +extern void (*const autogen_entrypoints[X86_IDT_VECTORS])(void); void __init trap_init(void) { unsigned int vector; @@ -2206,7 +2206,7 @@ void __init trap_init(void) pv_trap_init(); - for ( vector = 0; vector < X86_NR_VECTORS; ++vector ) + for ( vector = 0; vector < X86_IDT_VECTORS; ++vector ) { if ( autogen_entrypoints[vector] ) { diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S index 40d094d5b2ee..d866e626257b 100644 --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -1243,7 +1243,7 @@ DATA(autogen_entrypoints, 8) FUNC_LOCAL(autogen_stubs, 0) /* Automatically generated stubs. */ vec = 0 - .rept X86_NR_VECTORS + .rept X86_IDT_VECTORS /* Common interrupts, heading towards do_IRQ(). */ #if defined(CONFIG_PV32) From patchwork Mon Feb 24 16:05:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13988435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBD50C021BB for ; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b02d6837sm109356675e9.13.2025.02.24.08.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 08:07:14 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6a74cff7-f2c9-11ef-9aae-95dc52dad729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1740413235; x=1741018035; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mFJsQ/EffrIUlzYFRF2KwYzGjP98dz2R+aov7nCV9uM=; b=ZAtgZNzxQkzSGNdQxm3L8xZ5Xiq5xTynAKoyMOHvIBlBpThsf8zUjwc5wj8xKjuxi7 RCsRUAw+PlennP7M5Fxv0pLsws0bqvnsfoHcLdKwkq7VGpq65hQ4PExQAsy6nkVQam76 zBg6ujf7vaWS4e0skHRf/RExk3eYBie7lzLDg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740413235; x=1741018035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mFJsQ/EffrIUlzYFRF2KwYzGjP98dz2R+aov7nCV9uM=; b=WY8HeJBY9sn/2Xb57KNqV+7l3iLKoj1gpG8aQoW5mZYeuLMAZsp0UNOVUqBAQ1D3zm wqgNzD/hSBlyAnZPGRg59QDLY08Abm4AIXvnDYpLChfgRiKQ00atZ78A1Z2reobl1KdA gjxmqynESKxNMERlgoZX9oI9C3xYf0kLiWS1682PVLdMISRwv9PyYLwyW8nWBELv9cOe bCufVBC0l0+LNSO/Lf+oLMRznQ3pO1dEtq607/k30tA3kMcrS567Zys5xFbXebuPzBZP 1SLqZHgRWH81+XjkPaOGt82ZaXzepH+ks2NGNcsjjXzByy0L1M6cXYRPU5PByyldplGE SmYg== X-Gm-Message-State: AOJu0YyzdxqwzYn1lvC6jy22mBNNWghZdTxUXIEcrZhfEGytSwMhuFIz bdCmt1H2Nkog8LTNWcSG+L10eFloqZEiV65pnOLPME4UN+1DNA70ceiZ17S7Vs/W7GMx7JsGsiB e X-Gm-Gg: ASbGncsATn8N+D0Q6+Y9ciBinQbQyCY531v7bkKxTgCESFQufX7LqqrLeJi/jxVF4+m zThAV6YwFRaw6UisGtm6d5RsdhpxzwT/6GPMfBtqxJfkV589ShHx078THeiVVWjAK6qroSZ7Ps4 aWUea2+Y4yGxxadMqrSldsQps8ICyp14Dgsxp5VgPlee/lK+x0HZcn41WD3xzrIDP40anhxGg3W BLb4SD4qL+yiFB1xPHkf7ynyFFXwU9Nm6ONEB9CJEsZCP3iYtbd9ooUExPfchOpDNn2cxfOYp+C qMOZsNeuJa0wxBPhelF7fue5hdHYTc067fefohI4NIlryJFjmhKS29i20nMRq5DuTpFpAYSpP/M UHIMQBw== X-Google-Smtp-Source: AGHT+IE79iRkP1Na06GcO9H0r52YMm4ebPcOdyybCXvdOn4EIo5vYoznFQISQZZO1mtfuO3r+rB14w== X-Received: by 2002:a05:600c:3150:b0:439:955d:7adb with SMTP id 5b1f17b1804b1-439ae222a7amr143397645e9.30.1740413235159; Mon, 24 Feb 2025 08:07:15 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 4/8] x86/IDT: Rename idt_table[] to bsp_idt[] Date: Mon, 24 Feb 2025 16:05:05 +0000 Message-Id: <20250224160509.1117847-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250224160509.1117847-1-andrew.cooper3@citrix.com> References: <20250224160509.1117847-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Having variables named idt_table[] and idt_tables[] is not ideal. Use X86_IDT_VECTORS and remove IDT_ENTRIES. State the size of bsp_idt[] in idt.h so that load_system_tables() and cpu_smpboot_alloc() can use sizeof() rather than opencoding the calculation. Move the variable into a new traps-init.c, to make a start at splitting traps.c in half. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/Makefile | 1 + xen/arch/x86/cpu/common.c | 2 +- xen/arch/x86/include/asm/idt.h | 3 +-- xen/arch/x86/pv/traps.c | 4 ++-- xen/arch/x86/smpboot.c | 2 +- xen/arch/x86/traps-init.c | 9 +++++++++ xen/arch/x86/traps.c | 14 +++++--------- 7 files changed, 20 insertions(+), 15 deletions(-) create mode 100644 xen/arch/x86/traps-init.c diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile index b35fd5196ce2..9dc941a0943e 100644 --- a/xen/arch/x86/Makefile +++ b/xen/arch/x86/Makefile @@ -65,6 +65,7 @@ obj-y += spec_ctrl.o obj-y += srat.o obj-y += string.o obj-y += time.o +obj-y += traps-init.o obj-y += traps.o obj-$(CONFIG_INTEL) += tsx.o obj-y += usercopy.o diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 1540ab0007a0..e8b355ebcf36 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -831,7 +831,7 @@ void load_system_tables(void) }; const struct desc_ptr idtr = { .base = (unsigned long)idt_tables[cpu], - .limit = (IDT_ENTRIES * sizeof(idt_entry_t)) - 1, + .limit = sizeof(bsp_idt) - 1, }; /* diff --git a/xen/arch/x86/include/asm/idt.h b/xen/arch/x86/include/asm/idt.h index 4ef52050a11b..29d1a7dfbc63 100644 --- a/xen/arch/x86/include/asm/idt.h +++ b/xen/arch/x86/include/asm/idt.h @@ -29,8 +29,7 @@ typedef union { }; } idt_entry_t; -#define IDT_ENTRIES 256 -extern idt_entry_t idt_table[]; +extern idt_entry_t bsp_idt[X86_IDT_VECTORS]; extern idt_entry_t *idt_tables[]; /* diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 77b034e4dc73..4aeb6cab5238 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -148,12 +148,12 @@ void __init pv_trap_init(void) { #ifdef CONFIG_PV32 /* The 32-on-64 hypercall vector is only accessible from ring 1. */ - _set_gate(idt_table + HYPERCALL_VECTOR, + _set_gate(bsp_idt + HYPERCALL_VECTOR, SYS_DESC_irq_gate, 1, entry_int82); #endif /* Fast trap for int80 (faster than taking the #GP-fixup path). */ - _set_gate(idt_table + LEGACY_SYSCALL_VECTOR, SYS_DESC_irq_gate, 3, + _set_gate(bsp_idt + LEGACY_SYSCALL_VECTOR, SYS_DESC_irq_gate, 3, &entry_int80); open_softirq(NMI_SOFTIRQ, nmi_softirq); diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index f3d60d5bae35..dc65f9e45269 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -1080,7 +1080,7 @@ static int cpu_smpboot_alloc(unsigned int cpu) idt_tables[cpu] = alloc_xenheap_pages(0, memflags); if ( idt_tables[cpu] == NULL ) goto out; - memcpy(idt_tables[cpu], idt_table, IDT_ENTRIES * sizeof(idt_entry_t)); + memcpy(idt_tables[cpu], bsp_idt, sizeof(bsp_idt)); disable_each_ist(idt_tables[cpu]); for ( stub_page = 0, i = cpu & ~(STUBS_PER_PAGE - 1); diff --git a/xen/arch/x86/traps-init.c b/xen/arch/x86/traps-init.c new file mode 100644 index 000000000000..b172ea933607 --- /dev/null +++ b/xen/arch/x86/traps-init.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Configuration of event handling for all CPUs. + */ +#include +#include + +idt_entry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) + bsp_idt[X86_IDT_VECTORS]; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index a8a4fdaeb59c..f7965b3ffa50 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -102,10 +102,6 @@ DEFINE_PER_CPU_READ_MOSTLY(seg_desc_t *, compat_gdt); DEFINE_PER_CPU_READ_MOSTLY(l1_pgentry_t, compat_gdt_l1e); #endif -/* Master table, used by CPU0. */ -idt_entry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) - idt_table[IDT_ENTRIES]; - /* Pointer to the IDT of every CPU. */ idt_entry_t *idt_tables[NR_CPUS] __read_mostly; @@ -2084,7 +2080,7 @@ void asmlinkage do_entry_CP(struct cpu_user_regs *regs) static void __init noinline __set_intr_gate(unsigned int n, uint32_t dpl, void *addr) { - _set_gate(&idt_table[n], SYS_DESC_irq_gate, dpl, addr); + _set_gate(&bsp_idt[n], SYS_DESC_irq_gate, dpl, addr); } static void __init set_swint_gate(unsigned int n, void *addr) @@ -2150,10 +2146,10 @@ void __init init_idt_traps(void) set_intr_gate (X86_EXC_CP, entry_CP); /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */ - enable_each_ist(idt_table); + enable_each_ist(bsp_idt); /* CPU0 uses the master IDT. */ - idt_tables[0] = idt_table; + idt_tables[0] = bsp_idt; this_cpu(gdt) = boot_gdt; if ( IS_ENABLED(CONFIG_PV32) ) @@ -2211,13 +2207,13 @@ void __init trap_init(void) if ( autogen_entrypoints[vector] ) { /* Found autogen entry: check we won't clobber an existing trap. */ - ASSERT(idt_table[vector].b == 0); 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b02d6837sm109356675e9.13.2025.02.24.08.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 08:07:15 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6ae2e851-f2c9-11ef-9897-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1740413236; x=1741018036; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2a7RbY8QCk2TLWrBIf90b/zkqmEwNcD5m6KQuSVDFjw=; b=XWq1RrcLg1mXapKJ3HOY9ZtJaXZuRZweNc8OPZYEy2FFLrdc/qv6IPOjoTFUHBtI5H lVt4n4+4jZcMMfr7GEAA3+pk/idpcqcyQmImi6UiGw8MGRlitL1UFXJnBpXS0T/tXZ8g +a2XSkgHwNPl0kYI447M+2iGXN73j71KfbN8E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740413236; x=1741018036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2a7RbY8QCk2TLWrBIf90b/zkqmEwNcD5m6KQuSVDFjw=; b=w6D8cu8S7xBvgD2ZMaqFrhV/Ru4JTVpxpcvIq/0ILmYx6gJYpAfPN7/Itrf9cmE0pH 6B4IPxTJgkB1sR8a67yHiLLyz3fgSi1ki21h8aX0oFs47uEt0VJdDXnamDAg806HY/DC zLK0J3gSz8PlsKIx+MK1N7gs7JhPwpLrGDtvirHi4wgVlmfatO6UpjOg9u/0CefwCcsK SN4M5lUmNpWhWNnm17v5rp9qrsqaW3X/FXhuiQzRQ1xBvG6r5MPNIBqyOIPPRPcRqr8L pf553zsCFV7a8WRRAYeTHSjkXe9ks1x7SWlCcrxpV6SQI7NREjHNgDZ/J/ciBMnA1W7y fraQ== X-Gm-Message-State: AOJu0YzXJn+XPDJLDiPS245z6XONm2pP4FF+3CEPngiyAf4SX9Rh1ZMb 1sx4HlWRhYgyDnWnNqCo0FSGaYqKFVeVIY/NGq6UgmoHHH6cPkT6CqCC1eLT/Rw6c8H+IBrr48q j X-Gm-Gg: ASbGncvZ/fsj0m3xBLbJVDYu0nf7zVSjaBGpnCCAmsEkD2aXWwD1eRoBatp/OxPvICA sZP6oenBA5BRYgcYp/Q11XiVfTEyIq1gkUTtM4bL1uTD5qIzcvi2bEYmRGMM9FFuTGfjzx0QXPK G5g4ygk33qzOpGL6xoL0kesThfSCwEUcM0szWOg96O65DxS4IxCO+F8xjzyCdUToBvYXbs3Ifon T9Cy2/QVSssfd8v5Hk/+0eNEfJs3Kw8+WVM3WWsfdQKR4x5tqj/RXe9q4pM03u/PZ8GiY6RyL0/ /9GU9cMgvJHP0fplyt/mh9ppvU9EpoZlCrYq9NM9ozov+iYVVt41Rwx81mJVHM4J7AkdDNpmxra faGrqRg== X-Google-Smtp-Source: AGHT+IEsnlgH0FFKo3AtBbyCmD1GiyDttxMH48OUHaofyJ8Q5l0+Fpaqz7EH7SSw8KYzD1j2UHH7Pw== X-Received: by 2002:a05:600c:4451:b0:439:8bb1:14b1 with SMTP id 5b1f17b1804b1-439ae1e8c88mr126527155e9.11.1740413235852; Mon, 24 Feb 2025 08:07:15 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 5/8] x86/IDT: Make idt_tables[] be per_cpu(idt) Date: Mon, 24 Feb 2025 16:05:06 +0000 Message-Id: <20250224160509.1117847-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250224160509.1117847-1-andrew.cooper3@citrix.com> References: <20250224160509.1117847-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 This can be a plain per_cpu() variable, and __read_mostly seeing as it's allocated once and never touched again. This removes a NR_CPU's sized structure, and improves NUMA locality of access for both the the VT-x and SVM context switch paths. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/cpu/common.c | 5 +++-- xen/arch/x86/crash.c | 8 ++++---- xen/arch/x86/domain.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 4 ++-- xen/arch/x86/hvm/vmx/vmcs.c | 2 +- xen/arch/x86/include/asm/idt.h | 3 ++- xen/arch/x86/machine_kexec.c | 7 +++++-- xen/arch/x86/smpboot.c | 14 +++++++------- xen/arch/x86/traps-init.c | 2 ++ xen/arch/x86/traps.c | 5 +---- 10 files changed, 28 insertions(+), 24 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index e8b355ebcf36..b83dbc5dfbba 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -819,6 +819,7 @@ void load_system_tables(void) * support using ARRAY_SIZE against per-cpu variables. */ struct tss_page *tss_page = &this_cpu(tss_page); + idt_entry_t *idt = this_cpu(idt); /* The TSS may be live. Disuade any clever optimisations. */ volatile struct tss64 *tss = &tss_page->tss; @@ -830,7 +831,7 @@ void load_system_tables(void) .limit = LAST_RESERVED_GDT_BYTE, }; const struct desc_ptr idtr = { - .base = (unsigned long)idt_tables[cpu], + .base = (unsigned long)idt, .limit = sizeof(bsp_idt) - 1, }; @@ -914,7 +915,7 @@ void load_system_tables(void) ltr(TSS_SELECTOR); lldt(0); - enable_each_ist(idt_tables[cpu]); + enable_each_ist(idt); /* * Bottom-of-stack must be 16-byte aligned! diff --git a/xen/arch/x86/crash.c b/xen/arch/x86/crash.c index 5f7d7b392a1f..1e4b0eeff21b 100644 --- a/xen/arch/x86/crash.c +++ b/xen/arch/x86/crash.c @@ -63,7 +63,7 @@ static int noreturn cf_check do_nmi_crash( * This update is safe from a security point of view, as this * pcpu is never going to try to sysret back to a PV vcpu. */ - set_ist(&idt_tables[cpu][X86_EXC_MC], IST_NONE); + set_ist(&per_cpu(idt, cpu)[X86_EXC_MC], IST_NONE); kexec_crash_save_cpu(); __stop_this_cpu(); @@ -120,6 +120,7 @@ static void nmi_shootdown_cpus(void) { unsigned long msecs; unsigned int cpu = smp_processor_id(); + idt_entry_t *idt = this_cpu(idt); disable_lapic_nmi_watchdog(); local_irq_disable(); @@ -133,9 +134,8 @@ static void nmi_shootdown_cpus(void) * Disable IST for MCEs to avoid stack corruption race conditions, and * change the NMI handler to a nop to avoid deviation from this codepath. */ - _set_gate_lower(&idt_tables[cpu][X86_EXC_NMI], - SYS_DESC_irq_gate, 0, &trap_nop); - set_ist(&idt_tables[cpu][X86_EXC_MC], IST_NONE); + _set_gate_lower(&idt[X86_EXC_NMI], SYS_DESC_irq_gate, 0, &trap_nop); + set_ist(&idt[X86_EXC_MC], IST_NONE); set_nmi_callback(do_nmi_crash); smp_send_nmi_allbutself(); diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index d3db76833f3c..a42fa5480593 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -116,7 +116,7 @@ void play_dead(void) local_irq_disable(); /* Change the NMI handler to a nop (see comment below). */ - _set_gate_lower(&idt_tables[cpu][X86_EXC_NMI], SYS_DESC_irq_gate, 0, + _set_gate_lower(&this_cpu(idt)[X86_EXC_NMI], SYS_DESC_irq_gate, 0, &trap_nop); /* diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index ea78da4f4210..4eac89964f61 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -915,7 +915,7 @@ static void cf_check svm_ctxt_switch_from(struct vcpu *v) svm_vmload_pa(per_cpu(host_vmcb, cpu)); /* Resume use of ISTs now that the host TR is reinstated. */ - enable_each_ist(idt_tables[cpu]); + enable_each_ist(per_cpu(idt, cpu)); /* * Possibly clear previous guest selection of SSBD if set. Note that @@ -944,7 +944,7 @@ static void cf_check svm_ctxt_switch_to(struct vcpu *v) * Cannot use ISTs for NMI/#MC/#DF while we are running with the guest TR. * But this doesn't matter: the IST is only req'd to handle SYSCALL/SYSRET. */ - disable_each_ist(idt_tables[cpu]); + disable_each_ist(per_cpu(idt, cpu)); svm_restore_dr(v); diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 20ab2d0f266f..e47a6e1542b7 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -917,7 +917,7 @@ static void vmx_set_host_env(struct vcpu *v) __vmwrite(HOST_GDTR_BASE, (unsigned long)(this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY)); - __vmwrite(HOST_IDTR_BASE, (unsigned long)idt_tables[cpu]); + __vmwrite(HOST_IDTR_BASE, (unsigned long)per_cpu(idt, cpu)); __vmwrite(HOST_TR_BASE, (unsigned long)&per_cpu(tss_page, cpu).tss); diff --git a/xen/arch/x86/include/asm/idt.h b/xen/arch/x86/include/asm/idt.h index 29d1a7dfbc63..3e3acdfa7930 100644 --- a/xen/arch/x86/include/asm/idt.h +++ b/xen/arch/x86/include/asm/idt.h @@ -3,6 +3,7 @@ #define X86_ASM_IDT_H #include +#include #include #include @@ -30,7 +31,7 @@ typedef union { } idt_entry_t; extern idt_entry_t bsp_idt[X86_IDT_VECTORS]; -extern idt_entry_t *idt_tables[]; +DECLARE_PER_CPU(idt_entry_t *, idt); /* * Set the Interrupt Stack Table used by a particular IDT entry. Typically diff --git a/xen/arch/x86/machine_kexec.c b/xen/arch/x86/machine_kexec.c index f775e526d59b..35fa5c82e9c2 100644 --- a/xen/arch/x86/machine_kexec.c +++ b/xen/arch/x86/machine_kexec.c @@ -170,9 +170,12 @@ void machine_kexec(struct kexec_image *image) */ for ( i = 0; i < nr_cpu_ids; i++ ) { - if ( idt_tables[i] == NULL ) + idt_entry_t *idt = per_cpu(idt, i); + + if ( !idt ) continue; - _update_gate_addr_lower(&idt_tables[i][X86_EXC_MC], &trap_nop); + + _update_gate_addr_lower(&idt[X86_EXC_MC], &trap_nop); } /* Reset CPUID masking and faulting to the host's default. */ diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index dc65f9e45269..4e9f9ac4b2ee 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -863,7 +863,7 @@ int setup_cpu_root_pgt(unsigned int cpu) rc = clone_mapping(__va(__pa(stack_base[cpu])) + off, rpt); if ( !rc ) - rc = clone_mapping(idt_tables[cpu], rpt); + rc = clone_mapping(per_cpu(idt, cpu), rpt); if ( !rc ) { struct tss_page *ptr = &per_cpu(tss_page, cpu); @@ -1009,7 +1009,7 @@ static void cpu_smpboot_free(unsigned int cpu, bool remove) if ( remove ) { FREE_XENHEAP_PAGE(per_cpu(gdt, cpu)); - FREE_XENHEAP_PAGE(idt_tables[cpu]); + FREE_XENHEAP_PAGE(per_cpu(idt, cpu)); if ( stack_base[cpu] ) { @@ -1076,12 +1076,12 @@ static int cpu_smpboot_alloc(unsigned int cpu) gdt[PER_CPU_GDT_ENTRY - FIRST_RESERVED_GDT_ENTRY].a = cpu; #endif - if ( idt_tables[cpu] == NULL ) - idt_tables[cpu] = alloc_xenheap_pages(0, memflags); - if ( idt_tables[cpu] == NULL ) + if ( per_cpu(idt, cpu) == NULL ) + per_cpu(idt, cpu) = alloc_xenheap_pages(0, memflags); + if ( per_cpu(idt, cpu) == NULL ) goto out; - memcpy(idt_tables[cpu], bsp_idt, sizeof(bsp_idt)); - disable_each_ist(idt_tables[cpu]); + memcpy(per_cpu(idt, cpu), bsp_idt, sizeof(bsp_idt)); + disable_each_ist(per_cpu(idt, cpu)); for ( stub_page = 0, i = cpu & ~(STUBS_PER_PAGE - 1); i < nr_cpu_ids && i <= (cpu | (STUBS_PER_PAGE - 1)); ++i ) diff --git a/xen/arch/x86/traps-init.c b/xen/arch/x86/traps-init.c index b172ea933607..ae600526cbe3 100644 --- a/xen/arch/x86/traps-init.c +++ b/xen/arch/x86/traps-init.c @@ -7,3 +7,5 @@ idt_entry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) bsp_idt[X86_IDT_VECTORS]; + +DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt); diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index f7965b3ffa50..aa3ed658def6 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -102,9 +102,6 @@ DEFINE_PER_CPU_READ_MOSTLY(seg_desc_t *, compat_gdt); DEFINE_PER_CPU_READ_MOSTLY(l1_pgentry_t, compat_gdt_l1e); #endif -/* Pointer to the IDT of every CPU. */ -idt_entry_t *idt_tables[NR_CPUS] __read_mostly; - /* * The TSS is smaller than a page, but we give it a full page to avoid * adjacent per-cpu data leaking via Meltdown when XPTI is in use. @@ -2149,7 +2146,7 @@ void __init init_idt_traps(void) enable_each_ist(bsp_idt); /* CPU0 uses the master IDT. */ - idt_tables[0] = bsp_idt; + this_cpu(idt) = bsp_idt; this_cpu(gdt) = boot_gdt; if ( IS_ENABLED(CONFIG_PV32) ) From patchwork Mon Feb 24 16:05:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13988432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E41F3C021BB for ; Mon, 24 Feb 2025 16:07:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.895268.1303898 (Exim 4.92) (envelope-from ) id 1tmazH-0004n7-B5; Mon, 24 Feb 2025 16:07:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 895268.1303898; Mon, 24 Feb 2025 16:07:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tmazH-0004lv-3M; Mon, 24 Feb 2025 16:07:19 +0000 Received: by outflank-mailman (input) for mailman id 895268; Mon, 24 Feb 2025 16:07:18 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tmazG-0003oc-Du for xen-devel@lists.xenproject.org; Mon, 24 Feb 2025 16:07:18 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 6b4fe0ec-f2c9-11ef-9aae-95dc52dad729; Mon, 24 Feb 2025 17:07:17 +0100 (CET) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4398c8c8b2cso46054775e9.2 for ; Mon, 24 Feb 2025 08:07:17 -0800 (PST) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. [92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b02d6837sm109356675e9.13.2025.02.24.08.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 08:07:16 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6b4fe0ec-f2c9-11ef-9aae-95dc52dad729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1740413237; x=1741018037; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gqs2ri15sfzFaC7F9ABm85vSLlP8o53QJK1dsgxDFAI=; b=gergOBXQHovQx0o2LaaqfesNdxDE0HGZOtA5GMklDP0EPtoRV2QCVjisFkeD1q0df6 63WzjPNVXPY9Ry4r78cSTTxofOv7SpwE6TVTe1K3S4yxLnudrpkCHJeRbUaNJ09fC51K 8ViWvG5KCtoQoIZHPgCEeQFDSEmfgS2LhfeWI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740413237; x=1741018037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gqs2ri15sfzFaC7F9ABm85vSLlP8o53QJK1dsgxDFAI=; b=Kfds7yx5km7VrYlyVBCKxI5vduCimPdl4wrod8SMGf+vBr8L4ZpCDjUAsiJLdHFILj 6KnJ+Xe8e9rXOMVR7EftzDU/WXCLuyueg6Yrm5lo14O6MqukhBApZSWgBmvAMCvHP4WX 7yEkYrJtYmRuDoxYs9VKOhwu+4ttYAzGWJGnpw0bjhreaW202+TFiqtuYmAUYGVL07NQ JLCgwH+z7GnlP+o3mIKdBLbjPxwlXaU1fARuPunr2VYlP8q+vo9GixLqVEqxUatKoQ4e 8csFo5mDDyuJ4nbcEkI4PlBgZFOrp9loRs6j/8j0ChdmfUjwonzy6OUZ8tr5zHqZY4UN PnrQ== X-Gm-Message-State: AOJu0YzhUrX7WwTxY4VDGHkogE6MTO67SDXFYo11yHPgqxS3uwiFFoos Vu/7v4kQu7jlbN3Rs27YftYHj6dFTwACz63FXMK+F4EcNeO0U+bEUW9KYPxoiKX2eYmIChUNk1V Q X-Gm-Gg: ASbGnctbjLIbmcBM0+3VkyeRXkyYqVda1q+93IvrFfHWmE4Y2ImSx04AySjqrFd0ZBR 77GbAE9gXDn/bGvoE3V5S9WIUea++9oazX8e/2JazkzLo60dlLc0VaSpyt0P4sCVFPq6B1W1pPG 4mbYOI2JkM7ozCLju/zt20q1Jkw45J7LoiEdz9AR1xwtjDD8F12gH5f4DSMuMyYdbp9yh1KN1y8 QEDVXHbaSlFXNUvO+mL7JNvUGeuYl0qqv0kdCU5fOu5Bz8gF++EwvXWGMcbMtY8xhegpC8edUBg YXiQ8LY3F+93mO5xCfpBkP0JXx62ZOW+bcxROcVUVDDROw0THpZ1MDGnuw3BS+Bib6Np4D3j98c kCNSBrA== X-Google-Smtp-Source: AGHT+IFdO2/tob/YlbgVoGHNyRf3tjSWVYo8AEV1AL0jYNyLp9S0lOZXJOCZSWz3IOsultllNDjgIw== X-Received: by 2002:a05:600c:3c86:b0:439:9b80:ca6f with SMTP id 5b1f17b1804b1-439ae1d7272mr136814925e9.5.1740413236550; Mon, 24 Feb 2025 08:07:16 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 6/8] x86/IDT: Generate bsp_idt[] at build time Date: Mon, 24 Feb 2025 16:05:07 +0000 Message-Id: <20250224160509.1117847-7-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250224160509.1117847-1-andrew.cooper3@citrix.com> References: <20250224160509.1117847-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 ... rather than dynamically at boot time. Aside from less runtime overhead, this approach is less fragile than the preexisting autogen stubs mechanism. We can manage this with some linker calculations. See patch comments for full details. For simplicity, we create a new set of entry stubs here, and clean up the old ones in the subsequent patch. bsp_idt[] needs to move from .bss to .data. No functional change yet; the boot path still (re)writes bsp_idt[] at this juncture. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné There's something differnet about LLD vs LD. Without the ABSOLUTE() in gen-idt.lds.h, LD is fine but LLD puts out symbols in the form: x86_IDT_entry_0xff_ADDR1|0000000000002fb0| t | NOTYPE| | |.text x86_IDT_entry_0xff_ADDR2|0000000000004020| a | NOTYPE| | |*ABS* which causes a slew of errors making symbols for xen-syms: .xen-syms.0.S:20:8: error: out of range literal value .long 0x15a0 - (((((((261 >> 8) * 0xffff000000000000) | (261 << 39))) + ((1 << 39) / 2)) + (64 << 30)) + (1 << 30)) ^ owing to half the symbols being t rather than a. Moreover, this is reliable for the full FreeBSD builds, but interminttent on randconfig. I haven't figured out which other option is having an effect. Forcing them all to absolute works in both toolchains. --- xen/arch/x86/include/asm/gen-idt.h | 121 +++++++++++++++++++++++++ xen/arch/x86/include/asm/gen-idt.lds.h | 27 ++++++ xen/arch/x86/traps-init.c | 4 - xen/arch/x86/x86_64/entry.S | 76 ++++++++++++++++ xen/arch/x86/xen.lds.S | 2 + 5 files changed, 226 insertions(+), 4 deletions(-) create mode 100644 xen/arch/x86/include/asm/gen-idt.h create mode 100644 xen/arch/x86/include/asm/gen-idt.lds.h diff --git a/xen/arch/x86/include/asm/gen-idt.h b/xen/arch/x86/include/asm/gen-idt.h new file mode 100644 index 000000000000..a345af0ec774 --- /dev/null +++ b/xen/arch/x86/include/asm/gen-idt.h @@ -0,0 +1,121 @@ +/* + * Generator for IDT entries. + * + * Caller to provide GEN(vector, symbol, dpl, autogen) macro + * + * Symbols are 'entry_0xYY' if there is no better name available. Regular + * handlers set autogen=1, while manual (autogen=0) require the symbol to be + * implemented somewhere else. + */ + +#define DPL0 0 +#define DPL1 1 +#define DPL3 3 + +#define manual 0 +#define autogen 1 + +#define GEN16(i) \ + GEN(0x ## i ## 0, entry_0x ## i ## 0, DPL0, autogen) \ + GEN(0x ## i ## 1, entry_0x ## i ## 1, DPL0, autogen) \ + GEN(0x ## i ## 2, entry_0x ## i ## 2, DPL0, autogen) \ + GEN(0x ## i ## 3, entry_0x ## i ## 3, DPL0, autogen) \ + GEN(0x ## i ## 4, entry_0x ## i ## 4, DPL0, autogen) \ + GEN(0x ## i ## 5, entry_0x ## i ## 5, DPL0, autogen) \ + GEN(0x ## i ## 6, entry_0x ## i ## 6, DPL0, autogen) \ + GEN(0x ## i ## 7, entry_0x ## i ## 7, DPL0, autogen) \ + GEN(0x ## i ## 8, entry_0x ## i ## 8, DPL0, autogen) \ + GEN(0x ## i ## 9, entry_0x ## i ## 9, DPL0, autogen) \ + GEN(0x ## i ## a, entry_0x ## i ## a, DPL0, autogen) \ + GEN(0x ## i ## b, entry_0x ## i ## b, DPL0, autogen) \ + GEN(0x ## i ## c, entry_0x ## i ## c, DPL0, autogen) \ + GEN(0x ## i ## d, entry_0x ## i ## d, DPL0, autogen) \ + GEN(0x ## i ## e, entry_0x ## i ## e, DPL0, autogen) \ + GEN(0x ## i ## f, entry_0x ## i ## f, DPL0, autogen) + + +GEN(0x00, entry_DE, DPL0, manual) +GEN(0x01, entry_DB, DPL0, manual) +GEN(0x02, entry_NMI, DPL0, manual) +GEN(0x03, entry_BP, DPL3, manual) +GEN(0x04, entry_OF, DPL3, manual) +GEN(0x05, entry_BR, DPL0, manual) +GEN(0x06, entry_UD, DPL0, manual) +GEN(0x07, entry_NM, DPL0, manual) +GEN(0x08, entry_DF, DPL0, manual) +GEN(0x09, entry_0x09, DPL0, autogen) /* Coprocessor Segment Overrun */ +GEN(0x0a, entry_TS, DPL0, manual) +GEN(0x0b, entry_NP, DPL0, manual) +GEN(0x0c, entry_SS, DPL0, manual) +GEN(0x0d, entry_GP, DPL0, manual) +GEN(0x0e, early_page_fault, DPL0, manual) +GEN(0x0f, entry_0x0f, DPL0, autogen) /* PIC Spurious Interrupt Vector */ + +GEN(0x10, entry_MF, DPL0, manual) +GEN(0x11, entry_AC, DPL0, manual) +GEN(0x12, entry_MC, DPL0, manual) +GEN(0x13, entry_XM, DPL0, manual) +GEN(0x14, entry_VE, DPL0, autogen) +GEN(0x15, entry_CP, DPL0, manual) +GEN(0x16, entry_0x16, DPL0, autogen) +GEN(0x17, entry_0x17, DPL0, autogen) +GEN(0x18, entry_0x18, DPL0, autogen) +GEN(0x19, entry_0x19, DPL0, autogen) +GEN(0x1a, entry_0x1a, DPL0, autogen) +GEN(0x1b, entry_0x1b, DPL0, autogen) +GEN(0x1c, entry_HV, DPL0, autogen) +GEN(0x1d, entry_VC, DPL0, autogen) +GEN(0x1e, entry_SX, DPL0, autogen) +GEN(0x1f, entry_0x1f, DPL0, autogen) + +GEN16(2) +GEN16(3) +GEN16(4) +GEN16(5) +GEN16(6) +GEN16(7) + +#ifdef CONFIG_PV +GEN(0x80, entry_int80, DPL0, manual) +#else +GEN(0x80, entry_0x80, DPL0, autogen) +#endif + +GEN(0x81, entry_0x81, DPL0, autogen) + +#ifdef CONFIG_PV32 +GEN(0x82, entry_int82, DPL1, manual) +#else +GEN(0x82, entry_0x82, DPL0, autogen) +#endif + +GEN(0x83, entry_0x83, DPL0, autogen) +GEN(0x84, entry_0x84, DPL0, autogen) +GEN(0x85, entry_0x85, DPL0, autogen) +GEN(0x86, entry_0x86, DPL0, autogen) +GEN(0x87, entry_0x87, DPL0, autogen) +GEN(0x88, entry_0x88, DPL0, autogen) +GEN(0x89, entry_0x89, DPL0, autogen) +GEN(0x8a, entry_0x8a, DPL0, autogen) +GEN(0x8b, entry_0x8b, DPL0, autogen) +GEN(0x8c, entry_0x8c, DPL0, autogen) +GEN(0x8d, entry_0x8d, DPL0, autogen) +GEN(0x8e, entry_0x8e, DPL0, autogen) +GEN(0x8f, entry_0x8f, DPL0, autogen) + +GEN16(9) +GEN16(a) +GEN16(b) +GEN16(c) +GEN16(d) +GEN16(e) +GEN16(f) + +#undef autogen +#undef manual + +#undef DPL3 +#undef DPL1 +#undef DPL0 + +#undef GEN16 diff --git a/xen/arch/x86/include/asm/gen-idt.lds.h b/xen/arch/x86/include/asm/gen-idt.lds.h new file mode 100644 index 000000000000..997cec0c4de1 --- /dev/null +++ b/xen/arch/x86/include/asm/gen-idt.lds.h @@ -0,0 +1,27 @@ +/* + * Linker file fragment to help format the IDT correctly + * + * The IDT, having grown compatibly since the 16 bit days, has the entrypoint + * address field split into 3. x86 ELF lacks the @lo/@hi/etc relocation forms + * commonly found in other architectures for accessing a part of a resolved + * symbol address. + * + * However, the linker can perform the necessary calculations and provide them + * under new symbol names. We use this to generate the low and next 16 bits + * of the address for each handler. + * + * The upper 32 bits are always a constant as Xen's .text/data/rodata sits in + * a single aligned 1G range, so do not need calculating in this manner. + */ +#ifndef X86_IDT_GEN_LDS_H +#define X86_IDT_GEN_LDS_H + +#define GEN(vec, sym, dpl, auto) \ + PROVIDE_HIDDEN(IDT_ ## sym ## _ADDR1 = ABSOLUTE(((sym) & 0xffff))); \ + PROVIDE_HIDDEN(IDT_ ## sym ## _ADDR2 = ABSOLUTE(((sym >> 16) & 0xffff))); + +#include + +#undef GEN + +#endif /* X86_IDT_GEN_LDS_H */ diff --git a/xen/arch/x86/traps-init.c b/xen/arch/x86/traps-init.c index ae600526cbe3..3ee28319584d 100644 --- a/xen/arch/x86/traps-init.c +++ b/xen/arch/x86/traps-init.c @@ -3,9 +3,5 @@ * Configuration of event handling for all CPUs. */ #include -#include - -idt_entry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) - bsp_idt[X86_IDT_VECTORS]; DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt); diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S index d866e626257b..313711a01184 100644 --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -1229,6 +1229,82 @@ FUNC(trap_nop, 0) iretq END(trap_nop) +/* + * Automatically generated entrypoints, and IDT + */ + + .pushsection .data.page_aligned, "aw", @progbits +DATA(bsp_idt, PAGE_SIZE) + .popsection + +/* + * Write an IDT Entry. The linker provides us new _ADDR1/2 symbols calculated + * from \sym. + */ +.macro write_idte sym, dpl + .pushsection .data.page_aligned, "aw", @progbits + .word IDT_\sym\()_ADDR1 + .word __HYPERVISOR_CS + .word 0x8e00 | (\dpl << 13) /* Present, DPL, Interrupt Gate */ + .word IDT_\sym\()_ADDR2 + .long __XEN_VIRT_START >> 32 + .long 0 + .popsection +.endm + +/* + * Write an automatically generated stub. Vectors in the exception range keep + * the stack properly aligned by judging whether the CPU pushed an error code + * or not. + * + * Alignment is forced to 16 because that's the size of the interrupt stub + * with CET active. + */ +.macro gen_entry vec, sym + +FUNC(\sym, 16) + ENDBR64 + + .if \vec < 0x20 /* Exception. */ + + test $8, %spl /* 64bit exception frames are 16 byte aligned, but the word */ + jz 1f /* size is 8 bytes. Check whether the processor gave us an */ + pushq $0 /* error code, and insert an empty one if not. */ +1: movb $\vec, EFRAME_entry_vector(%rsp) + jmp handle_exception + + .else /* Interrupt. */ + + pushq $0 + movb $\vec, EFRAME_entry_vector(%rsp) + jmp common_interrupt + + .endif +END(\sym) +.endm + +/* + * Generator. Write an entrypoint if necessary, and record an IDT entry. + */ +.macro gen vec, sym, dpl, auto + + .if \auto + gen_entry \vec, \sym + .endif + + write_idte \sym, \dpl +.endm +#define GEN(v, s, d, a) gen vec=v, sym=s, dpl=d auto=a; +#include +#undef GEN + + .pushsection .data.page_aligned, "aw", @progbits +END(bsp_idt) + .if . - bsp_idt != PAGE_SIZE + .error "Bad bsp_idt size, should be PAGE_SIZE" + .endif + .popsection + /* Table of automatically generated entry points. One per vector. */ .pushsection .init.rodata, "a", @progbits DATA(autogen_entrypoints, 8) diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S index 42217eaf2485..d4dd6434c466 100644 --- a/xen/arch/x86/xen.lds.S +++ b/xen/arch/x86/xen.lds.S @@ -8,6 +8,8 @@ # define DECL_SECTION_WITH_LADDR #endif #include + +#include #include #include From patchwork Mon Feb 24 16:05:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13988440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80B8FC021BB for ; Mon, 24 Feb 2025 16:08:11 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.895270.1303924 (Exim 4.92) (envelope-from ) id 1tmazK-0005XW-6A; Mon, 24 Feb 2025 16:07:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 895270.1303924; Mon, 24 Feb 2025 16:07:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tmazK-0005WF-1i; Mon, 24 Feb 2025 16:07:22 +0000 Received: by outflank-mailman (input) for mailman id 895270; Mon, 24 Feb 2025 16:07:19 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tmazH-0004jn-RW for xen-devel@lists.xenproject.org; Mon, 24 Feb 2025 16:07:19 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 6bad58e9-f2c9-11ef-9897-31a8f345e629; Mon, 24 Feb 2025 17:07:18 +0100 (CET) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-439350f1a0bso27387295e9.0 for ; Mon, 24 Feb 2025 08:07:18 -0800 (PST) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. [92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b02d6837sm109356675e9.13.2025.02.24.08.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 08:07:16 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6bad58e9-f2c9-11ef-9897-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1740413237; x=1741018037; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xoVYQcMEL32R74WeX/YmAkzuEJp1kM7LECNyrYOhOmA=; b=P65GMOqud4XVlvW7vzUB93DBsh/GtIYER40p5uSZHQndEsIdKOAsWSEdpqOK9hD6Bc 3CzPI4vV+5gG0fvEKLPFNI69I3SORQ5X4f2aWwiVy4GFV9sLSKA05sb0Qy8YNtR2D63q SLJDItu6HqRa3Bnr5pkHCcIqCNvePhpV//GO4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740413237; x=1741018037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xoVYQcMEL32R74WeX/YmAkzuEJp1kM7LECNyrYOhOmA=; b=cR2YP1y11l53zXtEGRjvXsH1HJFEDhw2Hzvq3QE5DW3HoJK6hh5Kb+HiqPi/+wEGh4 ApkSa0t3HQZ0n1AQjjNZfWoVcMf9iCDtfdAXeZQzkx9UPGXnOZ07JYp6dYw38dbCbQ0b JTKlg+FISREai1+ZgSU9HjtgBDZp61x1T9O3DMcDBOInrVjYHyc8qiwLndX7c0N5nKYQ HI5PRVZ+fn/ubr85aiACyVpneWYczOY6xv/KRXuiKirU5FtgYqc2NXevfpXVsTlh452Q BUioqd7NevUHeYUpYF0650QwwcGwQSoI3QzeBaFdJCk2KOH/CfjJ3pKEhFhbDBOjWra+ J3nw== X-Gm-Message-State: AOJu0Yw99bKyMZi/pwjaPrTBTY5VuGqszGnYIt5rDdpHnNKI52kzUWqs m5q4e+dB3NtCsqNAVPAcSukcYP/noSePSFnsd+BfnrDcGGnOZO6gGoQ063y/eNAvED1jrn4bFjT z X-Gm-Gg: ASbGnctvnXPBd/zIEbhbn1fZZZthN2GF1XD1k/3/AuXauW0h0Y6hh2JgeHDxmFtFSzb A1A3T4fb1kI8O/ePI6XmP9QlQ+QoeCcRA2+IffZ5SmayWKYxdomjT1zh6AYXscdlhxi0gtIqpl4 r1vexOAHp8sjBL4IMW21jP7gA6Fp/u5+/YV/G49PZUsiZq5j2C/ERx3RqCr5O69bHrb1iPfo4Db G5azVJOtqorlqYWOBxOmHlqls4oSxR6s16pQX+lBbNkdUFEw+m3t1kmrqRVq5/0WHmNSlaz5P1W VxCzOwgvtluCtHqbCrGTiPWQMdfYLi71jCe4RVhyDORjU2BY2y7IchN8+SIzTgDdK/xQy3c2gko bFpDW+Q== X-Google-Smtp-Source: AGHT+IF3mnszYSSw34gWV6vXFtpybB5EnRW4fd65y2VauAYzmaftts5GU0rQtfnW+Z8TkCF3/CAifw== X-Received: by 2002:a05:600c:4784:b0:439:8605:6d7c with SMTP id 5b1f17b1804b1-439a2864c3cmr139921985e9.0.1740413237219; Mon, 24 Feb 2025 08:07:17 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 7/8] x86/IDT: Don't rewrite bsp_idt[] at boot time Date: Mon, 24 Feb 2025 16:05:08 +0000 Message-Id: <20250224160509.1117847-8-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250224160509.1117847-1-andrew.cooper3@citrix.com> References: <20250224160509.1117847-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Now that bsp_idt[] is constructed at build time, we do not need to manually initialise it in init_idt_traps() and trap_init(). The only edit needed to the bsp_idt[] is to switch from the early #PF handler to the normal one, and this can be done using _update_gate_addr_lower() as we do on the kexec path for NMI and #MC. This in turn allows us to drop set_{intr,swint}_gate() and the underlying infrastructure. It also lets us drop autogen_entrypoints[] and that underlying infrastructure. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné Bloat-o-meter reports: add/remove: 0/3 grow/shrink: 1/2 up/down: 9/-6482 (-6473) Function old new delta trap_init 425 434 +9 __set_intr_gate 84 - -84 pv_trap_init 163 17 -146 init_idt_traps 469 105 -364 autogen_entrypoints 2048 - -2048 autogen_stubs 3840 - -3840 The 3840 for autogen_stubs isn't really a saving here; it was introduced under different names in the prior patch. We do safe 2k on autogen_entrypoints by having the linker complete the work at build time. --- xen/arch/x86/include/asm/idt.h | 16 ------- xen/arch/x86/pv/traps.c | 13 ------ xen/arch/x86/traps.c | 76 +--------------------------------- xen/arch/x86/x86_64/entry.S | 60 --------------------------- 4 files changed, 1 insertion(+), 164 deletions(-) diff --git a/xen/arch/x86/include/asm/idt.h b/xen/arch/x86/include/asm/idt.h index 3e3acdfa7930..a80a09517e00 100644 --- a/xen/arch/x86/include/asm/idt.h +++ b/xen/arch/x86/include/asm/idt.h @@ -74,22 +74,6 @@ static inline void _write_gate_lower(volatile idt_entry_t *gate, gate->a = new->a; } -#define _set_gate(gate_addr,type,dpl,addr) \ -do { \ - (gate_addr)->a = 0; \ - smp_wmb(); /* disable gate /then/ rewrite */ \ - (gate_addr)->b = \ - ((unsigned long)(addr) >> 32); \ - smp_wmb(); /* rewrite /then/ enable gate */ \ - (gate_addr)->a = \ - (((unsigned long)(addr) & 0xFFFF0000UL) << 32) | \ - ((unsigned long)(dpl) << 45) | \ - ((unsigned long)(type) << 40) | \ - ((unsigned long)(addr) & 0xFFFFUL) | \ - ((unsigned long)__HYPERVISOR_CS << 16) | \ - (1UL << 47); \ -} while (0) - static inline void _set_gate_lower(idt_entry_t *gate, unsigned long type, unsigned long dpl, void *addr) { diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 4aeb6cab5238..932800555bca 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -141,21 +141,8 @@ static void cf_check nmi_softirq(void) *v_ptr = NULL; } -void nocall entry_int80(void); -void nocall entry_int82(void); - void __init pv_trap_init(void) { -#ifdef CONFIG_PV32 - /* The 32-on-64 hypercall vector is only accessible from ring 1. */ - _set_gate(bsp_idt + HYPERCALL_VECTOR, - SYS_DESC_irq_gate, 1, entry_int82); -#endif - - /* Fast trap for int80 (faster than taking the #GP-fixup path). */ - _set_gate(bsp_idt + LEGACY_SYSCALL_VECTOR, SYS_DESC_irq_gate, 3, - &entry_int80); - open_softirq(NMI_SOFTIRQ, nmi_softirq); } diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index aa3ed658def6..5f6c9def5afb 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2074,22 +2074,6 @@ void asmlinkage do_entry_CP(struct cpu_user_regs *regs) panic("CONTROL-FLOW PROTECTION FAULT: #CP[%04x] %s\n", ec, err); } -static void __init noinline __set_intr_gate(unsigned int n, - uint32_t dpl, void *addr) -{ - _set_gate(&bsp_idt[n], SYS_DESC_irq_gate, dpl, addr); -} - -static void __init set_swint_gate(unsigned int n, void *addr) -{ - __set_intr_gate(n, 3, addr); -} - -static void __init set_intr_gate(unsigned int n, void *addr) -{ - __set_intr_gate(n, 0, addr); -} - void percpu_traps_init(void) { subarch_percpu_traps_init(); @@ -2098,50 +2082,10 @@ void percpu_traps_init(void) wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); } -/* Exception entries */ -void nocall entry_DE(void); -void nocall entry_DB(void); -void nocall entry_NMI(void); -void nocall entry_BP(void); -void nocall entry_OF(void); -void nocall entry_BR(void); -void nocall entry_UD(void); -void nocall entry_NM(void); -void nocall entry_DF(void); -void nocall entry_TS(void); -void nocall entry_NP(void); -void nocall entry_SS(void); -void nocall entry_GP(void); -void nocall early_page_fault(void); void nocall entry_PF(void); -void nocall entry_MF(void); -void nocall entry_AC(void); -void nocall entry_MC(void); -void nocall entry_XM(void); -void nocall entry_CP(void); void __init init_idt_traps(void) { - set_intr_gate (X86_EXC_DE, entry_DE); - set_intr_gate (X86_EXC_DB, entry_DB); - set_intr_gate (X86_EXC_NMI, entry_NMI); - set_swint_gate(X86_EXC_BP, entry_BP); - set_swint_gate(X86_EXC_OF, entry_OF); - set_intr_gate (X86_EXC_BR, entry_BR); - set_intr_gate (X86_EXC_UD, entry_UD); - set_intr_gate (X86_EXC_NM, entry_NM); - set_intr_gate (X86_EXC_DF, entry_DF); - set_intr_gate (X86_EXC_TS, entry_TS); - set_intr_gate (X86_EXC_NP, entry_NP); - set_intr_gate (X86_EXC_SS, entry_SS); - set_intr_gate (X86_EXC_GP, entry_GP); - set_intr_gate (X86_EXC_PF, early_page_fault); - set_intr_gate (X86_EXC_MF, entry_MF); - set_intr_gate (X86_EXC_AC, entry_AC); - set_intr_gate (X86_EXC_MC, entry_MC); - set_intr_gate (X86_EXC_XM, entry_XM); - set_intr_gate (X86_EXC_CP, entry_CP); - /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */ enable_each_ist(bsp_idt); @@ -2189,31 +2133,13 @@ static void __init init_ler(void) setup_force_cpu_cap(X86_FEATURE_XEN_LBR); } -extern void (*const autogen_entrypoints[X86_IDT_VECTORS])(void); void __init trap_init(void) { - unsigned int vector; - /* Replace early pagefault with real pagefault handler. */ - set_intr_gate(X86_EXC_PF, entry_PF); + _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF); pv_trap_init(); - for ( vector = 0; vector < X86_IDT_VECTORS; ++vector ) - { - if ( autogen_entrypoints[vector] ) - { - /* Found autogen entry: check we won't clobber an existing trap. */ - ASSERT(bsp_idt[vector].b == 0); - set_intr_gate(vector, autogen_entrypoints[vector]); - } - else - { - /* No entry point: confirm we have an existing trap in place. */ - ASSERT(bsp_idt[vector].b != 0); - } - } - init_ler(); /* Cache {,compat_}gdt_l1e now that physically relocation is done. */ diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S index 313711a01184..8e56ffbaf9f8 100644 --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -1304,63 +1304,3 @@ END(bsp_idt) .error "Bad bsp_idt size, should be PAGE_SIZE" .endif .popsection - -/* Table of automatically generated entry points. One per vector. */ - .pushsection .init.rodata, "a", @progbits -DATA(autogen_entrypoints, 8) - /* pop into the .init.rodata section and record an entry point. */ - .macro entrypoint ent - .pushsection .init.rodata, "a", @progbits - .quad \ent - .popsection - .endm - - .popsection -FUNC_LOCAL(autogen_stubs, 0) /* Automatically generated stubs. */ - - vec = 0 - .rept X86_IDT_VECTORS - - /* Common interrupts, heading towards do_IRQ(). */ -#if defined(CONFIG_PV32) - .if vec >= FIRST_IRQ_VECTOR && vec != HYPERCALL_VECTOR && vec != LEGACY_SYSCALL_VECTOR -#elif defined(CONFIG_PV) - .if vec >= FIRST_IRQ_VECTOR && vec != LEGACY_SYSCALL_VECTOR -#else - .if vec >= FIRST_IRQ_VECTOR -#endif - - .align CONFIG_FUNCTION_ALIGNMENT, CODE_FILL -1: - ENDBR64 - pushq $0 - movb $vec, EFRAME_entry_vector(%rsp) - jmp common_interrupt - - entrypoint 1b - - /* Reserved exceptions, heading towards do_unhandled_trap(). */ - .elseif vec == X86_EXC_CSO || vec == X86_EXC_SPV || \ - vec == X86_EXC_VE || (vec > X86_EXC_CP && vec < X86_EXC_NUM) - -1: - ENDBR64 - test $8,%spl /* 64bit exception frames are 16 byte aligned, but the word */ - jz 2f /* size is 8 bytes. Check whether the processor gave us an */ - pushq $0 /* error code, and insert an empty one if not. */ -2: movb $vec, EFRAME_entry_vector(%rsp) - jmp handle_exception - - entrypoint 1b - - /* Hand crafted entry points above. */ - .else - entrypoint 0 - .endif - - vec = vec + 1 - .endr -END(autogen_stubs) - - .section .init.rodata, "a", @progbits -END(autogen_entrypoints) From patchwork Mon Feb 24 16:05:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13988439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCE31C021BB for ; Mon, 24 Feb 2025 16:08:05 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.895271.1303929 (Exim 4.92) (envelope-from ) id 1tmazK-0005ac-Kj; Mon, 24 Feb 2025 16:07:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 895271.1303929; Mon, 24 Feb 2025 16:07:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tmazK-0005Za-Ba; Mon, 24 Feb 2025 16:07:22 +0000 Received: by outflank-mailman (input) for mailman id 895271; Mon, 24 Feb 2025 16:07:21 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tmazI-0004jn-PW for xen-devel@lists.xenproject.org; Mon, 24 Feb 2025 16:07:20 +0000 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [2a00:1450:4864:20::336]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 6c043abb-f2c9-11ef-9897-31a8f345e629; Mon, 24 Feb 2025 17:07:18 +0100 (CET) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-439a1e8ba83so43793845e9.3 for ; Mon, 24 Feb 2025 08:07:18 -0800 (PST) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. [92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b02d6837sm109356675e9.13.2025.02.24.08.07.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 08:07:17 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6c043abb-f2c9-11ef-9897-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1740413238; x=1741018038; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/vkRGkyBus2gEBLdspjKGggtdKVPeJ87gwlguifSmpE=; b=NY6boNPT93eQUcy8/fvz5kUg/F/j5U5vsPQfqKLMOwWT7sT/kPFD+TK0nlxyHBK4tK dpO3G/Aitmt6ulB91K+ud0ICTxeGHr7ucnzT4vYqqW7CoxvolxW1CZvrLf+58+sjHXJ1 /w8E5PkjeYdG0Azab23m+CsklWZwItc8n/wsI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740413238; x=1741018038; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/vkRGkyBus2gEBLdspjKGggtdKVPeJ87gwlguifSmpE=; b=iSmq7OPvvP3E/pek5kajEhasuuDPttZiHivBbchS1UE6iDo7ANU8vuyphJSRtCOZYG 2Ciq+SmMK+JN8A6nU6Zl5CSITnMRJHtA+fK/9D9zfAYM41CSpB29yntWT9y5vEdlYz2m 106s80yVA8KtfngtuDZo4RZ/ws/0cp7Ija+Hhnol5sE2K1QWxg9839TF+2Bu3gBvrQ5S DIFkaYMVu1Mn4DormggiQI6qc5siF5eynWilYOQpntNqpxVYnnXYe/K8G2vMHS7obrCu ZPvlzODfJv4BbWfIdkF48P9jZCMHso0Ea1rg5klNu80booMIUh58OFfwIYbbidMVsoru 3Cpw== X-Gm-Message-State: AOJu0YyaLHzeK/d4kThx0Uk6u5cLLdiY1UQ2qONlv/N6tkoMrkkXjde7 gJPHLYMg0zc81sFuO1MM7u+fTW266qnP/BM2acCkowQxCyWjaBYU95SZJlSnCnvu/HbW4CDkw14 T X-Gm-Gg: ASbGncs0DhJW0YZr6I88nQxMV9u+36r34EKw7iqUG9NZMmljB9SoeZfKYhDgKv0n9uV /5llSJOpNgbNAtomaDOlu+YwAAUSpbVcue6N0WtPEet/Q8hp3U58uH9q1PWwFAOSrAC7P/MfL3M Db+EgcD2JyYDLNO220dQddf1kNYvMNXogPYXJKYKGjDdvT2J3HgFxExtTfQ7K1AxHvKFiP+IAl8 8zTn1Qe8r7HR5HWnY27IRZlei6VuIf9yQr305Sfu9XgBjK+sstMqE4V9eSI7jXAyDXKz38NtoS9 adCdE5TlX4O1r5wZWUA9gElWQPQpdGmkMm525HYrStcKMBmakZTuYCTmcrKINPagDekrizx93I5 qlbOF+Q== X-Google-Smtp-Source: AGHT+IGi1zYZDpGvr8GwpT7jAKnxfA8om/IlUkaskGzi1JgviCxfXmyY3iuevrVF3OVbEwaqA8br1w== X-Received: by 2002:a05:600c:468c:b0:439:9361:13d3 with SMTP id 5b1f17b1804b1-439aeb3767emr113331435e9.18.1740413237883; Mon, 24 Feb 2025 08:07:17 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 8/8] x86/traps: Convert pv_trap_init() to being an initcall Date: Mon, 24 Feb 2025 16:05:09 +0000 Message-Id: <20250224160509.1117847-9-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250224160509.1117847-1-andrew.cooper3@citrix.com> References: <20250224160509.1117847-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 With most of pv_trap_init() being done at build time, opening of NMI_SOFTIRQ can be a regular initcall, simplifying trap_init(). No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/include/asm/pv/traps.h | 4 ---- xen/arch/x86/pv/traps.c | 5 ++++- xen/arch/x86/traps.c | 2 -- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/include/asm/pv/traps.h b/xen/arch/x86/include/asm/pv/traps.h index 404f5b169ca8..8c31d5a793c5 100644 --- a/xen/arch/x86/include/asm/pv/traps.h +++ b/xen/arch/x86/include/asm/pv/traps.h @@ -14,8 +14,6 @@ #include -void pv_trap_init(void); - int pv_raise_nmi(struct vcpu *v); int pv_emulate_privileged_op(struct cpu_user_regs *regs); @@ -32,8 +30,6 @@ static inline bool pv_trap_callback_registered(const struct vcpu *v, #include -static inline void pv_trap_init(void) {} - static inline int pv_raise_nmi(struct vcpu *v) { return -EOPNOTSUPP; } static inline int pv_emulate_privileged_op(struct cpu_user_regs *regs) { return 0; } diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 932800555bca..c3c0976c440f 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -141,10 +141,13 @@ static void cf_check nmi_softirq(void) *v_ptr = NULL; } -void __init pv_trap_init(void) +static int __init cf_check pv_trap_init(void) { open_softirq(NMI_SOFTIRQ, nmi_softirq); + + return 0; } +__initcall(pv_trap_init); /* * Deliver NMI to PV guest. Return 0 on success. diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 5f6c9def5afb..454e0d51c596 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2138,8 +2138,6 @@ void __init trap_init(void) /* Replace early pagefault with real pagefault handler. */ _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF); - pv_trap_init(); - init_ler(); /* Cache {,compat_}gdt_l1e now that physically relocation is done. */