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Mon, 24 Feb 2025 19:40:18 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:14 +0000 Subject: [PATCH v2 1/9] target/loongarch: Enable rotr.w/rotri.w for LoongArch32 MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-1-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.149; envelope-from=jiaxun.yang@flygoat.com; helo=fout-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As per "LoongArch Reference Manual Volume 1: Basic Architecture" v1.1.0, "2.2 Table 2. Application-level basic integer instructions in LA32", rotr.w and rotri.w is a part of LA32 basic integer instructions. Note that those instructions are indeed not in LA32R subset, however QEMU is not performing any check against LA32R so far. Make it available to ALL. Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc index 377307785aab4837bc181f1691632e7970a9889d..136c4c845527f0e63902a8306dcaf136dd4dd3fc 100644 --- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc @@ -78,7 +78,7 @@ TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w) TRANS(sll_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d) TRANS(srl_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d) TRANS(sra_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d) -TRANS(rotr_w, 64, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w) +TRANS(rotr_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w) TRANS(rotr_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d) TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl) TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl) @@ -86,5 +86,5 @@ TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl) TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl) TRANS(srai_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w) TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl) -TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w) +TRANS(rotri_w, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w) TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl) From patchwork Tue Feb 25 00:40:15 2025 Content-Type: text/plain; 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Mon, 24 Feb 2025 19:40:19 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:15 +0000 Subject: [PATCH v2 2/9] target/loongarch: Fix address generation for gen_sc MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-2-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.149; envelope-from=jiaxun.yang@flygoat.com; helo=fout-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org gen_sc should use make_address_i to obtain source address to ensure that address is properly truncated. Another temp value is created in middle to avoid data corruption as make_address_i may return the same memory location as src1. Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc index 974bc2a70feddbf021a07b19a0859781eb3a11c4..c35f6f3ce47877ab6ad84fa2cbc50b46c0b23ad1 100644 --- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc @@ -22,13 +22,12 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE); - TCGv t0 = tcg_temp_new(); + TCGv t0 = make_address_i(ctx, src1, a->imm); TCGv val = tcg_temp_new(); TCGLabel *l1 = gen_new_label(); TCGLabel *done = gen_new_label(); - tcg_gen_addi_tl(t0, src1, a->imm); tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1); tcg_gen_movi_tl(dest, 0); tcg_gen_br(done); @@ -36,6 +35,7 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) gen_set_label(l1); tcg_gen_mov_tl(val, src2); /* generate cmpxchg */ + t0 = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val, ctx->mem_idx, mop); tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval); From patchwork Tue Feb 25 00:40:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13989155 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA629C021A4 for ; Tue, 25 Feb 2025 00:43:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmj0R-0004dt-7E; Mon, 24 Feb 2025 19:41:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmizo-0004Xi-Nx for qemu-devel@nongnu.org; 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Mon, 24 Feb 2025 19:40:20 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:16 +0000 Subject: [PATCH v2 3/9] target/loongarch: Fix PGD CSR for LoongArch32 MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-3-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.157; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As per manual, the source of PGD CSR is relevant to highest bit of BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check bit 31 of BADV to determine PGDH/PGDL for LoongArch32. Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/csr_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c index 15f94caefabc7722263fa46e948e21de37b4203c..821aa6af46ea2129d771fdc937eca72317cefc1e 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -26,7 +26,7 @@ target_ulong helper_csrrd_pgd(CPULoongArchState *env) v = env->CSR_BADV; } - if ((v >> 63) & 0x1) { + if (extract64(v, is_la64(env) ? 63 : 31, 1)) { v = env->CSR_PGDH; } else { v = env->CSR_PGDL; From patchwork Tue Feb 25 00:40:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13989150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3C54C021B8 for ; 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Mon, 24 Feb 2025 19:40:21 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:17 +0000 Subject: [PATCH v2 4/9] target/loongarch: Perform sign extension for IOCSR reads MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-4-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.157; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As per LoongArch Reference Manual - Volume 1: Basic Architecture, 4.2.2. IOCSR Access Instructions: The reading value is described as "writes it to the general register rd after symbolic expansion." which means it should be sign extended. Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/iocsr_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/iocsr_helper.c index b6916f53d20ca133f0000e773685cb94240bafe2..db30de2523fff01bcc8923eb12c7fca7bedca7bf 100644 --- a/target/loongarch/tcg/iocsr_helper.c +++ b/target/loongarch/tcg/iocsr_helper.c @@ -17,20 +17,20 @@ uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr) { - return address_space_ldub(env->address_space_iocsr, r_addr, - GET_MEMTXATTRS(env), NULL); + return (int8_t)address_space_ldub(env->address_space_iocsr, r_addr, + GET_MEMTXATTRS(env), NULL); } uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr) { - return address_space_lduw(env->address_space_iocsr, r_addr, - GET_MEMTXATTRS(env), NULL); + return (int16_t)address_space_lduw(env->address_space_iocsr, r_addr, + GET_MEMTXATTRS(env), NULL); } uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr) { - return address_space_ldl(env->address_space_iocsr, r_addr, - GET_MEMTXATTRS(env), NULL); + return (int32_t)address_space_ldl(env->address_space_iocsr, r_addr, + GET_MEMTXATTRS(env), NULL); } uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr) From patchwork Tue Feb 25 00:40:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13989154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5C58C021B8 for ; Tue, 25 Feb 2025 00:42:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmizt-0004b6-2w; Mon, 24 Feb 2025 19:40:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmizq-0004Z0-Fn for qemu-devel@nongnu.org; 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Mon, 24 Feb 2025 19:40:22 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:18 +0000 Subject: [PATCH v2 5/9] target/loongarch: Use target_ulong for iocsrrd helper results MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-5-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.157; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Those results are all targeting TCGv values, which means they should be in target_ulong type. Signed-off-by: Jiaxun Yang --- target/loongarch/helper.h | 8 ++++---- target/loongarch/tcg/iocsr_helper.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index b3b64a021536255a3f9decfc10ff61fe8380e2ae..409d93a5b0808f0e32b8c0e2e17cebac9feaf8ed 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -104,10 +104,10 @@ DEF_HELPER_2(csrwr_estat, i64, env, tl) DEF_HELPER_2(csrwr_asid, i64, env, tl) DEF_HELPER_2(csrwr_tcfg, i64, env, tl) DEF_HELPER_2(csrwr_ticlr, i64, env, tl) -DEF_HELPER_2(iocsrrd_b, i64, env, tl) -DEF_HELPER_2(iocsrrd_h, i64, env, tl) -DEF_HELPER_2(iocsrrd_w, i64, env, tl) -DEF_HELPER_2(iocsrrd_d, i64, env, tl) +DEF_HELPER_2(iocsrrd_b, tl, env, tl) +DEF_HELPER_2(iocsrrd_h, tl, env, tl) +DEF_HELPER_2(iocsrrd_w, tl, env, tl) +DEF_HELPER_2(iocsrrd_d, tl, env, tl) DEF_HELPER_3(iocsrwr_b, void, env, tl, tl) DEF_HELPER_3(iocsrwr_h, void, env, tl, tl) DEF_HELPER_3(iocsrwr_w, void, env, tl, tl) diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/iocsr_helper.c index db30de2523fff01bcc8923eb12c7fca7bedca7bf..23d819de0ef9790eb82741f1e8a0e20dc139bf4b 100644 --- a/target/loongarch/tcg/iocsr_helper.c +++ b/target/loongarch/tcg/iocsr_helper.c @@ -15,25 +15,25 @@ #define GET_MEMTXATTRS(cas) \ ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index}) -uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr) +target_ulong helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr) { return (int8_t)address_space_ldub(env->address_space_iocsr, r_addr, GET_MEMTXATTRS(env), NULL); } -uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr) +target_ulong helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr) { return (int16_t)address_space_lduw(env->address_space_iocsr, r_addr, GET_MEMTXATTRS(env), NULL); } -uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr) +target_ulong helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr) { return (int32_t)address_space_ldl(env->address_space_iocsr, r_addr, GET_MEMTXATTRS(env), NULL); } -uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr) +target_ulong helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr) { return address_space_ldq(env->address_space_iocsr, r_addr, GET_MEMTXATTRS(env), NULL); From patchwork Tue Feb 25 00:40:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13989149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0186C021A4 for ; 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Mon, 24 Feb 2025 19:40:23 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:19 +0000 Subject: [PATCH v2 6/9] target/loongarch: Fix some modifiers for log formatting MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-6-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.157; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org target_ulong -> TARGET_FMT_ld vaddr -> VADDR_PRIx uint32_t -> PRIx32 Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +- target/loongarch/tcg/tlb_helper.c | 2 +- target/loongarch/tcg/translate.c | 5 ++--- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc index c35f6f3ce47877ab6ad84fa2cbc50b46c0b23ad1..8584441b543712af8a56aa234c90fd6370c8df01 100644 --- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc @@ -56,7 +56,7 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a, if (a->rd != 0 && (a->rj == a->rd || a->rk == a->rd)) { qemu_log_mask(LOG_GUEST_ERROR, "Warning: source register overlaps destination register" - "in atomic insn at pc=0x" TARGET_FMT_lx "\n", + "in atomic insn at pc=0x%016"VADDR_PRIx"\n", ctx->base.pc_next - 4); return false; } diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 97f38fc391338ba4b76115b142fa76d89e45cd62..a1426b46f36c99e300ab924cb487875ec21ab226 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -517,7 +517,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base, if (unlikely((level == 0) || (level > 4))) { qemu_log_mask(LOG_GUEST_ERROR, - "Attepted LDDIR with level %"PRId64"\n", level); + "Attepted LDDIR with level "TARGET_FMT_ld"\n", level); return base; } diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c index 1fca4afc731c048816618d87610a0cc0fe7579b1..3939670e18d01bd9fc08861532166882fbd3f890 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -287,9 +287,8 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->opcode = translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_next); if (!decode(ctx, ctx->opcode)) { - qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. " - TARGET_FMT_lx ": 0x%x\n", - ctx->base.pc_next, ctx->opcode); + qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. %016"VADDR_PRIx + ": 0x%08"PRIx32"\n", ctx->base.pc_next, ctx->opcode); generate_exception(ctx, EXCCODE_INE); } From patchwork Tue Feb 25 00:40:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13989148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E453C021A4 for ; Tue, 25 Feb 2025 00:41:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmizx-0004bZ-41; Mon, 24 Feb 2025 19:40:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmizr-0004a1-TF for qemu-devel@nongnu.org; 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Mon, 24 Feb 2025 19:40:24 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:20 +0000 Subject: [PATCH v2 7/9] target/loongarch: Use target_ulong for CSR helpers MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-7-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.149; envelope-from=jiaxun.yang@flygoat.com; helo=fout-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All CSRs are meant to be target_ulong wide in our setting. Signed-off-by: Jiaxun Yang --- target/loongarch/helper.h | 14 +++++++------- target/loongarch/tcg/op_helper.c | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index 409d93a5b0808f0e32b8c0e2e17cebac9feaf8ed..a608754b7f52689da9e9f4da1cef68d5af72f2ed 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -97,13 +97,13 @@ DEF_HELPER_1(rdtime_d, i64, env) #ifndef CONFIG_USER_ONLY /* CSRs helper */ -DEF_HELPER_1(csrrd_pgd, i64, env) -DEF_HELPER_1(csrrd_cpuid, i64, env) -DEF_HELPER_1(csrrd_tval, i64, env) -DEF_HELPER_2(csrwr_estat, i64, env, tl) -DEF_HELPER_2(csrwr_asid, i64, env, tl) -DEF_HELPER_2(csrwr_tcfg, i64, env, tl) -DEF_HELPER_2(csrwr_ticlr, i64, env, tl) +DEF_HELPER_1(csrrd_pgd, tl, env) +DEF_HELPER_1(csrrd_cpuid, tl, env) +DEF_HELPER_1(csrrd_tval, tl, env) +DEF_HELPER_2(csrwr_estat, tl, env, tl) +DEF_HELPER_2(csrwr_asid, tl, env, tl) +DEF_HELPER_2(csrwr_tcfg, tl, env, tl) +DEF_HELPER_2(csrwr_ticlr, tl, env, tl) DEF_HELPER_2(iocsrrd_b, tl, env, tl) DEF_HELPER_2(iocsrrd_h, tl, env, tl) DEF_HELPER_2(iocsrrd_w, tl, env, tl) diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c index b17208e5b962f2191b2afa60181bff311d618bba..c9d7e84e7ec9000bab655366bdf6ed8aaa4fd080 100644 --- a/target/loongarch/tcg/op_helper.c +++ b/target/loongarch/tcg/op_helper.c @@ -61,7 +61,7 @@ void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk) } } -target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz) +target_ulong helper_crc32(target_ulong val, target_ulong m, target_ulong sz) { uint8_t buf[8]; target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1); @@ -71,7 +71,7 @@ target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz) return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff); } -target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz) +target_ulong helper_crc32c(target_ulong val, target_ulong m, target_ulong sz) { uint8_t buf[8]; target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1); From patchwork Tue Feb 25 00:40:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13989153 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C45FC021A4 for ; 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Mon, 24 Feb 2025 19:40:25 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:21 +0000 Subject: [PATCH v2 8/9] target/loongarch: Fix load type for gen_ll MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-8-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.149; envelope-from=jiaxun.yang@flygoat.com; helo=fout-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is in TCGv which means it should be a tl type value. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc index 8584441b543712af8a56aa234c90fd6370c8df01..138bcb3e9999b2c186057c658a019136311f1b82 100644 --- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc @@ -9,7 +9,7 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv t0 = make_address_i(ctx, src1, a->imm); - tcg_gen_qemu_ld_i64(t1, t0, ctx->mem_idx, mop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mop); tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr)); tcg_gen_st_tl(t1, tcg_env, offsetof(CPULoongArchState, llval)); gen_set_gpr(a->rd, t1, EXT_NONE); From patchwork Tue Feb 25 00:40:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13989152 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6AF98C021A4 for ; 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Mon, 24 Feb 2025 19:40:26 -0500 (EST) From: Jiaxun Yang Date: Tue, 25 Feb 2025 00:40:22 +0000 Subject: [PATCH v2 9/9] target/loongarch: Introduce max32 CPU type MIME-Version: 1.0 Message-Id: <20250225-la32-fixes1-v2-9-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=202.12.124.157; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce max32 CPU type as it's necessary to demonstrate all features we have in LA32. Signed-off-by: Jiaxun Yang --- target/loongarch/cpu.c | 152 +++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 122 insertions(+), 30 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index f5bc8720d1fc1b28950ee02de5ae6cce86fc6a96..43a18871ea88a92c72a3b3f1493d760df6f0df20 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -375,6 +375,126 @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) return MMU_DA_IDX; } +static void loongarch_la132_initfn(Object *obj) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(obj); + CPULoongArchState *env = &cpu->env; + + int i; + + for (i = 0; i < 21; i++) { + env->cpucfg[i] = 0x0; + } + + cpu->dtb_compatible = "loongarch,Loongson-1C103"; + env->cpucfg[0] = 0x148042; /* PRID */ + + uint32_t data = 0; + data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ + data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); + data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ + data = FIELD_DP32(data, CPUCFG1, UAL, 1); + data = FIELD_DP32(data, CPUCFG1, RI, 0); + data = FIELD_DP32(data, CPUCFG1, EP, 0); + data = FIELD_DP32(data, CPUCFG1, RPLV, 0); + data = FIELD_DP32(data, CPUCFG1, HP, 1); + data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); + env->cpucfg[1] = data; +} + +static void loongarch_max32_initfn(Object *obj) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(obj); + CPULoongArchState *env = &cpu->env; + int i; + + for (i = 0; i < 21; i++) { + env->cpucfg[i] = 0x0; + } + + cpu->dtb_compatible = "loongarch,la32"; + env->cpucfg[0] = 0x148042; /* PRID */ + + uint32_t data = 0; + data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ + data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); + data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ + data = FIELD_DP32(data, CPUCFG1, UAL, 1); + data = FIELD_DP32(data, CPUCFG1, HP, 1); + data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); + env->cpucfg[1] = data; + + data = 0; + data = FIELD_DP32(data, CPUCFG2, FP, 1); + data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); + data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); + data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); + data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); + data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); + env->cpucfg[2] = data; + + data = 0; + data = FIELD_DP32(data, CPUCFG3, CCDMA, 1); + data = FIELD_DP32(data, CPUCFG3, ITLBHMC, 1); + data = FIELD_DP32(data, CPUCFG3, ICHMC, 1); + env->cpucfg[3] = data; + + env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ + + data = 0; + data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); + data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); + env->cpucfg[5] = data; + + data = 0; + data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); + data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); + data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); + data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); + data = FIELD_DP32(data, CPUCFG16, L2_IUINCL, 1); + env->cpucfg[16] = data; + + /* 16K L1I */ + data = 0; + data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); + data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 7); + data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 5); + env->cpucfg[17] = data; + + /* 16K L1D */ + data = 0; + data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); + data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 7); + data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 5); + env->cpucfg[18] = data; + + data = 0; + /* 128K L2 */ + data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 7); + data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 9); + data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 5); + env->cpucfg[19] = data; + + env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); + + env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8); + env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 31); + env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 0); + + env->CSR_PRCFG2 = 0x3ffff000; + + env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); + env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); + env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); + env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); + + loongarch_cpu_post_init(obj); +} + static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu = LOONGARCH_CPU(obj); @@ -473,35 +593,6 @@ static void loongarch_la464_initfn(Object *obj) loongarch_cpu_post_init(obj); } -static void loongarch_la132_initfn(Object *obj) -{ - LoongArchCPU *cpu = LOONGARCH_CPU(obj); - CPULoongArchState *env = &cpu->env; - - int i; - - for (i = 0; i < 21; i++) { - env->cpucfg[i] = 0x0; - } - - cpu->dtb_compatible = "loongarch,Loongson-1C103"; - env->cpucfg[0] = 0x148042; /* PRID */ - - uint32_t data = 0; - data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ - data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); - data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); - data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ - data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ - data = FIELD_DP32(data, CPUCFG1, UAL, 1); - data = FIELD_DP32(data, CPUCFG1, RI, 0); - data = FIELD_DP32(data, CPUCFG1, EP, 0); - data = FIELD_DP32(data, CPUCFG1, RPLV, 0); - data = FIELD_DP32(data, CPUCFG1, HP, 1); - data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); - env->cpucfg[1] = data; -} - static void loongarch_max_initfn(Object *obj) { /* '-cpu max' for TCG: we use cpu la464. */ @@ -916,8 +1007,9 @@ static const TypeInfo loongarch_cpu_type_infos[] = { .abstract = true, .class_init = loongarch64_cpu_class_init, }, - DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), + DEFINE_LOONGARCH_CPU_TYPE(32, "max32", loongarch_max32_initfn), + DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), };