From patchwork Tue Feb 25 08:04:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13989443 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5194E25B68E; Tue, 25 Feb 2025 08:04:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740470653; cv=none; b=TGOaaUqPbuX10xMvtxCNjGEsSdoCq+IVnFJ131tccSzgP/wkjpmLLAVOlaVIYz7C00qSJ5HMG955GywTF5kWMwVeL5iZITM6qJSrbGnl+F9DxFEVwJ5FkkDroXQrd7Zn6mflKFTzBkS4NTWdl4A2us1rErNfSIU+L0SHSQ+zVy0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740470653; c=relaxed/simple; bh=9KVXWc8stYPpZlIbVSdXAfaPi9fFh/5ieJlqnGagLLU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=flfoUXd5I7W0bUAUz515i6LlzK8NFmETqLQLPvZ9YxP8iG9AFJikb10oOURqDX03XnKRY8t/LmdJ/afjDoeH1HfzEaaep+UpATvH62w/pPsiXA0mVBu+1FLK8JUTDjb27D5DkNdsH/v7zUugetMcNMxmeysLr4jBF5EeakgHIqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VpXbLunl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VpXbLunl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3D596C4CEE2; Tue, 25 Feb 2025 08:04:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740470652; bh=9KVXWc8stYPpZlIbVSdXAfaPi9fFh/5ieJlqnGagLLU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VpXbLunl6/8IB3r01XBqTcYmSUeZ/CortIR3eiQTx8B7bHYs11bLt+WbFoAnpKqWd Qq24B5fsGZS84YUpM6ScHIfy6LazheD4VMH4yveFQyEvIIaKJ2KGN2MUFQK59fXBou UbeWE4TJ4B6tSwe3FVzbH/s8qlot1rm/JNhqwG34reaFG1zupwzDYU4+yTgFC1eV1z oRcmeydRSpotdij74XsbtX6p/pBwXTnEcFrz/VTMlotWivj+wysztkMtEbQGQdn4EI 0nsgkjZ4I0KHXl//0j5DWSnkT23PxyVQ5t9FF4pJqQpF5SMx1VLm+E1+oy+tyusjPm L9uhGM5WC/kNQ== From: Lorenzo Bianconi Date: Tue, 25 Feb 2025 09:04:06 +0100 Subject: [PATCH v4 1/2] dt-bindings: PCI: mediatek-gen3: Add mediatek,pbus-csr phandle array property Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250225-en7581-pcie-pbus-csr-v4-1-24324382424a@kernel.org> References: <20250225-en7581-pcie-pbus-csr-v4-0-24324382424a@kernel.org> In-Reply-To: <20250225-en7581-pcie-pbus-csr-v4-0-24324382424a@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Lorenzo Bianconi Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 Introduce the mediatek,pbus-csr property for the pbus-csr syscon node available on EN7581 SoC. The airoha pbus-csr block provides a configuration interface for the PBUS controller used to detect if a given address is accessible on PCIe controller. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index f05aab2b1addcac91d4685d7d94f421814822b92..162406e0691a81044406aa8f9e60605d0d917811 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -109,6 +109,17 @@ properties: power-domains: maxItems: 1 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 @@ -168,6 +179,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -197,6 +210,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -224,6 +239,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: From patchwork Tue Feb 25 08:04:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13989444 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 283312153E6; Tue, 25 Feb 2025 08:04:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740470656; cv=none; b=q53eiMEYdau22iiVINjlRmPB7UigZRwLjGSJ/+bQjAii0BjYfB9CFk51wR9Ucyyh+tFeOyz3jvD3QCntnpJwhkCDJrvZSJWBT9t7O8CqMAEDTMcvZgezzeRIZlj7KPKI9P+ikUqpb54JnJ8AeJuMFiZh2oa1sH/h+2mzLGK8is4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740470656; c=relaxed/simple; bh=UIr6nl14PNT9O4sqrjXYAxiPPUTsIADVOWslxLJu8eE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=X4IZgrMHF/6V2NYvgM4MSNa6I3ML3DTU8GOK9knJw8Rx3WBnhYzwTQdsXiRP/rWp2vzBaB2/0vyT/Wg5mmTW93GUA4aW1rbo1/ogMFjFI4IjQHC0WxAt8hmb4azQSTxXl56YRPuaQ7n7L7pd7lBSB28ebS/EyIZct6H72z6rvBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HazrX7jc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HazrX7jc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1EA54C4CEE2; Tue, 25 Feb 2025 08:04:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740470655; bh=UIr6nl14PNT9O4sqrjXYAxiPPUTsIADVOWslxLJu8eE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HazrX7jcNWGDWPn00kfwIVFAZrjrOIBlHvF+GFuYvJW8uoqNS3ZZRIdbOhlVlMZlX X3Op2ucNDqG6zvoE/1kq8WIEibknLRURU287GeRnMXwegTD6rBSZDv+0vOs2xF3UW1 AeEA9ZrFrsJh/Ke3stfrdxT7GPdxnHATTSCx3AU3HJVOonvZLgLz7amEVY+sD06SGu 0KbZqydZzhF/vAzBsf7V3m8s7ZE2jgTnBzF36r8mK2jGdrTPjBHXBJa2FA5Zlvzj9h 5l+ib7csstl5fMKyONEYosEt5Fqw/SNWUDIbQmLZnsq5FJ1HawjZ46XmzlLqBMzdPz vEgzTqDtIV36A== From: Lorenzo Bianconi Date: Tue, 25 Feb 2025 09:04:07 +0100 Subject: [PATCH v4 2/2] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250225-en7581-pcie-pbus-csr-v4-2-24324382424a@kernel.org> References: <20250225-en7581-pcie-pbus-csr-v4-0-24324382424a@kernel.org> In-Reply-To: <20250225-en7581-pcie-pbus-csr-v4-0-24324382424a@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Lorenzo Bianconi Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= X-Mailer: b4 0.14.2 Configure PBus base address and address mask to allow the hw to detect if a given address is accessible on PCIe controller. Fixes: f6ab898356dd ("PCI: mediatek-gen3: Add Airoha EN7581 support") Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 0f64e76e2111468e6a453889ead7fbc75804faf7..3583e5481dc8a6a357738048fc341c22204527d9 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -930,9 +932,13 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) { + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); struct device *dev = pcie->dev; + struct resource_entry *entry; + struct regmap *pbus_regmap; + u32 val, args[2], size; + resource_size_t addr; int err; - u32 val; /* * The controller may have been left out of reset by the bootloader @@ -944,6 +950,26 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) /* Wait for the time needed to complete the reset lines assert. */ msleep(PCIE_EN7581_RESET_TIME_MS); + /* + * Configure PBus base address and base address mask to allow the + * hw to detect if a given address is accessible on PCIe controller. + */ + pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, + "mediatek,pbus-csr", + ARRAY_SIZE(args), + args); + if (IS_ERR(pbus_regmap)) + return PTR_ERR(pbus_regmap); + + entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) + return -ENODEV; + + addr = entry->res->start - entry->offset; + regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); + size = lower_32_bits(resource_size(entry->res)); + regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); + /* * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 * requires PHY initialization and power-on before PHY reset deassert.