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a=ed25519-sha256; t=1740476062; l=5709; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=brkFgGbvu8Si1vNLuH/EyodmI+pPyxs89QuPsEBMO1M=; b=8VJIODrxDNySrUb8DA3brne3D67GwyM9bxMEYuBbY/IBld+zlE7Q3K59qObaWFZ78uPgyN+zR yjnkB/X8NU/D9ploAU1/XjeUiKoEQdlY9d7mdqAagOnOI4o9YZUgREw X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: mkBTNilHXKHoq7SteiZw5PSQ-9Tw1O-b X-Proofpoint-ORIG-GUID: mkBTNilHXKHoq7SteiZw5PSQ-9Tw1O-b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 adultscore=0 phishscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502250066 From: Krishna chaitanya chundru Add a device tree binding for the Toshiba TC956x PCIe switch, which provides an Ethernet MAC integrated to the 3rd downstream port and two downstream PCIe ports. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/pci/toshiba,tc956x.yaml | 178 +++++++++++++++++++++ 1 file changed, 178 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/toshiba,tc956x.yaml b/Documentation/devicetree/bindings/pci/toshiba,tc956x.yaml new file mode 100644 index 000000000000..ffed23004f0d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/toshiba,tc956x.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/toshiba,tc956x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC956x PCIe switch + +maintainers: + - Krishna chaitanya chundru + +description: | + Toshiba TC956x PCIe switch has one upstream and three downstream + ports. The 3rd downstream port has integrated endpoint device of + Ethernet MAC. Other two downstream ports are supposed to connect + to external device. + + The TC956x PCIe switch can be configured through I2C interface before + PCIe link is established to change FTS, ASPM related entry delays, + tx amplitude etc for better power efficiency and functionality. + +properties: + compatible: + items: + - enum: + - "pci1179,0623" + - const: pciclass,0604 + + reg: + maxItems: 1 + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A phandle to the parent I2C node and the slave address of the device + used to do configure tc956x to change FTS, tx amplitude etc. + items: + - description: Phandle to the I2C controller node + - description: I2C slave address + + vdd18-supply: true + + vdd09-supply: true + + vddc-supply: true + + vddio1-supply: true + + vddio2-supply: true + + vddio18-supply: true + + reset-gpios: + maxItems: 1 + description: + GPIO controlling the RESX# pin. + +allOf: + - $ref: "#/$defs/tc956x-node" + +patternProperties: + "^pcie@[1-3],0$": + description: + child nodes describing the internal downstream ports + the tc956x switch. + type: object + $ref: "#/$defs/tc956x-node" + unevaluatedProperties: false + +$defs: + tc956x-node: + type: object + + properties: + tc956x,tx-amplitude-microvolt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Change Tx Margin setting for low power consumption. + + tc956x,no-dfe-support: + type: boolean + description: + Disable DFE (Decision Feedback Equalizer), which mitigates + intersymbol interference and some reflections caused by impedance mismatches. + + allOf: + - $ref: /schemas/pci/pci-pci-bridge.yaml# + +unevaluatedProperties: false + +required: + - vdd18-supply + - vdd09-supply + - vddc-supply + - vddio1-supply + - vddio2-supply + - vddio18-supply + - i2c-parent + - reset-gpios + +examples: + - | + #include + + pcie { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + bus-range = <0x01 0xff>; + + pcie@0,0 { + compatible = "pci1179,0623", "pciclass,0604"; + + reg = <0x10000 0x0 0x0 0x0 0x0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + bus-range = <0x02 0xff>; + + i2c-parent = <&qup_i2c 0x77>; + + vdd18-supply = <&vdd>; + vdd09-supply = <&vdd>; + vddc-supply = <&vdd>; + vddio1-supply = <&vdd>; + vddio2-supply = <&vdd>; + vddio18-supply = <&vdd>; + + reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x03 0xff>; + + tc956x,no-dfe-support; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x04 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; 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Two embedded Ethernet devices are present on one of the downstream ports. Power to the TC956x is supplied through two LDO regulators, controlled by two GPIOs, which are added as fixed regulators. Configure the TC956x through I2C. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Bjorn Andersson Acked-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 116 +++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 2 files changed, 117 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 7a36c90ad4ec..13dbb24a3179 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -218,6 +218,31 @@ vph_pwr: vph-pwr-regulator { regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; }; + + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_0P9"; + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <899400>; + regulator-max-microvolt = <899400>; + enable-active-high; + pinctrl-0 = <&ntn_0p9_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_1P8"; + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&ntn_1p8_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <10000>; + }; + }; &apps_rsc { @@ -735,6 +760,75 @@ &pcie1_phy { status = "okay"; }; +&pcie1_port { + pcie@0,0 { + compatible = "pci1179,0623", "pciclass,0604"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + i2c-parent = <&i2c0 0x77>; + + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pcie@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pcie@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins = "gpio6"; @@ -839,6 +933,28 @@ &sdhc_2 { status = "okay"; }; +&pm8350c_gpios { + ntn_0p9_en: ntn-0p9-en-state { + pins = "gpio2"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + ntn_1p8_en: ntn-1p8-en-state { + pins = "gpio3"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0f2caf36910b..b2e2b1f26731 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2284,7 +2284,7 @@ pcie1: pcie@1c08000 { status = "disabled"; - pcie@0 { + pcie1_port: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From patchwork Tue Feb 25 09:34:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13989619 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D629526158C for ; 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Tue, 25 Feb 2025 01:34:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IGkTr/zaRhtjk7yZHJlTH42C0GF7O7ieoM0aPS51ydoOaKSFln0kJiX7IFN15MoAYzjjQgltA== X-Received: by 2002:a17:90b:2dc6:b0:2fa:1e3e:9be5 with SMTP id 98e67ed59e1d1-2fe68a2df32mr5100129a91.0.1740476086972; Tue, 25 Feb 2025 01:34:46 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fe6a3dec52sm1080770a91.20.2025.02.25.01.34.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 01:34:46 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 25 Feb 2025 15:04:00 +0530 Subject: [PATCH v4 03/10] PCI: Add new start_link() & stop_link function ops Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250225-qps615_v4_1-v4-3-e08633a7bdf8@oss.qualcomm.com> References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> In-Reply-To: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski Cc: quic_vbadigan@quicnic.com, amitk@kernel.org, dmitry.baryshkov@linaro.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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When the PCI bridge is found, its child DT nodes will be scanned and pwrctrl devices will be created if needed. By the time pwrctrl driver probe gets called link training is already enabled by controller driver. Certain devices like TC956x which uses PCI pwrctl framework needs to configure the device before PCI link is up. As the controller driver already enables link training as part of its probe, the moment device is powered on, controller and device participates in the link training and link can come up immediately and maynot have time to configure the device. So we need to stop the link training by using stop_link() and enable them back after device is configured by using start_link(). Signed-off-by: Krishna Chaitanya Chundru --- include/linux/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa..bbec32be668b 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -804,6 +804,8 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + int (*start_link)(struct pci_bus *bus); + void (*stop_link)(struct pci_bus *bus); }; /* From patchwork Tue Feb 25 09:34:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13989620 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1825264A87 for ; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 501d9ddfea16..47f34dd12c39 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -435,6 +435,8 @@ struct dw_pcie_ops { enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); + int (*host_start_link)(struct dw_pcie *pcie); + void (*host_stop_link)(struct dw_pcie *pcie); }; struct dw_pcie { @@ -664,6 +666,20 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci) pci->ops->stop_link(pci); } +static inline int dw_pcie_host_start_link(struct dw_pcie *pci) +{ + if (pci->ops && pci->ops->host_start_link) + return pci->ops->host_start_link(pci); + + return 0; +} + +static inline void dw_pcie_host_stop_link(struct dw_pcie *pci) +{ + if (pci->ops && pci->ops->host_stop_link) + pci->ops->host_stop_link(pci); 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index ffaded8f2df7..2d3ec61e8dfa 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -697,10 +697,28 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); +static int dw_pcie_op_start_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + return dw_pcie_host_start_link(pci); +} + +static void dw_pcie_op_stop_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + dw_pcie_host_stop_link(pci); +} + static struct pci_ops dw_pcie_ops = { .map_bus = dw_pcie_own_conf_map_bus, .read = pci_generic_config_read, .write = pci_generic_config_write, + .start_link = dw_pcie_op_start_link, + .stop_link = dw_pcie_op_stop_link, }; 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Assert PERST# and disable LTSSM bit to prevent the PCIe controller from participating in link training during host_stop_link(). De-assert PERST# and enable LTSSM bit during host_start_link(). Introduce ltssm_disable function op to stop link training. For the switches like TC956x, which needs to configure it before the PCIe link is established. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e4d3366ead1f..8c9c89417440 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -247,6 +247,7 @@ struct qcom_pcie_ops { void (*host_post_init)(struct qcom_pcie *pcie); void (*deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); + void (*ltssm_disable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); }; @@ -618,6 +619,37 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) return 0; } +static int qcom_pcie_host_start_link(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + + qcom_ep_reset_deassert(pcie); + + if (pcie->cfg->ops->ltssm_enable) + pcie->cfg->ops->ltssm_enable(pcie); + + return 0; +} + +static void qcom_pcie_host_stop_link(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + + qcom_ep_reset_assert(pcie); + + if (pcie->cfg->ops->ltssm_disable) + pcie->cfg->ops->ltssm_disable(pcie); +} + +static void qcom_pcie_2_3_2_ltssm_disable(struct qcom_pcie *pcie) +{ + u32 val; + + val = readl(pcie->parf + PARF_LTSSM); + val &= ~LTSSM_EN; + writel(val, pcie->parf + PARF_LTSSM); +} + static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) { u32 val; @@ -1362,6 +1394,7 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .host_post_init = qcom_pcie_host_post_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .ltssm_disable = qcom_pcie_2_3_2_ltssm_disable, .config_sid = qcom_pcie_config_sid_1_9_0, }; @@ -1429,6 +1462,8 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, + .host_start_link = qcom_pcie_host_start_link, + .host_stop_link = qcom_pcie_host_stop_link, }; static int qcom_pcie_icc_init(struct qcom_pcie *pcie) From patchwork Tue Feb 25 09:34:04 2025 Content-Type: text/plain; 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Tue, 25 Feb 2025 01:35:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IFXI2cvrJrVKemjd3SibfbqUc08kbM1mQxwPvC2ZFCfh6cLWmlluxx8UqPeRlPhYbWspo8iAA== X-Received: by 2002:a17:90a:da87:b0:2fa:1f1b:3db6 with SMTP id 98e67ed59e1d1-2fce875b1e1mr27083647a91.29.1740476111099; Tue, 25 Feb 2025 01:35:11 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fe6a3dec52sm1080770a91.20.2025.02.25.01.35.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 01:35:10 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 25 Feb 2025 15:04:04 +0530 Subject: [PATCH v4 07/10] PCI: PCI: Add pcie_is_link_active() to determine if the PCIe link is active Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250225-qps615_v4_1-v4-7-e08633a7bdf8@oss.qualcomm.com> References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> In-Reply-To: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski Cc: quic_vbadigan@quicnic.com, amitk@kernel.org, dmitry.baryshkov@linaro.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/hotplug/pciehp_hpc.c | 13 +------------ drivers/pci/pci.c | 26 +++++++++++++++++++++++--- include/linux/pci.h | 5 +++++ 3 files changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index bb5a8d9f03ad..d0a2efebb519 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -234,18 +234,7 @@ static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) */ int pciehp_check_link_active(struct controller *ctrl) { - struct pci_dev *pdev = ctrl_dev(ctrl); - u16 lnk_status; - int ret; - - ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); - if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(lnk_status)) - return -ENODEV; - - ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); - ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); - - return ret; + return pcie_is_link_active(ctrl_dev(ctrl)); } static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 869d204a70a3..3d4fe6fefa13 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4907,7 +4907,6 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type) return 0; if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) { - u16 status; pci_dbg(dev, "waiting %d ms for downstream link\n", delay); msleep(delay); @@ -4923,8 +4922,7 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type) if (!dev->link_active_reporting) return -ENOTTY; - pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &status); - if (!(status & PCI_EXP_LNKSTA_DLLLA)) + if (pcie_is_link_active(dev)) return -ENOTTY; return pci_dev_wait(child, reset_type, @@ -6219,6 +6217,28 @@ void pcie_print_link_status(struct pci_dev *dev) } EXPORT_SYMBOL(pcie_print_link_status); +/** + * pcie_is_link_active() - Checks if the link is active or not + * @pdev: PCI device to query + * + * Check whether the link is active or not. + * + * If the config read returns error then return -ENODEV. + */ +int pcie_is_link_active(struct pci_dev *pdev) +{ + u16 lnk_status; + int ret; + + ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); + if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(lnk_status)) + return -ENODEV; + + pci_dbg(pdev, "lnk_status = %x\n", lnk_status); + return !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); +} +EXPORT_SYMBOL(pcie_is_link_active); + /** * pci_select_bars - Make BAR mask from the type of resource * @dev: the PCI device for which BAR mask is made diff --git a/include/linux/pci.h b/include/linux/pci.h index bbec32be668b..84bb98e61e8a 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1946,6 +1946,7 @@ pci_release_mem_regions(struct pci_dev *pdev) pci_select_bars(pdev, IORESOURCE_MEM)); } +int pcie_is_link_active(struct pci_dev *dev); #else /* CONFIG_PCI is not enabled */ static inline void pci_set_flags(int flags) { } @@ -2094,6 +2095,10 @@ pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, { return -ENOSPC; } + +static inline int pcie_is_link_active(struct pci_dev *dev) +{ return -ENODEV; } + #endif /* CONFIG_PCI */ /* Include architecture-dependent settings and functions */ From patchwork Tue Feb 25 09:34:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13989624 X-Patchwork-Delegate: kw@linux.com Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 245D5263C72 for ; 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Tue, 25 Feb 2025 01:35:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IEpKoyaLC9BE0PgW+pLRLJ3ZL5Zr6S+ZXgHJQ0EqFLNIC8xFmJzelvUpI4UhVYHawu5ZXamxQ== X-Received: by 2002:a17:90b:56d0:b0:2f5:747:cbd with SMTP id 98e67ed59e1d1-2fe68ae292bmr4764958a91.18.1740476117514; Tue, 25 Feb 2025 01:35:17 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fe6a3dec52sm1080770a91.20.2025.02.25.01.35.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 01:35:17 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 25 Feb 2025 15:04:05 +0530 Subject: [PATCH v4 08/10] PCI: pwrctrl: Add power control driver for tc956x Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250225-qps615_v4_1-v4-8-e08633a7bdf8@oss.qualcomm.com> References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> In-Reply-To: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski Cc: quic_vbadigan@quicnic.com, amitk@kernel.org, dmitry.baryshkov@linaro.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, Krishna Chaitanya Chundru , Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740476062; l=19426; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=LMnw2grkYulPRTIzz/uk3BUBKeG6SeucXy3zupQY8Lo=; b=Cv10bXTLgL5Oc+3lVkZ9LI4O1smWriwz9Z1xqx/d9AISdVgq1ccCvbQUruiIlTfIY3FQAzuDQ AM2ZSSmUUD9A7OPZMFTDz23i7s9rFAcwNYmKV8+QYyT8cAR/FWHsPKH X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: 22hQGICBqNLlcNwaUQd4myikHnh1AaIm X-Proofpoint-ORIG-GUID: 22hQGICBqNLlcNwaUQd4myikHnh1AaIm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 phishscore=0 impostorscore=0 malwarescore=0 adultscore=0 spamscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502250066 TC956x is a PCIe switch which has one upstream and three downstream ports. To one of the downstream ports ethernet MAC is connected as endpoint device. Other two downstream ports are supposed to connect to external device. One Host can connect to TC956x by upstream port. TC956x switch needs to be configured after powering on and before PCIe link was up. The PCIe controller driver already enables link training at the host side even before this driver probe happens, due to this when driver enables power to the switch it participates in the link training and PCIe link may come up before configuring the switch through i2c. Once the link is up the configuration done through i2c will not have any affect.To prevent the host from participating in link training, disable link training on the host side to ensure the link does not come up before the switch is configured via I2C. Based up on dt property and type of the port, tc956x is configured through i2c. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Bjorn Andersson Reviewed-by: Bartosz Golaszewski --- drivers/pci/pwrctrl/Kconfig | 6 + drivers/pci/pwrctrl/Makefile | 1 + drivers/pci/pwrctrl/pci-pwrctrl-tc956x.c | 625 +++++++++++++++++++++++++++++++ 3 files changed, 632 insertions(+) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index 54589bb2403b..ae8a0a39f586 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -10,3 +10,9 @@ config PCI_PWRCTL_PWRSEQ tristate select POWER_SEQUENCING select PCI_PWRCTL + +config PCI_PWRCTRL_TC956X + tristate "PCI Power Control driver for TC956x PCIe switch" + select PCI_PWRCTL + help + Say Y here to enable the pwrctrl driver for TC956x PCIe switch. diff --git a/drivers/pci/pwrctrl/Makefile b/drivers/pci/pwrctrl/Makefile index 75c7ce531c7e..93f32871260b 100644 --- a/drivers/pci/pwrctrl/Makefile +++ b/drivers/pci/pwrctrl/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_PWRCTL) += pci-pwrctrl-core.o pci-pwrctrl-core-y := core.o obj-$(CONFIG_PCI_PWRCTL_PWRSEQ) += pci-pwrctrl-pwrseq.o +obj-$(CONFIG_PCI_PWRCTRL_TC956X) += pci-pwrctrl-tc956x.o diff --git a/drivers/pci/pwrctrl/pci-pwrctrl-tc956x.c b/drivers/pci/pwrctrl/pci-pwrctrl-tc956x.c new file mode 100644 index 000000000000..bf72bbcae536 --- /dev/null +++ b/drivers/pci/pwrctrl/pci-pwrctrl-tc956x.c @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" + +#define TC956X_GPIO_CONFIG 0x801208 +#define TC956X_RESET_GPIO 0x801210 + +#define TC956X_BUS_CONTROL 0x801014 + +#define TC956X_PORT_L0S_DELAY 0x82496c +#define TC956X_PORT_L1_DELAY 0x824970 + +#define TC956X_EMBEDDED_ETH_DELAY 0x8200d8 +#define TC956X_ETH_L1_DELAY_MASK GENMASK(27, 18) +#define TC956X_ETH_L1_DELAY_VALUE(x) FIELD_PREP(TC956X_ETH_L1_DELAY_MASK, x) +#define TC956X_ETH_L0S_DELAY_MASK GENMASK(17, 13) +#define TC956X_ETH_L0S_DELAY_VALUE(x) FIELD_PREP(TC956X_ETH_L0S_DELAY_MASK, x) + +#define TC956X_NFTS_2_5_GT 0x824978 +#define TC956X_NFTS_5_GT 0x82497c + +#define TC956X_PORT_LANE_ACCESS_ENABLE 0x828000 + +#define TC956X_PHY_RATE_CHANGE_OVERRIDE 0x828040 +#define TC956X_PHY_RATE_CHANGE 0x828050 + +#define TC956X_TX_MARGIN 0x828234 + +#define TC956X_DFE_ENABLE 0x828a04 +#define TC956X_DFE_EQ0_MODE 0x828a08 +#define TC956X_DFE_EQ1_MODE 0x828a0c +#define TC956X_DFE_EQ2_MODE 0x828a14 +#define TC956X_DFE_PD_MASK 0x828254 + +#define TC956X_PORT_SELECT 0x82c02c +#define TC956X_PORT_ACCESS_ENABLE 0x82c030 + +#define TC956X_POWER_CONTROL 0x82b09c +#define TC956X_POWER_CONTROL_OVREN 0x82b2c8 + +#define TC956X_GPIO_MASK 0xfffffff3 + +#define TC956X_TX_MARGIN_MIN_VAL 400000 + +struct tc956x_pwrctrl_reg_setting { + unsigned int offset; + unsigned int val; +}; + +enum tc956x_pwrctrl_ports { + TC956X_USP, + TC956X_DSP1, + TC956X_DSP2, + TC956X_DSP3, + TC956X_ETHERNET, + TC956X_MAX +}; + +struct tc956x_pwrctrl_cfg { + u32 l0s_delay; + u32 l1_delay; + u32 tx_amp; + u8 nfts[2]; /* GEN1 & GEN2*/ + bool disable_dfe; + bool disable_port; +}; + +#define TC956X_PWRCTL_MAX_SUPPLY 6 + +struct tc956x_pwrctrl_ctx { + struct regulator_bulk_data supplies[TC956X_PWRCTL_MAX_SUPPLY]; + struct tc956x_pwrctrl_cfg cfg[TC956X_MAX]; + struct gpio_desc *reset_gpio; + struct i2c_adapter *adapter; + struct i2c_client *client; + struct pci_pwrctrl pwrctrl; +}; + +/* + * downstream port power off sequence, hardcoding the address + * as we don't know register names for these register offsets. + */ +static const struct tc956x_pwrctrl_reg_setting common_pwroff_seq[] = { + {0x82900c, 0x1}, + {0x829010, 0x1}, + {0x829018, 0x0}, + {0x829020, 0x1}, + {0x82902c, 0x1}, + {0x829030, 0x1}, + {0x82903c, 0x1}, + {0x829058, 0x0}, + {0x82905c, 0x1}, + {0x829060, 0x1}, + {0x8290cc, 0x1}, + {0x8290d0, 0x1}, + {0x8290d8, 0x1}, + {0x8290e0, 0x1}, + {0x8290e8, 0x1}, + {0x8290ec, 0x1}, + {0x8290f4, 0x1}, + {0x82910c, 0x1}, + {0x829110, 0x1}, + {0x829114, 0x1}, +}; + +static const struct tc956x_pwrctrl_reg_setting dsp1_pwroff_seq[] = { + {TC956X_PORT_ACCESS_ENABLE, 0x2}, + {TC956X_PORT_LANE_ACCESS_ENABLE, 0x3}, + {TC956X_POWER_CONTROL, 0x014f4804}, + {TC956X_POWER_CONTROL_OVREN, 0x1}, + {TC956X_PORT_ACCESS_ENABLE, 0x4}, +}; + +static const struct tc956x_pwrctrl_reg_setting dsp2_pwroff_seq[] = { + {TC956X_PORT_ACCESS_ENABLE, 0x8}, + {TC956X_PORT_LANE_ACCESS_ENABLE, 0x1}, + {TC956X_POWER_CONTROL, 0x014f4804}, + {TC956X_POWER_CONTROL_OVREN, 0x1}, + {TC956X_PORT_ACCESS_ENABLE, 0x8}, +}; + +/* + * Since all transfers are initiated by the probe, no locks are necessary, + * as there are no concurrent calls. + */ +static int tc956x_pwrctrl_i2c_write(struct i2c_client *client, + u32 reg_addr, u32 reg_val) +{ + struct i2c_msg msg; + u8 msg_buf[7]; + int ret; + + msg.addr = client->addr; + msg.len = 7; + msg.flags = 0; + + /* Big Endian for reg addr */ + put_unaligned_be24(reg_addr, &msg_buf[0]); + + /* Little Endian for reg val */ + put_unaligned_le32(reg_val, &msg_buf[3]); + + msg.buf = msg_buf; + ret = i2c_transfer(client->adapter, &msg, 1); + return ret == 1 ? 0 : ret; +} + +static int tc956x_pwrctrl_i2c_read(struct i2c_client *client, + u32 reg_addr, u32 *reg_val) +{ + struct i2c_msg msg[2]; + u8 wr_data[3]; + u32 rd_data; + int ret; + + msg[0].addr = client->addr; + msg[0].len = 3; + msg[0].flags = 0; + + /* Big Endian for reg addr */ + put_unaligned_be24(reg_addr, &wr_data[0]); + + msg[0].buf = wr_data; + + msg[1].addr = client->addr; + msg[1].len = 4; + msg[1].flags = I2C_M_RD; + + msg[1].buf = (u8 *)&rd_data; + + ret = i2c_transfer(client->adapter, &msg[0], 2); + if (ret == 2) { + *reg_val = get_unaligned_le32(&rd_data); + return 0; + } + + /* If only one message successfully completed, return -EIO */ + return ret == 1 ? -EIO : ret; +} + +static int tc956x_pwrctrl_i2c_bulk_write(struct i2c_client *client, + const struct tc956x_pwrctrl_reg_setting *seq, int len) +{ + int ret, i; + + for (i = 0; i < len; i++) { + ret = tc956x_pwrctrl_i2c_write(client, seq[i].offset, seq[i].val); + if (ret) + return ret; + } + + return 0; +} + +static int tc956x_pwrctrl_disable_port(struct tc956x_pwrctrl_ctx *ctx, + enum tc956x_pwrctrl_ports port) +{ + struct tc956x_pwrctrl_cfg *cfg = &ctx->cfg[port]; + const struct tc956x_pwrctrl_reg_setting *seq; + int ret, len; + + if (!cfg->disable_port) + return 0; + + if (port == TC956X_DSP1) { + seq = dsp1_pwroff_seq; + len = ARRAY_SIZE(dsp1_pwroff_seq); + } else { + seq = dsp2_pwroff_seq; + len = ARRAY_SIZE(dsp2_pwroff_seq); + } + + ret = tc956x_pwrctrl_i2c_bulk_write(ctx->client, seq, len); + if (ret) + return ret; + + return tc956x_pwrctrl_i2c_bulk_write(ctx->client, + common_pwroff_seq, ARRAY_SIZE(common_pwroff_seq)); +} + +static int tc956x_pwrctrl_set_l0s_l1_entry_delay(struct tc956x_pwrctrl_ctx *ctx, + enum tc956x_pwrctrl_ports port, bool is_l1, u32 ns) +{ + u32 rd_val, units; + int ret; + + if (!ns) + return 0; + + /* convert to units of 256ns */ + units = ns / 256; + + if (port == TC956X_ETHERNET) { + ret = tc956x_pwrctrl_i2c_read(ctx->client, TC956X_EMBEDDED_ETH_DELAY, &rd_val); + if (ret) + return ret; + + if (is_l1) + rd_val = u32_replace_bits(rd_val, units, TC956X_ETH_L1_DELAY_MASK); + else + rd_val = u32_replace_bits(rd_val, units, TC956X_ETH_L0S_DELAY_MASK); + + return tc956x_pwrctrl_i2c_write(ctx->client, TC956X_EMBEDDED_ETH_DELAY, rd_val); + } + + ret = tc956x_pwrctrl_i2c_write(ctx->client, TC956X_PORT_SELECT, BIT(port)); + if (ret) + return ret; + + return tc956x_pwrctrl_i2c_write(ctx->client, + is_l1 ? TC956X_PORT_L1_DELAY : TC956X_PORT_L0S_DELAY, units); +} + +static int tc956x_pwrctrl_set_tx_amplitude(struct tc956x_pwrctrl_ctx *ctx, + enum tc956x_pwrctrl_ports port, u32 amp) +{ + int port_access; + + if (amp < TC956X_TX_MARGIN_MIN_VAL) + return 0; + + /* txmargin = (Amp(uV) - 400000) / 3125 */ + amp = (amp - TC956X_TX_MARGIN_MIN_VAL) / 3125; + + switch (port) { + case TC956X_USP: + port_access = 0x1; + break; + case TC956X_DSP1: + port_access = 0x2; + break; + case TC956X_DSP2: + port_access = 0x8; + break; + default: + return -EINVAL; + }; + + struct tc956x_pwrctrl_reg_setting tx_amp_seq[] = { + {TC956X_PORT_ACCESS_ENABLE, port_access}, + {TC956X_PORT_LANE_ACCESS_ENABLE, 0x3}, + {TC956X_TX_MARGIN, amp}, + }; + + return tc956x_pwrctrl_i2c_bulk_write(ctx->client, tx_amp_seq, ARRAY_SIZE(tx_amp_seq)); +} + +static int tc956x_pwrctrl_disable_dfe(struct tc956x_pwrctrl_ctx *ctx, + enum tc956x_pwrctrl_ports port) +{ + struct tc956x_pwrctrl_cfg *cfg = &ctx->cfg[port]; + int port_access, lane_access = 0x3; + u32 phy_rate = 0x21; + + if (!cfg->disable_dfe) + return 0; + + switch (port) { + case TC956X_USP: + phy_rate = 0x1; + port_access = 0x1; + break; + case TC956X_DSP1: + port_access = 0x2; + break; + case TC956X_DSP2: + port_access = 0x8; + lane_access = 0x1; + break; + default: + return -EINVAL; + }; + + struct tc956x_pwrctrl_reg_setting disable_dfe_seq[] = { + {TC956X_PORT_ACCESS_ENABLE, port_access}, + {TC956X_PORT_LANE_ACCESS_ENABLE, lane_access}, + {TC956X_DFE_ENABLE, 0x0}, + {TC956X_DFE_EQ0_MODE, 0x411}, + {TC956X_DFE_EQ1_MODE, 0x11}, + {TC956X_DFE_EQ2_MODE, 0x11}, + {TC956X_DFE_PD_MASK, 0x7}, + {TC956X_PHY_RATE_CHANGE_OVERRIDE, 0x10}, + {TC956X_PHY_RATE_CHANGE, phy_rate}, + {TC956X_PHY_RATE_CHANGE, 0x0}, + {TC956X_PHY_RATE_CHANGE_OVERRIDE, 0x0}, + }; + + return tc956x_pwrctrl_i2c_bulk_write(ctx->client, + disable_dfe_seq, ARRAY_SIZE(disable_dfe_seq)); +} + +static int tc956x_pwrctrl_set_nfts(struct tc956x_pwrctrl_ctx *ctx, + enum tc956x_pwrctrl_ports port, u8 *nfts) +{ + struct tc956x_pwrctrl_reg_setting nfts_seq[] = { + {TC956X_NFTS_2_5_GT, nfts[0]}, + {TC956X_NFTS_5_GT, nfts[1]}, + }; + int ret; + + if (!nfts[0]) + return 0; + + ret = tc956x_pwrctrl_i2c_write(ctx->client, TC956X_PORT_SELECT, BIT(port)); + if (ret) + return ret; + + return tc956x_pwrctrl_i2c_bulk_write(ctx->client, nfts_seq, ARRAY_SIZE(nfts_seq)); +} + +static int tc956x_pwrctrl_assert_deassert_reset(struct tc956x_pwrctrl_ctx *ctx, bool deassert) +{ + int ret, val; + + ret = tc956x_pwrctrl_i2c_write(ctx->client, TC956X_GPIO_CONFIG, TC956X_GPIO_MASK); + if (ret) + return ret; + + val = deassert ? 0xc : 0; + + return tc956x_pwrctrl_i2c_write(ctx->client, TC956X_RESET_GPIO, val); +} + +static int tc956x_pwrctrl_parse_device_dt(struct tc956x_pwrctrl_ctx *ctx, struct device_node *node, + enum tc956x_pwrctrl_ports port) +{ + struct tc956x_pwrctrl_cfg *cfg; + int ret; + + cfg = &ctx->cfg[port]; + + /* Disable port if the status of the port is disabled. */ + if (!of_device_is_available(node)) { + cfg->disable_port = true; + return 0; + }; + + ret = of_property_read_u32(node, "aspm-l0s-entry-delay-ns", &cfg->l0s_delay); + if (ret && ret != -EINVAL) + return ret; + + ret = of_property_read_u32(node, "aspm-l1-entry-delay-ns", &cfg->l1_delay); + if (ret && ret != -EINVAL) + return ret; + + ret = of_property_read_u32(node, "qcom,tx-amplitude-microvolt", &cfg->tx_amp); + if (ret && ret != -EINVAL) + return ret; + + ret = of_property_read_u8_array(node, "nfts", cfg->nfts, 2); + if (ret && ret != -EINVAL) + return ret; + + cfg->disable_dfe = of_property_read_bool(node, "qcom,no-dfe-support"); + + return 0; +} + +static void tc956x_pwrctrl_power_off(struct tc956x_pwrctrl_ctx *ctx) +{ + gpiod_set_value(ctx->reset_gpio, 1); + + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); +} + +static int tc956x_pwrctrl_bring_up(struct tc956x_pwrctrl_ctx *ctx) +{ + struct tc956x_pwrctrl_cfg *cfg; + int ret, i; + + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret < 0) + return dev_err_probe(ctx->pwrctrl.dev, ret, "cannot enable regulators\n"); + + gpiod_set_value(ctx->reset_gpio, 0); + + /* wait for the internal osc frequency to stablise */ + usleep_range(10000, 10500); + + ret = tc956x_pwrctrl_assert_deassert_reset(ctx, false); + if (ret) + goto power_off; + + for (i = 0; i < TC956X_MAX; i++) { + cfg = &ctx->cfg[i]; + ret = tc956x_pwrctrl_disable_port(ctx, i); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Disabling port failed\n"); + goto power_off; + } + + ret = tc956x_pwrctrl_set_l0s_l1_entry_delay(ctx, i, false, cfg->l0s_delay); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Setting L0s entry delay failed\n"); + goto power_off; + } + + ret = tc956x_pwrctrl_set_l0s_l1_entry_delay(ctx, i, true, cfg->l1_delay); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Setting L1 entry delay failed\n"); + goto power_off; + } + + ret = tc956x_pwrctrl_set_tx_amplitude(ctx, i, cfg->tx_amp); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Setting Tx amplitube failed\n"); + goto power_off; + } + + ret = tc956x_pwrctrl_set_nfts(ctx, i, cfg->nfts); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Setting nfts failed\n"); + goto power_off; + } + + ret = tc956x_pwrctrl_disable_dfe(ctx, i); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Disabling DFE failed\n"); + goto power_off; + } + } + + ret = tc956x_pwrctrl_assert_deassert_reset(ctx, true); + if (!ret) + return 0; + +power_off: + tc956x_pwrctrl_power_off(ctx); + return ret; +} + +static int tc956x_pwrctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pci_dev *pci_dev = to_pci_dev(dev->parent); + struct pci_host_bridge *bridge = pci_find_host_bridge(pci_dev->bus); + enum tc956x_pwrctrl_ports port; + struct tc956x_pwrctrl_ctx *ctx; + int ret, addr; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ret = of_property_read_u32_index(pdev->dev.of_node, "i2c-parent", 1, &addr); + if (ret) + return dev_err_probe(dev, ret, "Failed to read i2c-parent property\n"); + + ctx->adapter = of_find_i2c_adapter_by_node(of_parse_phandle(dev->of_node, "i2c-parent", 0)); + of_node_put(dev->of_node); + if (!ctx->adapter) + return dev_err_probe(dev, -EPROBE_DEFER, "Failed to find I2C adapter\n"); + + ctx->client = i2c_new_dummy_device(ctx->adapter, addr); + if (IS_ERR(ctx->client)) { + dev_err(dev, "Failed to create I2C client\n"); + i2c_put_adapter(ctx->adapter); + return PTR_ERR(ctx->client); + } + + ctx->supplies[0].supply = "vddc"; + ctx->supplies[1].supply = "vdd18"; + ctx->supplies[2].supply = "vdd09"; + ctx->supplies[3].supply = "vddio1"; + ctx->supplies[4].supply = "vddio2"; + ctx->supplies[5].supply = "vddio18"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret) { + dev_err_probe(dev, ret, + "failed to get supply regulator\n"); + goto remove_i2c; + } + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ctx->reset_gpio)) { + ret = dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "failed to get reset GPIO\n"); + goto remove_i2c; + } + + pci_pwrctrl_init(&ctx->pwrctrl, dev); + + port = TC956X_USP; + ret = tc956x_pwrctrl_parse_device_dt(ctx, pdev->dev.of_node, port); + if (ret) { + dev_err(dev, "failed to parse device tree properties: %d\n", ret); + goto remove_i2c; + } + + /* + * Downstream ports are always children of the upstream port. + * The first node represents DSP1, the second node represents DSP2, and so on. + */ + for_each_child_of_node_scoped(pdev->dev.of_node, child) { + ret = tc956x_pwrctrl_parse_device_dt(ctx, child, port++); + if (ret) + break; + /* Embedded ethernet device are under DSP3 */ + if (port == TC956X_DSP3) + for_each_child_of_node_scoped(child, child1) { + ret = tc956x_pwrctrl_parse_device_dt(ctx, child1, port++); + if (ret) + break; + } + } + if (ret) { + dev_err(dev, "failed to parse device tree properties: %d\n", ret); + goto remove_i2c; + } + + if (!pcie_is_link_active(pci_dev) && bridge->ops->stop_link) + bridge->ops->stop_link(pci_dev->bus); + + ret = tc956x_pwrctrl_bring_up(ctx); + if (ret) + goto remove_i2c; + + if (!pcie_is_link_active(pci_dev) && bridge->ops->start_link) { + ret = bridge->ops->start_link(pci_dev->bus); + if (ret) + goto power_off; + } + + ret = devm_pci_pwrctrl_device_set_ready(dev, &ctx->pwrctrl); + if (ret) + goto power_off; + + platform_set_drvdata(pdev, ctx); + + return 0; + +power_off: + tc956x_pwrctrl_power_off(ctx); +remove_i2c: + i2c_unregister_device(ctx->client); + i2c_put_adapter(ctx->adapter); + return ret; +} + +static void tc956x_pwrctrl_remove(struct platform_device *pdev) +{ + struct tc956x_pwrctrl_ctx *ctx = platform_get_drvdata(pdev); + + tc956x_pwrctrl_power_off(ctx); + i2c_unregister_device(ctx->client); + i2c_put_adapter(ctx->adapter); +} + +static const struct of_device_id tc956x_pwrctrl_of_match[] = { + { .compatible = "pci1179,0623"}, + { } +}; +MODULE_DEVICE_TABLE(of, tc956x_pwrctrl_of_match); + +static struct platform_driver tc956x_pwrctrl_driver = { + .driver = { + .name = "pwrctrl-tc956x", + .of_match_table = tc956x_pwrctrl_of_match, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, + .probe = tc956x_pwrctrl_probe, + .remove = tc956x_pwrctrl_remove, +}; +module_platform_driver(tc956x_pwrctrl_driver); + +MODULE_AUTHOR("Krishna chaitanya chundru "); +MODULE_DESCRIPTION("TC956x power control driver"); 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a=ed25519-sha256; t=1740476062; l=2266; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=O6QdMw9pPsUSonExw1v1X4uasyeeZLrOu/yWsY9TlUk=; b=b1gIs1M9+w2uwq8aKEXnUyCHK9+vOyRbRv5s4qKcQEAZdCgZPuRWhO+GdKlQIBt9b/Bn2pEXT uruNXKmtI+CCHawO8jaBl+e3bTGGIRKv6bJTzcR/Oz3rUUio2gnzg1U X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: YGMJDT3blvHZy5Ow0kQpsfq3C9Ma8cR3 X-Proofpoint-ORIG-GUID: YGMJDT3blvHZy5Ow0kQpsfq3C9Ma8cR3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502250066 Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to handle PCIe link specific events such as Link up and Link down, which give the driver a chance to start bus enumeration on its own when link is up and initiate link training if link goes to a bad state. The PCIe driver can still work without this interrupt but it will provide a nice user experience when device gets plugged and removed. Hence, document it in the binding along with the existing MSI interrupts. Global interrupt is parsed as optional in driver, so adding it in bindings will not break the ABI. Signed-off-by: Krishna Chaitanya Chundru --- Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 76cb9fbfd476..7ae09ba8da60 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -54,7 +54,7 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: items: @@ -66,6 +66,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: maxItems: 1 @@ -149,9 +150,10 @@ examples: , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, From patchwork Tue Feb 25 09:34:07 2025 Content-Type: text/plain; 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a=ed25519-sha256; t=1740476062; l=1320; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=J9FPWpMy4pUYh48OOv9ER9vlynBjXbryZTb/XXp/SPY=; b=WOlWMX+kIeY2N8YTUwAYj0VddkFeHag0EknvUTM3VaxmVM236/nVGuRz/ImSIHtcCmYtacv/T +cR0HO8dFH7BLzzTFlAbRrRlSOW1jZI8utrAjX1hgYW4Mo2UkayZR+u X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: KnQqPZlBcmavpqE21sUl1UbusIc24iDT X-Proofpoint-ORIG-GUID: KnQqPZlBcmavpqE21sUl1UbusIc24iDT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=682 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502250066 Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPUs. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, add it to the PCIe RC node along with the existing MSI interrupts. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index b2e2b1f26731..6d71353592c9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2225,9 +2225,10 @@ pcie1: pcie@1c08000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,