From patchwork Tue Mar 19 15:52:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 10859895 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AA7FB1708 for ; Tue, 19 Mar 2019 15:54:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E16A2968A for ; Tue, 19 Mar 2019 15:54:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8C7A9296B0; Tue, 19 Mar 2019 15:54:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1C670297A0 for ; Tue, 19 Mar 2019 15:54:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727236AbfCSPyr (ORCPT ); Tue, 19 Mar 2019 11:54:47 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:62501 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726579AbfCSPyr (ORCPT ); Tue, 19 Mar 2019 11:54:47 -0400 X-IronPort-AV: E=Sophos;i="5.58,498,1544454000"; d="scan'208";a="10591164" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2019 00:54:45 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 609BF400F044; Wed, 20 Mar 2019 00:54:43 +0900 (JST) From: Gareth Williams To: Mark Brown , Rob Herring , Mark Rutland Cc: Phil Edworthy , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gareth Williams Subject: [PATCH v2 1/3] dt-bindings: snps,dw-apb-ssi: Add mandatory clock bindings documentation Date: Tue, 19 Mar 2019 15:52:05 +0000 Message-Id: <1553010727-23157-2-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553010727-23157-1-git-send-email-gareth.williams.jx@renesas.com> References: <1553010727-23157-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Phil Edworthy The Synopsys SSI driver uses a mandatory clock that is not documented, so detail it in the device tree bindings. Also correct the spelling of "pins" in the "Optional Properties" section for the driver. Signed-off-by: Phil Edworthy Signed-off-by: Gareth Williams --- v2: - Seperated spelling correction and mandatory clock documentation from the optional interface clock documentation commit. --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 2864bc6..bcd8f96 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -8,9 +8,10 @@ Required properties: - interrupts : One interrupt, used by the controller. - #address-cells : <1>, as required by generic SPI binding. - #size-cells : <0>, also as required by generic SPI binding. +- clocks : phandle for the core clock used to generate the external SPI clock. Optional properties: -- cs-gpios : Specifies the gpio pis to be used for chipselects. +- cs-gpios : Specifies the gpio pins to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. - reg-io-width : The I/O register width (in bytes) implemented by this device. Supported values are 2 or 4 (the default). @@ -25,6 +26,7 @@ Example: interrupts = <0 154 4>; #address-cells = <1>; #size-cells = <0>; + clocks = <&spi_m_clk>; num-cs = <2>; cs-gpios = <&gpio0 13 0>, <&gpio0 14 0>; From patchwork Tue Mar 19 15:52:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 10859897 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D73FF1390 for ; Tue, 19 Mar 2019 15:55:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BBE722906C for ; Tue, 19 Mar 2019 15:55:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AFFA42874E; Tue, 19 Mar 2019 15:55:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E65E29708 for ; Tue, 19 Mar 2019 15:55:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727018AbfCSPzA (ORCPT ); Tue, 19 Mar 2019 11:55:00 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:57627 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726579AbfCSPzA (ORCPT ); Tue, 19 Mar 2019 11:55:00 -0400 X-IronPort-AV: E=Sophos;i="5.58,498,1544454000"; d="scan'208";a="10591178" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2019 00:54:58 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id BCD86400F023; Wed, 20 Mar 2019 00:54:56 +0900 (JST) From: Gareth Williams To: Mark Brown , Rob Herring , Mark Rutland Cc: Gareth Williams , Phil Edworthy , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] dt-bindings: snps,dw-apb-ssi: Add optional clock bindings documentation Date: Tue, 19 Mar 2019 15:52:06 +0000 Message-Id: <1553010727-23157-3-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553010727-23157-1-git-send-email-gareth.williams.jx@renesas.com> References: <1553010727-23157-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add documentation to the Synopsys SPI dt-bindings to support an optional interface clock that may be used for register access. Signed-off-by: Phil Edworthy Signed-off-by: Gareth Williams --- v2: Created this separate patch to detail the optional interface clock property. This includes the clocks section on working with the two clocks and the clock-names line for pclk. --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index bcd8f96..f54c8c3 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -8,9 +8,15 @@ Required properties: - interrupts : One interrupt, used by the controller. - #address-cells : <1>, as required by generic SPI binding. - #size-cells : <0>, also as required by generic SPI binding. -- clocks : phandle for the core clock used to generate the external SPI clock. +- clocks : phandles for the clocks, see the description of clock-names below. + The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock + is optional. If a single clock is specified but no clock-name, it is the + "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first. Optional properties: +- clock-names : Contains the names of the clocks: + "ssi_clk", for the core clock used to generate the external SPI clock. + "pclk", the interface clock, required for register access. - cs-gpios : Specifies the gpio pins to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. - reg-io-width : The I/O register width (in bytes) implemented by this From patchwork Tue Mar 19 15:52:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 10859899 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A48B21390 for ; Tue, 19 Mar 2019 15:55:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 878FB2861E for ; Tue, 19 Mar 2019 15:55:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7BA12296B0; Tue, 19 Mar 2019 15:55:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 19DAB2861E for ; Tue, 19 Mar 2019 15:55:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726898AbfCSPzN (ORCPT ); Tue, 19 Mar 2019 11:55:13 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:55228 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726579AbfCSPzN (ORCPT ); Tue, 19 Mar 2019 11:55:13 -0400 X-IronPort-AV: E=Sophos;i="5.58,498,1544454000"; d="scan'208";a="10591201" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2019 00:55:11 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 596E5400F023; Wed, 20 Mar 2019 00:55:10 +0900 (JST) From: Gareth Williams To: Mark Brown Cc: Phil Edworthy , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Gareth Williams Subject: [PATCH v2 3/3] spi: dw: Add support for an optional interface clock Date: Tue, 19 Mar 2019 15:52:07 +0000 Message-Id: <1553010727-23157-4-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553010727-23157-1-git-send-email-gareth.williams.jx@renesas.com> References: <1553010727-23157-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Phil Edworthy The Synopsys SSI Controller has an interface clock, but most SoCs hide this away. However, on some SoCs you need to explicitly enable the interface clock in order to access the registers. Therefore, add support for an optional interface clock. Signed-off-by: Phil Edworthy Signed-off-by: Gareth Williams --- v2: - Added dependancy information to patch notes. - Expanded on optional clock comment for clarity Depends on commit 60b8f0ddf1a ("clk: Add (devm_)clk_get_optional() functions") --- drivers/spi/spi-dw-mmio.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 4bd59a9..de952b1 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -30,6 +30,7 @@ struct dw_spi_mmio { struct dw_spi dws; struct clk *clk; + struct clk *pclk; void *priv; }; @@ -172,6 +173,14 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) if (ret) return ret; + /* Optional clock needed to access the registers */ + dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk"); + if (IS_ERR(dwsmmio->pclk)) + return PTR_ERR(dwsmmio->pclk); + ret = clk_prepare_enable(dwsmmio->pclk); + if (ret) + goto out_clk; + dws->bus_num = pdev->id; dws->max_freq = clk_get_rate(dwsmmio->clk); @@ -199,6 +208,8 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) return 0; out: + clk_disable_unprepare(dwsmmio->pclk); +out_clk: clk_disable_unprepare(dwsmmio->clk); return ret; } @@ -208,6 +219,7 @@ static int dw_spi_mmio_remove(struct platform_device *pdev) struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev); dw_spi_remove_host(&dwsmmio->dws); + clk_disable_unprepare(dwsmmio->pclk); clk_disable_unprepare(dwsmmio->clk); return 0;