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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Leon Romanovsky , "Tariq Toukan" , , , , Shahar Shitrit , Carolina Jubran Subject: [PATCH net-next 1/6] net/mlx5: Relocate function declarations from port.h to mlx5_core.h Date: Wed, 26 Feb 2025 13:47:47 +0200 Message-ID: <20250226114752.104838-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250226114752.104838-1-tariqt@nvidia.com> References: <20250226114752.104838-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE8:EE_|MW4PR12MB7214:EE_ X-MS-Office365-Filtering-Correlation-Id: 35484375-2ef5-430a-dcb2-08dd565b854d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: Qd9pUrZgeiiy7iW68eUnCIGMCW/M+M3JyMn7uScrcdcUtQHA+idiz6++KzU/IMu9ckf4y3nsSgIRoKMmz7LJuZ3BlZAYstQfUUa5lLUeeAf4wYBbB+e+PUmlE8gyFCyl0EdccWayzF//FafVh5rA37DZHQKQw3dXZNoSnfF4Hc1ubvWsRiO4Rrt3g8nXS3r8/MZpW0EmDN47rZmy/6ZTRkx+V9BwatxEuOppdDTyzaxor63CeoBlp8H157C7JwhUkjXdyOEJnfSw4xMkqZBzsFJTvpk7j/dGjljmdCOIbEJ6MTRnXFgrzwqlOkqd2+Ul+pFlXmH16f8lqligd+KNWV37I07n97NkVJ7hA5tZ5z/yXn3H41oIqfiFvFVcM4in5H7XnkrGQGEjZK9PbbKvpyIrUF6Q5cV7Ny/DHyP+q4McilFDw4MHFNdFMRyzp7RlJFoTeeEMVjK+piKSbuctCovj1xK0rdsY9m8F40qwxeas0GmzPllS3MjrSSjKhugduQNr0xGGTypuqd+lr83huVXYeaeE46o76PYpVBBg8pq2LU4PqrON1iDTgKR5ywZVG0Nu+fT8lSI/EfGvvHf/LI4O6mMaGeYjt9LDM+CDpZqjB+rCcDhotBztk40QuAIwinMs6MT+BacMOO1+EhNc5T6ZzOgBf6GR4qzHRUxxY+UO4ayNDdZwrV6+sQ+T9iPrC9PDw+eYO88k7vkP9TGkjlTMB9+sNzBfvJ2MEr7rFh0umDPARws81Mp9KLzyQbruZXyX5On29OG894oJh2HaoY0n1nB8LNwbUyCEmJyjHtto5MEJLFJp+3d3T0u+m/A1y3rirqdne7B8Ac7nPQ3OwhEz3Es4c3mcfnW2gVuMHurl1hVf0Y8BjhEfuVFCPlbMX/mEVCbFUlcvmwJWm7cbCDgeUNbxbBqfLLYxSFvrXyV+KLkqOxe+dE/yNqLr6Wmm6KDxbN5SwxXY9FYxfhIXBklD/neBzHkobwdS6Jv8WkQWLvAND+jDP+rO2zDSxU9JNAd4gGSkKcVbZxK2cPnBJkSk+8MxdJmp9GRh5XLJ/eRPwU3dgphtHyZBwUAhEPamG/danr0SDipgAr7jo4FVjyk1huplwuA2WA0wTJeTT7GjEGm0vZjJlqS1ibXQtwpJcF0HIWvqO/W0Qz85EauzpBHpZ9ccGBzrQR4QKNQzBk9h5RLn+TZlOQZkd66Grip+a8BqmC1hChyL8jjDqq3yfjgQiCtZW94LAebm3Sln/TRNNrBtDOxVFhR0IjN24cUVLaICUa1uqGVGqBt2eUs0fB1gBW1zhjwgbVkTE6Z4iYFJlBWF9LBC3d3mD/ojaLhRtQWE2u9GajnTzffOwOd4aEQy5mt8JL1JULDK4Ng7vHlxt52PNy4KhRCvZscYxEVkWzh8OwugravVLUetYdvbu9Sp2dDbsOHsw8XOORYbUQIiesnjnlKsUoXfYbN5xJYSM93Y4HDgriBPWKTwK6hyxFPFzfmcJix9J8IilQZlXsI= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 11:48:43.3869 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35484375-2ef5-430a-dcb2-08dd565b854d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7214 X-Patchwork-Delegate: kuba@kernel.org From: Shahar Shitrit The port header is a general file under include, yet it contains declarations for functions that are either not exported or exported but not used outside the mlx5_core driver. To enhance code organization, we move these declarations to mlx5_core.h, where they are more appropriately scoped. This refactor removes unnecessary exported symbols and prevents unexported functions from being inadvertently referenced outside of the mlx5_core driver. Signed-off-by: Shahar Shitrit Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/mlx5_core.h | 85 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/port.c | 20 ----- include/linux/mlx5/port.h | 85 +------------------ 3 files changed, 86 insertions(+), 104 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index 6fef1005c469..6278b02105da 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -114,6 +114,21 @@ struct mlx5_cmd_alias_obj_create_attr { u8 access_key[ACCESS_KEY_LEN]; }; +struct mlx5_port_eth_proto { + u32 cap; + u32 admin; + u32 oper; +}; + +struct mlx5_module_eeprom_query_params { + u16 size; + u16 offset; + u16 i2c_address; + u32 page; + u32 bank; + u32 module_number; +}; + static inline void mlx5_printk(struct mlx5_core_dev *dev, int level, const char *format, ...) { struct device *device = dev->device; @@ -280,6 +295,76 @@ int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode); struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev); void mlx5_dm_cleanup(struct mlx5_core_dev *dev); +void mlx5_toggle_port_link(struct mlx5_core_dev *dev); +int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, + enum mlx5_port_status status); +int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, + enum mlx5_port_status *status); +int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration); + +int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port); +int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause); +int mlx5_query_port_pause(struct mlx5_core_dev *dev, + u32 *rx_pause, u32 *tx_pause); + +int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx); +int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, + u8 *pfc_en_rx); + +int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev, + u16 stall_critical_watermark, + u16 stall_minor_watermark); +int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev, + u16 *stall_critical_watermark, + u16 *stall_minor_watermark); + +int mlx5_max_tc(struct mlx5_core_dev *mdev); +int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc); +int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, + u8 prio, u8 *tc); +int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group); +int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, + u8 tc, u8 *tc_group); +int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw); +int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, + u8 tc, u8 *bw_pct); +int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, + u8 *max_bw_value, + u8 *max_bw_unit); +int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, + u8 *max_bw_value, + u8 *max_bw_unit); +int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode); +int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode); + +int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen); +int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen); +int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable); +void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, + bool *enabled); +int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, + u16 offset, u16 size, u8 *data); +int +mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, + struct mlx5_module_eeprom_query_params *params, + u8 *data); + +int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out); +int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in); +int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state); +int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state); +int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio); +int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio); + +int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, + struct mlx5_port_eth_proto *eproto); +bool mlx5_ptys_ext_supported(struct mlx5_core_dev *mdev); +u32 mlx5_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper, + bool force_legacy); +u32 mlx5_port_speed2linkmodes(struct mlx5_core_dev *mdev, u32 speed, + bool force_legacy); +int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); + #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \ MLX5_CAP_GEN((mdev), pps_modify) && \ MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c index 3995df064101..c7d749e8e133 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -196,7 +196,6 @@ void mlx5_toggle_port_link(struct mlx5_core_dev *dev) if (ps == MLX5_PORT_UP) mlx5_set_port_admin_status(dev, MLX5_PORT_UP); } -EXPORT_SYMBOL_GPL(mlx5_toggle_port_link); int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, enum mlx5_port_status status) @@ -210,7 +209,6 @@ int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_PAOS, 0, 1); } -EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status); int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, enum mlx5_port_status *status) @@ -227,7 +225,6 @@ int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, *status = MLX5_GET(paos_reg, out, admin_status); return 0; } -EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status); static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu, u16 *max_mtu, u16 *oper_mtu, u8 port) @@ -257,7 +254,6 @@ int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port) return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_PMTU, 0, 1); } -EXPORT_SYMBOL_GPL(mlx5_set_port_mtu); void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port) @@ -447,7 +443,6 @@ int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, return mlx5_query_mcia(dev, &query, data); } -EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom); int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, struct mlx5_module_eeprom_query_params *params, @@ -467,7 +462,6 @@ int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, return mlx5_query_mcia(dev, params, data); } -EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom_by_page); static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc, int pvlc_size, u8 local_port) @@ -518,7 +512,6 @@ int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause) return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_PFCC, 0, 1); } -EXPORT_SYMBOL_GPL(mlx5_set_port_pause); int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 *rx_pause, u32 *tx_pause) @@ -538,7 +531,6 @@ int mlx5_query_port_pause(struct mlx5_core_dev *dev, return 0; } -EXPORT_SYMBOL_GPL(mlx5_query_port_pause); int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev, u16 stall_critical_watermark, @@ -597,7 +589,6 @@ int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx) return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_PFCC, 0, 1); } -EXPORT_SYMBOL_GPL(mlx5_set_port_pfc); int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx) { @@ -616,7 +607,6 @@ int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx) return 0; } -EXPORT_SYMBOL_GPL(mlx5_query_port_pfc); int mlx5_max_tc(struct mlx5_core_dev *mdev) { @@ -667,7 +657,6 @@ int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc) return 0; } -EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc); int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, u8 prio, u8 *tc) @@ -689,7 +678,6 @@ int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, return err; } -EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc); static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in, int inlen) @@ -728,7 +716,6 @@ int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group) return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in)); } -EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group); int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, u8 tc, u8 *tc_group) @@ -749,7 +736,6 @@ int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, return 0; } -EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group); int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw) { @@ -763,7 +749,6 @@ int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw) return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in)); } -EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc); int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 tc, u8 *bw_pct) @@ -784,7 +769,6 @@ int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, return 0; } -EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc); int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, u8 *max_bw_value, @@ -808,7 +792,6 @@ int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in)); } -EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit); int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, u8 *max_bw_value, @@ -834,7 +817,6 @@ int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, return 0; } -EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit); int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode) { @@ -845,7 +827,6 @@ int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode) MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode); return mlx5_cmd_exec_in(mdev, set_wol_rol, in); } -EXPORT_SYMBOL_GPL(mlx5_set_port_wol); int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode) { @@ -860,7 +841,6 @@ int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode) return err; } -EXPORT_SYMBOL_GPL(mlx5_query_port_wol); int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen) { diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h index fd625e0dd869..58770b86f793 100644 --- a/include/linux/mlx5/port.h +++ b/include/linux/mlx5/port.h @@ -61,15 +61,6 @@ enum mlx5_an_status { #define MLX5_EEPROM_PAGE_LENGTH 256 #define MLX5_EEPROM_HIGH_PAGE_LENGTH 128 -struct mlx5_module_eeprom_query_params { - u16 size; - u16 offset; - u16 i2c_address; - u32 page; - u32 bank; - u32 module_number; -}; - enum mlx5e_link_mode { MLX5E_1000BASE_CX_SGMII = 0, MLX5E_1000BASE_KX = 1, @@ -145,12 +136,6 @@ enum mlx5_ptys_width { MLX5_PTYS_WIDTH_12X = 1 << 4, }; -struct mlx5_port_eth_proto { - u32 cap; - u32 admin; - u32 oper; -}; - #define MLX5E_PROT_MASK(link_mode) (1U << link_mode) #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \ (ext ? MLX5_GET(reg, out, ext_##field) : \ @@ -163,14 +148,7 @@ int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper, u16 *proto_oper, u8 local_port, u8 plane_index); -void mlx5_toggle_port_link(struct mlx5_core_dev *dev); -int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, - enum mlx5_port_status status); -int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, - enum mlx5_port_status *status); -int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration); - -int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port); + void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port); void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu, u8 port); @@ -178,65 +156,4 @@ void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu, int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, u8 *vl_hw_cap, u8 local_port); -int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause); -int mlx5_query_port_pause(struct mlx5_core_dev *dev, - u32 *rx_pause, u32 *tx_pause); - -int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx); -int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, - u8 *pfc_en_rx); - -int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev, - u16 stall_critical_watermark, - u16 stall_minor_watermark); -int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev, - u16 *stall_critical_watermark, u16 *stall_minor_watermark); - -int mlx5_max_tc(struct mlx5_core_dev *mdev); - -int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc); -int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, - u8 prio, u8 *tc); -int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group); -int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, - u8 tc, u8 *tc_group); -int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw); -int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, - u8 tc, u8 *bw_pct); -int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, - u8 *max_bw_value, - u8 *max_bw_unit); -int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, - u8 *max_bw_value, - u8 *max_bw_unit); -int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode); -int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode); - -int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen); -int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen); -int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable); -void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, - bool *enabled); -int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, - u16 offset, u16 size, u8 *data); -int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, - struct mlx5_module_eeprom_query_params *params, u8 *data); - -int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out); -int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Leon Romanovsky , "Tariq Toukan" , , , , Shahar Shitrit , Carolina Jubran Subject: [PATCH net-next 2/6] net/mlx5: Refactor link speed handling with mlx5_link_info struct Date: Wed, 26 Feb 2025 13:47:48 +0200 Message-ID: <20250226114752.104838-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250226114752.104838-1-tariqt@nvidia.com> References: <20250226114752.104838-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE4:EE_|DM4PR12MB7695:EE_ X-MS-Office365-Filtering-Correlation-Id: 414f1dcc-d7a4-482b-eecc-08dd565b8972 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: 4PSFDqW+utv9pWLuwLQsmivGnLNg/1qTvJCCwQDXGJkA3X5Dq5r9ksHXH0G+g2X6fG5sWPqsHwvRyEwCtud2XiUTsaylqrUU2qyjKr3n15rOaMwKL1LsonMVz1oQW07M1vPYNrElpAZDidnEWdmPwK06EmidvG4D/HZ8T2SIZERDfumdIQFvyHUghzI904lTfHnNQAA7pSfon9ZF9wCxfHUcHB1z7u3RnsOMitLz8L9DiLJC6kaHPxKWoqkOLR965SrEEYfUqwQKGEGiza+P9mNDlgigeqq616q1aTZ08/cautKR31RXjglhH1AtzeZQ/ApkTKroVIVrfDj93jbglUxSERb3lRk5rVHrpVfxgoIonVpGqVLjDpDY1ei2yoYPVLWuTaAiHyqVM7oR7+v3zLe0WKOU7zWTzslxVggFxqSJIJFmVPYw0aiT8kCfOKScJ8lia2gDllEMWKTQ3l5qk3JB0EC48FsntasjbCCPk7T/UkQyVr6O8A91FjPKCjPSzmIPb6T8dv+w3iNJ3n8zcRMBveIisvb9nq4j3lwIXxZMuxHUJlo5ltGAcgv7aXEkrvQaXxHjmYLZikd4Q/rmnhwgHbVZIbHVOdj+w0pkuwNSVXPOVYVx0VTzIo5XZU8UDPBH/T1VPIznjy3vbfOzjDaBTi44YnkOeQpuFO27Rvb1QTPzJAU16X6zuZviRiJdubxHZxtuXRNGMERZLX9Q2hB3BcH+x9FZTH9AizmpZBzO/3NEO4ZgsxllrDTAXsnloYh+4NqhwABX1m0ZZeR0dC/+LZvTOxNUCqLjYp8Ih5SxAnBh9VU64kx3Y+AjT+Y9MGfNF/VxyY5McQQ3MNVQW2Lpdy8NwaxMz4Pvaxn07hygN++GjoPdEAjcAdzIfxwWOAdC04GLY54LAWLefzNpeUYndYxVd9jcLPTeni92CfGewm1TUx5dLRJTkwZn3lOzp5lZ3uYXu+qKIVX/enUkigrS4fc4AlEi+UHhtF75L8jvZb5/O06BwtvBdjl9RhriXWsqTYQ4gdMjRofQNRqcnxXyLmvtc7WKULCNBtsuAvAshRdcJM2yGNdC0aHgYvfBUTQG5hMZjrs3vaQqYmvtCiPj/qnzIRaRG9zjkLpmvf6+3HZA0MSFlRzl71jFkz+GfrnOVJ+4c4QV1yaFJUfrcd57nsUK5g8KzU2L3+uFdb4U977waEO2vXgSCzBMOJP4HSgEbS4ojCIi/E5or5EqZRlj/noxZqKMPRA7+agUos+qU38SRrntcMdaM8CCAmciD+NCxZESTRIOFt0yMwoJxer5vhBKtg2qIkBKSulVEAnlM+0rFlZHx4D3nhXiP2Xe8EagGwdiQwYS7PzJ6xzGqSYArttF6BTUZTSsMwLFfshOWkR1tDH1k0P7RwVea8pSCnaTsyKPNk0SFruCNggK57AcFu0lVlUtkUpOfH8lECAMRmnGu6zTKzcTL/GC8h7OE9gJyUE9xTv8pr8L+fZ9C5YDt43ySB6DIXrT3+IQOcw= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 11:48:50.3408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 414f1dcc-d7a4-482b-eecc-08dd565b8972 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7695 X-Patchwork-Delegate: kuba@kernel.org From: Shahar Shitrit Introduce struct mlx5_link_info with a speed field and change the types of mlx5e_link_speed and mlx5e_ext_link_speed from arrays of u32 to arrays of struct mlx5_link_info. These arrays are renamed to mlx5e_link_info and mlx5e_ext_link_info, respectively. This change prepares for a future patch that will introduce a lanes field in struct mlx5_link_info and add lanes mapping alongside the speed for each link mode in the two arrays. Additionally, rename function mlx5_port_speed2linkmodes() to mlx5_port_info2linkmodes() and function mlx5_port_ptys2speed() to mlx5_port_ptys2info() and update the speed parameter/return type to struct mlx5_link_info, in preparation for the upcoming patch where these functions will also utilize the lanes field. Signed-off-by: Shahar Shitrit Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/port.c | 9 +- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 24 ++- .../ethernet/mellanox/mlx5/core/mlx5_core.h | 14 +- .../net/ethernet/mellanox/mlx5/core/port.c | 144 +++++++++--------- 4 files changed, 103 insertions(+), 88 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c index f62fbfb67a1b..6049ccf475bc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c @@ -80,6 +80,7 @@ int mlx5_port_set_eth_ptys(struct mlx5_core_dev *dev, bool an_disable, int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed) { struct mlx5_port_eth_proto eproto; + const struct mlx5_link_info *info; bool force_legacy = false; bool ext; int err; @@ -94,9 +95,13 @@ int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed) if (err) goto out; } - *speed = mlx5_port_ptys2speed(mdev, eproto.oper, force_legacy); - if (!(*speed)) + info = mlx5_port_ptys2info(mdev, eproto.oper, force_legacy); + if (!info) { + *speed = SPEED_UNKNOWN; err = -EINVAL; + goto out; + } + *speed = info->speed; out: return err; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 0cb515fa179f..9a1b1564228b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -1082,23 +1082,21 @@ static void get_speed_duplex(struct net_device *netdev, struct ethtool_link_ksettings *link_ksettings) { struct mlx5e_priv *priv = netdev_priv(netdev); - u32 speed = SPEED_UNKNOWN; + const struct mlx5_link_info *info; u8 duplex = DUPLEX_UNKNOWN; + u32 speed = SPEED_UNKNOWN; if (!netif_carrier_ok(netdev)) goto out; - speed = mlx5_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy); - if (!speed) { - if (data_rate_oper) - speed = 100 * data_rate_oper; - else - speed = SPEED_UNKNOWN; - goto out; + info = mlx5_port_ptys2info(priv->mdev, eth_proto_oper, force_legacy); + if (info) { + speed = info->speed; + duplex = DUPLEX_FULL; + } else if (data_rate_oper) { + speed = 100 * data_rate_oper; } - duplex = DUPLEX_FULL; - out: link_ksettings->base.speed = speed; link_ksettings->base.duplex = duplex; @@ -1349,6 +1347,7 @@ static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, { struct mlx5_core_dev *mdev = priv->mdev; struct mlx5_port_eth_proto eproto; + struct mlx5_link_info info = {}; const unsigned long *adver; bool an_changes = false; u8 an_disable_admin; @@ -1359,7 +1358,6 @@ static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, u32 link_modes; u8 an_status; u8 autoneg; - u32 speed; bool ext; int err; @@ -1367,7 +1365,7 @@ static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, adver = link_ksettings->link_modes.advertising; autoneg = link_ksettings->base.autoneg; - speed = link_ksettings->base.speed; + info.speed = link_ksettings->base.speed; ext_supported = mlx5_ptys_ext_supported(mdev); ext_requested = ext_link_mode_requested(adver); @@ -1384,7 +1382,7 @@ static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, goto out; } link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) : - mlx5_port_speed2linkmodes(mdev, speed, !ext); + mlx5_port_info2linkmodes(mdev, &info, !ext); err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg); if (err) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index 6278b02105da..9639e44f71ed 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -129,6 +129,10 @@ struct mlx5_module_eeprom_query_params { u32 module_number; }; +struct mlx5_link_info { + u32 speed; +}; + static inline void mlx5_printk(struct mlx5_core_dev *dev, int level, const char *format, ...) { struct device *device = dev->device; @@ -359,10 +363,12 @@ int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio); int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, struct mlx5_port_eth_proto *eproto); bool mlx5_ptys_ext_supported(struct mlx5_core_dev *mdev); -u32 mlx5_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper, - bool force_legacy); -u32 mlx5_port_speed2linkmodes(struct mlx5_core_dev *mdev, u32 speed, - bool force_legacy); +const struct mlx5_link_info *mlx5_port_ptys2info(struct mlx5_core_dev *mdev, + u32 eth_proto_oper, + bool force_legacy); +u32 mlx5_port_info2linkmodes(struct mlx5_core_dev *mdev, + struct mlx5_link_info *info, + bool force_legacy); int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c index c7d749e8e133..e1b69416f391 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -1038,56 +1038,57 @@ int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio) } /* speed in units of 1Mb */ -static const u32 mlx5e_link_speed[MLX5E_LINK_MODES_NUMBER] = { - [MLX5E_1000BASE_CX_SGMII] = 1000, - [MLX5E_1000BASE_KX] = 1000, - [MLX5E_10GBASE_CX4] = 10000, - [MLX5E_10GBASE_KX4] = 10000, - [MLX5E_10GBASE_KR] = 10000, - [MLX5E_20GBASE_KR2] = 20000, - [MLX5E_40GBASE_CR4] = 40000, - [MLX5E_40GBASE_KR4] = 40000, - [MLX5E_56GBASE_R4] = 56000, - [MLX5E_10GBASE_CR] = 10000, - [MLX5E_10GBASE_SR] = 10000, - [MLX5E_10GBASE_ER] = 10000, - [MLX5E_40GBASE_SR4] = 40000, - [MLX5E_40GBASE_LR4] = 40000, - [MLX5E_50GBASE_SR2] = 50000, - [MLX5E_100GBASE_CR4] = 100000, - [MLX5E_100GBASE_SR4] = 100000, - [MLX5E_100GBASE_KR4] = 100000, - [MLX5E_100GBASE_LR4] = 100000, - [MLX5E_100BASE_TX] = 100, - [MLX5E_1000BASE_T] = 1000, - [MLX5E_10GBASE_T] = 10000, - [MLX5E_25GBASE_CR] = 25000, - [MLX5E_25GBASE_KR] = 25000, - [MLX5E_25GBASE_SR] = 25000, - [MLX5E_50GBASE_CR2] = 50000, - [MLX5E_50GBASE_KR2] = 50000, +static const struct mlx5_link_info mlx5e_link_info[MLX5E_LINK_MODES_NUMBER] = { + [MLX5E_1000BASE_CX_SGMII] = {.speed = 1000}, + [MLX5E_1000BASE_KX] = {.speed = 1000}, + [MLX5E_10GBASE_CX4] = {.speed = 10000}, + [MLX5E_10GBASE_KX4] = {.speed = 10000}, + [MLX5E_10GBASE_KR] = {.speed = 10000}, + [MLX5E_20GBASE_KR2] = {.speed = 20000}, + [MLX5E_40GBASE_CR4] = {.speed = 40000}, + [MLX5E_40GBASE_KR4] = {.speed = 40000}, + [MLX5E_56GBASE_R4] = {.speed = 56000}, + [MLX5E_10GBASE_CR] = {.speed = 10000}, + [MLX5E_10GBASE_SR] = {.speed = 10000}, + [MLX5E_10GBASE_ER] = {.speed = 10000}, + [MLX5E_40GBASE_SR4] = {.speed = 40000}, + [MLX5E_40GBASE_LR4] = {.speed = 40000}, + [MLX5E_50GBASE_SR2] = {.speed = 50000}, + [MLX5E_100GBASE_CR4] = {.speed = 100000}, + [MLX5E_100GBASE_SR4] = {.speed = 100000}, + [MLX5E_100GBASE_KR4] = {.speed = 100000}, + [MLX5E_100GBASE_LR4] = {.speed = 100000}, + [MLX5E_100BASE_TX] = {.speed = 100}, + [MLX5E_1000BASE_T] = {.speed = 1000}, + [MLX5E_10GBASE_T] = {.speed = 10000}, + [MLX5E_25GBASE_CR] = {.speed = 25000}, + [MLX5E_25GBASE_KR] = {.speed = 25000}, + [MLX5E_25GBASE_SR] = {.speed = 25000}, + [MLX5E_50GBASE_CR2] = {.speed = 50000}, + [MLX5E_50GBASE_KR2] = {.speed = 50000}, }; -static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = { - [MLX5E_SGMII_100M] = 100, - [MLX5E_1000BASE_X_SGMII] = 1000, - [MLX5E_5GBASE_R] = 5000, - [MLX5E_10GBASE_XFI_XAUI_1] = 10000, - [MLX5E_40GBASE_XLAUI_4_XLPPI_4] = 40000, - [MLX5E_25GAUI_1_25GBASE_CR_KR] = 25000, - [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2] = 50000, - [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR] = 50000, - [MLX5E_CAUI_4_100GBASE_CR4_KR4] = 100000, - [MLX5E_100GAUI_2_100GBASE_CR2_KR2] = 100000, - [MLX5E_200GAUI_4_200GBASE_CR4_KR4] = 200000, - [MLX5E_400GAUI_8_400GBASE_CR8] = 400000, - [MLX5E_100GAUI_1_100GBASE_CR_KR] = 100000, - [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = 200000, - [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = 400000, - [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = 800000, - [MLX5E_200GAUI_1_200GBASE_CR1_KR1] = 200000, - [MLX5E_400GAUI_2_400GBASE_CR2_KR2] = 400000, - [MLX5E_800GAUI_4_800GBASE_CR4_KR4] = 800000, +static const struct mlx5_link_info +mlx5e_ext_link_info[MLX5E_EXT_LINK_MODES_NUMBER] = { + [MLX5E_SGMII_100M] = {.speed = 100}, + [MLX5E_1000BASE_X_SGMII] = {.speed = 1000}, + [MLX5E_5GBASE_R] = {.speed = 5000}, + [MLX5E_10GBASE_XFI_XAUI_1] = {.speed = 10000}, + [MLX5E_40GBASE_XLAUI_4_XLPPI_4] = {.speed = 40000}, + [MLX5E_25GAUI_1_25GBASE_CR_KR] = {.speed = 25000}, + [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2] = {.speed = 50000}, + [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR] = {.speed = 50000}, + [MLX5E_CAUI_4_100GBASE_CR4_KR4] = {.speed = 100000}, + [MLX5E_100GAUI_2_100GBASE_CR2_KR2] = {.speed = 100000}, + [MLX5E_200GAUI_4_200GBASE_CR4_KR4] = {.speed = 200000}, + [MLX5E_400GAUI_8_400GBASE_CR8] = {.speed = 400000}, + [MLX5E_100GAUI_1_100GBASE_CR_KR] = {.speed = 100000}, + [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = {.speed = 200000}, + [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = {.speed = 400000}, + [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = {.speed = 800000}, + [MLX5E_200GAUI_1_200GBASE_CR1_KR1] = {.speed = 200000}, + [MLX5E_400GAUI_2_400GBASE_CR2_KR2] = {.speed = 400000}, + [MLX5E_800GAUI_4_800GBASE_CR4_KR4] = {.speed = 800000}, }; int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, @@ -1125,44 +1126,49 @@ bool mlx5_ptys_ext_supported(struct mlx5_core_dev *mdev) return !!eproto.cap; } -static void mlx5e_port_get_speed_arr(struct mlx5_core_dev *mdev, - const u32 **arr, u32 *size, - bool force_legacy) +static void mlx5e_port_get_link_mode_info_arr(struct mlx5_core_dev *mdev, + const struct mlx5_link_info **arr, + u32 *size, + bool force_legacy) { bool ext = force_legacy ? false : mlx5_ptys_ext_supported(mdev); - *size = ext ? ARRAY_SIZE(mlx5e_ext_link_speed) : - ARRAY_SIZE(mlx5e_link_speed); - *arr = ext ? mlx5e_ext_link_speed : mlx5e_link_speed; + *size = ext ? ARRAY_SIZE(mlx5e_ext_link_info) : + ARRAY_SIZE(mlx5e_link_info); + *arr = ext ? mlx5e_ext_link_info : mlx5e_link_info; } -u32 mlx5_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper, - bool force_legacy) +const struct mlx5_link_info *mlx5_port_ptys2info(struct mlx5_core_dev *mdev, + u32 eth_proto_oper, + bool force_legacy) { unsigned long temp = eth_proto_oper; - const u32 *table; - u32 speed = 0; + const struct mlx5_link_info *table; u32 max_size; int i; - mlx5e_port_get_speed_arr(mdev, &table, &max_size, force_legacy); + mlx5e_port_get_link_mode_info_arr(mdev, &table, &max_size, + force_legacy); i = find_first_bit(&temp, max_size); if (i < max_size) - speed = table[i]; - return speed; + return &table[i]; + + return NULL; } -u32 mlx5_port_speed2linkmodes(struct mlx5_core_dev *mdev, u32 speed, - bool force_legacy) +u32 mlx5_port_info2linkmodes(struct mlx5_core_dev *mdev, + struct mlx5_link_info *info, + bool force_legacy) { + const struct mlx5_link_info *table; u32 link_modes = 0; - const u32 *table; u32 max_size; int i; - mlx5e_port_get_speed_arr(mdev, &table, &max_size, force_legacy); + mlx5e_port_get_link_mode_info_arr(mdev, &table, &max_size, + force_legacy); for (i = 0; i < max_size; ++i) { - if (table[i] == speed) + if (table[i].speed == info->speed) link_modes |= MLX5E_PROT_MASK(i); } return link_modes; @@ -1170,9 +1176,9 @@ u32 mlx5_port_speed2linkmodes(struct mlx5_core_dev *mdev, u32 speed, int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed) { + const struct mlx5_link_info *table; struct mlx5_port_eth_proto eproto; u32 max_speed = 0; - const u32 *table; u32 max_size; bool ext; int err; @@ -1183,10 +1189,10 @@ int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed) if (err) return err; - mlx5e_port_get_speed_arr(mdev, &table, &max_size, false); + mlx5e_port_get_link_mode_info_arr(mdev, &table, &max_size, false); for (i = 0; i < max_size; ++i) if (eproto.cap & MLX5E_PROT_MASK(i)) - max_speed = max(max_speed, table[i]); + max_speed = max(max_speed, table[i].speed); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Leon Romanovsky , "Tariq Toukan" , , , , Shahar Shitrit , Carolina Jubran Subject: [PATCH net-next 3/6] net/mlx5e: Enable lanes configuration when auto-negotiation is off Date: Wed, 26 Feb 2025 13:47:49 +0200 Message-ID: <20250226114752.104838-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250226114752.104838-1-tariqt@nvidia.com> References: <20250226114752.104838-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C9:EE_|CH3PR12MB9219:EE_ X-MS-Office365-Filtering-Correlation-Id: 0cf614cc-6b99-41a1-9650-08dd565b85b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: 6+zOgjbzkFA69LA8eOWIsJLaXRbiMbsnL98yyRd9JlK7nwyGe+kl33rfe/sOAiSeN8nyx5eXtRzAJv6jueX6j3cxc/eXOk/QGjAAU5ufdMAGqQ+sjAkCq6zEhLu2Nr2QV6UwN41l8jOEO/2zcKr+052vfDkuVYujU7eX/MNcrLJZ7Be1j6EPPZFU9rV1MwGxBIkl+dWuZT4kZWd0FV4PERM5BUveVyylMtmWvtUINyNP/8XL0dIrrITYcOv1sdGVrWf9EgMt2et77B95xjkUu9JjEF9/MSplZlJyU00tKjNY2QWPFjsqTnPVs9LPysVWry6Zn0JNXcW+RSRXipMdejhGis0TyMwEsAmnUtgBsqNLCQM+Es0pURwF4GugxwPqWpUrPu9VerS26517OJri0Rbaw2BOmBthwbahEdZrDjuYSbz6c1/PHjYkmkZvwHRqhD8g9y1QdaP9gttGGBFSIqtuNocYoqTO80gR+v49r68pNU9taB3eYf+P41c+P8ZrlFYPx88vn6b9ElVnWstqibAP3sAAwYzvEnDsUpAuC4IfcFgPiE80gg996ZEYt6lzBRkChJv6R2l9CB52+Z+LHADbbupu2kBwIQJz5lb5s0ynWl/yPK3ZhPgF8ZAORJrHCy5El9K3ISS1ljeVF8v0Rskeud+/n2lzT7tSLHSuAzKm1WuAbX6dnxx4Qktb2JDZO7PodsgS34p5pzL7eKLFd17VGxTyDvQ3yMwRfu1UERi0SkQtqBxzgoEaPilPK/KS2XUx4RS11lNaXR1qM/Ve1JbkFdyQj7YqagmrFV8E+f+0zY9D0BfU87ovDdmDAuBogLo1rOmNPHiOXCruoppd4spsBwggIPCLJtwPRn1cD+jD8cGyi451IBejskLT0SqZIW2kQNRGRTtXfhyRWkJT5DPDcvQmjs54smMt3eu/RsZklT+wIS4JTVrGjFVBKXrXaOCN+aNCjX6iiSTqls9M3cr6GK3hFOjYygFr2Ur2w1PNn3GB+JvJ5nXlh0ePVAMCroFtMii86OSjyMt/e3O9rGr+bTu5GSpRmhjgZwZFE6Wwe2UlEJ2pjSFm6u7Iz7tRfr2GeRJqJ/LAiDH5Ax1es1muDOltPaY/WXyNDsK9rQSnVnqMLqY6+SDqkr3ZLoHFLcIC6f9WfKTckD2ON9TZCm/qMlveSPpQniB0SLGHqmVKfWqYCaAI+FqoaFZasuJ1/5y1X5RePC4HIaa16xwh0X0puRpnDKKaDs0H8/ARyYckx4F7Z69NkFkey/GN4pwwucIf/6j6sC/fBsBJv5cPtWXTSsDbXQU2D7UJzrMLJacut3A6Z44W+Vb6JvINworZ870nLG9feI/8XjKC7Fdqo8J7L9yWlisaWvFDjxr+M+dZjvPBd9fRiWUWb1IGPZV/aR5qHtcfcmQaKbmfuSwpHMqtQqE1SS00foLyT/jw0SsXlfory3iUGUKZebLcKf/KUMyy3tZRkkWMEDUYrJm+hX2pvT9G5afGDuO+k2QVMG0= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 11:48:44.0420 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0cf614cc-6b99-41a1-9650-08dd565b85b6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9219 X-Patchwork-Delegate: kuba@kernel.org From: Shahar Shitrit Currently, when auto-negotiation is disabled, the driver retrieves the speed and converts it into all link modes that correspond to that speed. With this patch, we add the ability to set the number of lanes, so that the combination of speed and lanes corresponds to exactly one specific link mode for the extended bit map. For the legacy bit map the driver sets all link modes correspond to speed and lanes. This change provides users with the option to set a specific link mode, rather than enabling all link modes associated with a given speed when auto-negotiation is off. Signed-off-by: Shahar Shitrit Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 20 ++-- .../ethernet/mellanox/mlx5/core/mlx5_core.h | 1 + .../net/ethernet/mellanox/mlx5/core/port.c | 98 ++++++++++--------- include/uapi/linux/ethtool.h | 2 + 4 files changed, 66 insertions(+), 55 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 9a1b1564228b..77aa971a00ae 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -1076,15 +1076,16 @@ static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev, } } -static void get_speed_duplex(struct net_device *netdev, - u32 eth_proto_oper, bool force_legacy, - u16 data_rate_oper, - struct ethtool_link_ksettings *link_ksettings) +static void get_link_properties(struct net_device *netdev, + u32 eth_proto_oper, bool force_legacy, + u16 data_rate_oper, + struct ethtool_link_ksettings *link_ksettings) { struct mlx5e_priv *priv = netdev_priv(netdev); const struct mlx5_link_info *info; u8 duplex = DUPLEX_UNKNOWN; u32 speed = SPEED_UNKNOWN; + u32 lanes = LANES_UNKNOWN; if (!netif_carrier_ok(netdev)) goto out; @@ -1092,14 +1093,17 @@ static void get_speed_duplex(struct net_device *netdev, info = mlx5_port_ptys2info(priv->mdev, eth_proto_oper, force_legacy); if (info) { speed = info->speed; + lanes = info->lanes; duplex = DUPLEX_FULL; } else if (data_rate_oper) { speed = 100 * data_rate_oper; + lanes = MAX_LANES; } out: - link_ksettings->base.speed = speed; link_ksettings->base.duplex = duplex; + link_ksettings->base.speed = speed; + link_ksettings->lanes = lanes; } static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap, @@ -1236,8 +1240,8 @@ static int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, get_supported(mdev, eth_proto_cap, link_ksettings); get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings, admin_ext); - get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext, - data_rate_oper, link_ksettings); + get_link_properties(priv->netdev, eth_proto_oper, !admin_ext, + data_rate_oper, link_ksettings); eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap; connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ? @@ -1366,6 +1370,7 @@ static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, adver = link_ksettings->link_modes.advertising; autoneg = link_ksettings->base.autoneg; info.speed = link_ksettings->base.speed; + info.lanes = link_ksettings->lanes; ext_supported = mlx5_ptys_ext_supported(mdev); ext_requested = ext_link_mode_requested(adver); @@ -2613,6 +2618,7 @@ static void mlx5e_get_ts_stats(struct net_device *netdev, } const struct ethtool_ops mlx5e_ethtool_ops = { + .cap_link_lanes_supported = true, .cap_rss_ctx_supported = true, .rxfh_per_ctx_key = true, .supported_coalesce_params = ETHTOOL_COALESCE_USECS | diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index 9639e44f71ed..2e02bdea8361 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -131,6 +131,7 @@ struct mlx5_module_eeprom_query_params { struct mlx5_link_info { u32 speed; + u32 lanes; }; static inline void mlx5_printk(struct mlx5_core_dev *dev, int level, const char *format, ...) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c index e1b69416f391..549f1066d2a5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -1039,56 +1039,56 @@ int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio) /* speed in units of 1Mb */ static const struct mlx5_link_info mlx5e_link_info[MLX5E_LINK_MODES_NUMBER] = { - [MLX5E_1000BASE_CX_SGMII] = {.speed = 1000}, - [MLX5E_1000BASE_KX] = {.speed = 1000}, - [MLX5E_10GBASE_CX4] = {.speed = 10000}, - [MLX5E_10GBASE_KX4] = {.speed = 10000}, - [MLX5E_10GBASE_KR] = {.speed = 10000}, - [MLX5E_20GBASE_KR2] = {.speed = 20000}, - [MLX5E_40GBASE_CR4] = {.speed = 40000}, - [MLX5E_40GBASE_KR4] = {.speed = 40000}, - [MLX5E_56GBASE_R4] = {.speed = 56000}, - [MLX5E_10GBASE_CR] = {.speed = 10000}, - [MLX5E_10GBASE_SR] = {.speed = 10000}, - [MLX5E_10GBASE_ER] = {.speed = 10000}, - [MLX5E_40GBASE_SR4] = {.speed = 40000}, - [MLX5E_40GBASE_LR4] = {.speed = 40000}, - [MLX5E_50GBASE_SR2] = {.speed = 50000}, - [MLX5E_100GBASE_CR4] = {.speed = 100000}, - [MLX5E_100GBASE_SR4] = {.speed = 100000}, - [MLX5E_100GBASE_KR4] = {.speed = 100000}, - [MLX5E_100GBASE_LR4] = {.speed = 100000}, - [MLX5E_100BASE_TX] = {.speed = 100}, - [MLX5E_1000BASE_T] = {.speed = 1000}, - [MLX5E_10GBASE_T] = {.speed = 10000}, - [MLX5E_25GBASE_CR] = {.speed = 25000}, - [MLX5E_25GBASE_KR] = {.speed = 25000}, - [MLX5E_25GBASE_SR] = {.speed = 25000}, - [MLX5E_50GBASE_CR2] = {.speed = 50000}, - [MLX5E_50GBASE_KR2] = {.speed = 50000}, + [MLX5E_1000BASE_CX_SGMII] = {.speed = 1000, .lanes = 1}, + [MLX5E_1000BASE_KX] = {.speed = 1000, .lanes = 1}, + [MLX5E_10GBASE_CX4] = {.speed = 10000, .lanes = 4}, + [MLX5E_10GBASE_KX4] = {.speed = 10000, .lanes = 4}, + [MLX5E_10GBASE_KR] = {.speed = 10000, .lanes = 1}, + [MLX5E_20GBASE_KR2] = {.speed = 20000, .lanes = 2}, + [MLX5E_40GBASE_CR4] = {.speed = 40000, .lanes = 4}, + [MLX5E_40GBASE_KR4] = {.speed = 40000, .lanes = 4}, + [MLX5E_56GBASE_R4] = {.speed = 56000, .lanes = 4}, + [MLX5E_10GBASE_CR] = {.speed = 10000, .lanes = 1}, + [MLX5E_10GBASE_SR] = {.speed = 10000, .lanes = 1}, + [MLX5E_10GBASE_ER] = {.speed = 10000, .lanes = 1}, + [MLX5E_40GBASE_SR4] = {.speed = 40000, .lanes = 4}, + [MLX5E_40GBASE_LR4] = {.speed = 40000, .lanes = 4}, + [MLX5E_50GBASE_SR2] = {.speed = 50000, .lanes = 2}, + [MLX5E_100GBASE_CR4] = {.speed = 100000, .lanes = 4}, + [MLX5E_100GBASE_SR4] = {.speed = 100000, .lanes = 4}, + [MLX5E_100GBASE_KR4] = {.speed = 100000, .lanes = 4}, + [MLX5E_100GBASE_LR4] = {.speed = 100000, .lanes = 4}, + [MLX5E_100BASE_TX] = {.speed = 100, .lanes = 1}, + [MLX5E_1000BASE_T] = {.speed = 1000, .lanes = 1}, + [MLX5E_10GBASE_T] = {.speed = 10000, .lanes = 1}, + [MLX5E_25GBASE_CR] = {.speed = 25000, .lanes = 1}, + [MLX5E_25GBASE_KR] = {.speed = 25000, .lanes = 1}, + [MLX5E_25GBASE_SR] = {.speed = 25000, .lanes = 1}, + [MLX5E_50GBASE_CR2] = {.speed = 50000, .lanes = 2}, + [MLX5E_50GBASE_KR2] = {.speed = 50000, .lanes = 2}, }; static const struct mlx5_link_info mlx5e_ext_link_info[MLX5E_EXT_LINK_MODES_NUMBER] = { - [MLX5E_SGMII_100M] = {.speed = 100}, - [MLX5E_1000BASE_X_SGMII] = {.speed = 1000}, - [MLX5E_5GBASE_R] = {.speed = 5000}, - [MLX5E_10GBASE_XFI_XAUI_1] = {.speed = 10000}, - [MLX5E_40GBASE_XLAUI_4_XLPPI_4] = {.speed = 40000}, - [MLX5E_25GAUI_1_25GBASE_CR_KR] = {.speed = 25000}, - [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2] = {.speed = 50000}, - [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR] = {.speed = 50000}, - [MLX5E_CAUI_4_100GBASE_CR4_KR4] = {.speed = 100000}, - [MLX5E_100GAUI_2_100GBASE_CR2_KR2] = {.speed = 100000}, - [MLX5E_200GAUI_4_200GBASE_CR4_KR4] = {.speed = 200000}, - [MLX5E_400GAUI_8_400GBASE_CR8] = {.speed = 400000}, - [MLX5E_100GAUI_1_100GBASE_CR_KR] = {.speed = 100000}, - [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = {.speed = 200000}, - [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = {.speed = 400000}, - [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = {.speed = 800000}, - [MLX5E_200GAUI_1_200GBASE_CR1_KR1] = {.speed = 200000}, - [MLX5E_400GAUI_2_400GBASE_CR2_KR2] = {.speed = 400000}, - [MLX5E_800GAUI_4_800GBASE_CR4_KR4] = {.speed = 800000}, + [MLX5E_SGMII_100M] = {.speed = 100, .lanes = 1}, + [MLX5E_1000BASE_X_SGMII] = {.speed = 1000, .lanes = 1}, + [MLX5E_5GBASE_R] = {.speed = 5000, .lanes = 1}, + [MLX5E_10GBASE_XFI_XAUI_1] = {.speed = 10000, .lanes = 1}, + [MLX5E_40GBASE_XLAUI_4_XLPPI_4] = {.speed = 40000, .lanes = 4}, + [MLX5E_25GAUI_1_25GBASE_CR_KR] = {.speed = 25000, .lanes = 1}, + [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2] = {.speed = 50000, .lanes = 2}, + [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR] = {.speed = 50000, .lanes = 1}, + [MLX5E_CAUI_4_100GBASE_CR4_KR4] = {.speed = 100000, .lanes = 4}, + [MLX5E_100GAUI_2_100GBASE_CR2_KR2] = {.speed = 100000, .lanes = 2}, + [MLX5E_200GAUI_4_200GBASE_CR4_KR4] = {.speed = 200000, .lanes = 4}, + [MLX5E_400GAUI_8_400GBASE_CR8] = {.speed = 400000, .lanes = 8}, + [MLX5E_100GAUI_1_100GBASE_CR_KR] = {.speed = 100000, .lanes = 1}, + [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = {.speed = 200000, .lanes = 2}, + [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = {.speed = 400000, .lanes = 4}, + [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = {.speed = 800000, .lanes = 8}, + [MLX5E_200GAUI_1_200GBASE_CR1_KR1] = {.speed = 200000, .lanes = 1}, + [MLX5E_400GAUI_2_400GBASE_CR2_KR2] = {.speed = 400000, .lanes = 2}, + [MLX5E_800GAUI_4_800GBASE_CR4_KR4] = {.speed = 800000, .lanes = 4}, }; int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, @@ -1168,8 +1168,10 @@ u32 mlx5_port_info2linkmodes(struct mlx5_core_dev *mdev, mlx5e_port_get_link_mode_info_arr(mdev, &table, &max_size, force_legacy); for (i = 0; i < max_size; ++i) { - if (table[i].speed == info->speed) - link_modes |= MLX5E_PROT_MASK(i); + if (table[i].speed == info->speed) { + if (!info->lanes || table[i].lanes == info->lanes) + link_modes |= MLX5E_PROT_MASK(i); + } } return link_modes; } diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h index 84833cca29fe..49d50afb102c 100644 --- a/include/uapi/linux/ethtool.h +++ b/include/uapi/linux/ethtool.h @@ -2192,6 +2192,8 @@ enum ethtool_link_mode_bit_indices { #define SPEED_800000 800000 #define SPEED_UNKNOWN -1 +#define LANES_UNKNOWN 0 +#define MAX_LANES 8 static inline int ethtool_validate_speed(__u32 speed) { From patchwork Wed Feb 26 11:47:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13992148 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2088.outbound.protection.outlook.com [40.107.212.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1EB0219E99; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Leon Romanovsky , "Tariq Toukan" , , , , Amir Tzin , Mark Bloch Subject: [PATCH net-next 4/6] net/mlx5: Lag, Enable Multiport E-Switch offloads on 8 ports LAG Date: Wed, 26 Feb 2025 13:47:50 +0200 Message-ID: <20250226114752.104838-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250226114752.104838-1-tariqt@nvidia.com> References: <20250226114752.104838-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C8:EE_|IA0PR12MB8375:EE_ X-MS-Office365-Filtering-Correlation-Id: a90fcc85-b32a-4500-4d5c-08dd565b8827 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: FW6DmNvfo1ZLbdHeVjRRa0oY15ZTUGGjOfVHC3N4BbTJSS/OwczgCSFkUzaC69WVQlPAscqYQ9/a4MxIr+R74eA8b+R7iXKO8bayAwF8zyUQ58acK4KThvDdTatJuUt5mzzP62jKKGaWVLE2ygXbU52iDkVeS/uCjV9RmV8fDbVEOaPeTw8DhXKo1RN52x3vpsIJ3L8PqPrZeMxGM1mk0VWVUn2aOweN+oBQMocZRKXkWqL+bxI92z5Y0BZM4MoFGedfUxDz6RA3oY7KeSvV8HvIUAtkxq8WQbGYcAEt/H4acWhobglpDMF+FScKlnzp/j5ivKyubjWjA3oOVUJlfHXIGG2r12xV6+W8njb6J8kIPh32ABFM1QgNPvxmaggmqGoQdaHTiAa5W0NLBa7ohd+/ji4KiJvftw9MmDw+sBItPBob6ctOVWUFNQ+HAi589KSBvNeRMl+N9ByUV/AjBTm++hSGNe25OiQbjxVchwjDQDmCp5OBROJh7y4zCF5ZHXH6/klb9qmM4ZBNyoyfm+5KinEkRatx0yOEmk4cwTG9OpM3TQKBneHaqQEgrTxBEoE+udkAaUrJH4JRF+3oCjnDSKdoIsVniZ+fYKfpZ/41tYINbOTS1lPHrUVrrBlQQefAJvSJkSuRuj/bpOFVxW2EkW+Cgt53b8JQJURFiAiNX7HfTEzPQL8mdJFFW9o1ZyYWGRU5yRSjkbYWgcV44ndcyjAmue5zAmTQVR7IEUYSD6L5v/HtEbjjJ47pXYX3BCvgPY8BXnMR7hKZpd+Yp+BtkSCDjfv9rVEqE2eHDUGMr2GJGtgn6dEUyonWopUDlKY1+VPZwmYfPz8UjQ9DVOKP1MGLkoABwiwnYRZG5kn2oQt/eqNfRaiywLWoK9XdPJb/3LD2DtNlZPV1HG/aIQPR/JYk0FoDv6ILGr04/DQ14P2xW6rKu9fENlC7bfZPnvM2dOrAmv9RBv4HSO/AJJv8PE64DC7ovEMLoq32czpllmj31+GMvotD2OXFsn45MJle2f38TRElq5J3BeKF0UJzRGnd/jPMw+irDB4AIwFtJEKrt6G9n+Zyj/WF2xNNzDKSvvybIGNQT8X1pJsTsZygYCGFeQP17Oq8oubA3tb5FTXR4+eJoK+Mf7qNKdp5PXl+GZGPuUe6uKEB/WybHVqviW32YLLOH13eVSLxFYVFAoffr4hRnFKy4qwbEf/BplsDN0Cmp7XfZZS9gromCixvLp39CqST2Gh1hCguLnll15vVLKzVKrFkOGeB52nlaIWTFywe8mrTuWcCZPzzZtZZUkalO8+Zy69S4KGmuQB6XWXCMoJBbBXkR3K4E07vt+3+77R8KbFH5qgqRb7DHy0QOx2Ll392WI57gKlDHF1Y0jp6PX9HqJu4RBVPYHnf4ZMW9S6uRVbAtQMv2MG/Bl1MgaxhQlvaVffBPydkKnQi1YU1VHWHvx5uV2ryeJkelnc87Te/3asV9BT8CqnxfP1moXhJKuVi9goXFAuxuTk= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 11:48:48.1517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a90fcc85-b32a-4500-4d5c-08dd565b8827 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8375 X-Patchwork-Delegate: kuba@kernel.org From: Amir Tzin Patch [1] added mlx5 driver support for 8 ports HCAs which are available since ConnectX-8. Now that Multiport E-Switch is tested, we can enable it by removing flag MLX5_LAG_MPESW_OFFLOADS_SUPPORTED_PORTS. [1] commit e0e6adfe8c20 ("net/mlx5: Enable 8 ports LAG") Signed-off-by: Amir Tzin Signed-off-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c index ffac0bd6c895..cbde54324059 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -65,7 +65,6 @@ static int mlx5_mpesw_metadata_set(struct mlx5_lag *ldev) return err; } -#define MLX5_LAG_MPESW_OFFLOADS_SUPPORTED_PORTS 4 static int enable_mpesw(struct mlx5_lag *ldev) { int idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); @@ -77,9 +76,6 @@ static int enable_mpesw(struct mlx5_lag *ldev) return -EINVAL; dev0 = ldev->pf[idx].dev; - if (ldev->ports > MLX5_LAG_MPESW_OFFLOADS_SUPPORTED_PORTS) - return -EOPNOTSUPP; - if (mlx5_eswitch_mode(dev0) != MLX5_ESWITCH_OFFLOADS || !MLX5_CAP_PORT_SELECTION(dev0, port_select_flow_table) || !MLX5_CAP_GEN(dev0, create_lag_when_not_master_up) || From patchwork Wed Feb 26 11:47:51 2025 Content-Type: text/plain; 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Wed, 26 Feb 2025 03:48:37 -0800 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Leon Romanovsky , "Tariq Toukan" , , , Subject: [PATCH net-next 5/6] net/mlx5e: Separate address related variables to be in struct Date: Wed, 26 Feb 2025 13:47:51 +0200 Message-ID: <20250226114752.104838-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250226114752.104838-1-tariqt@nvidia.com> References: <20250226114752.104838-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE7:EE_|LV3PR12MB9186:EE_ X-MS-Office365-Filtering-Correlation-Id: 79047777-dc6a-4368-ab6c-08dd565b8e1e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: FbXsfolkc1pOEdX1Su+FPGiJUTRBv91iwGj1WJEeF+xmnrwHtlsOAm1Hw9GRDrf2Vk6ywFiWHmVWUgxbvyHfIBEEmrQsSA7ZurPIlPFRiFZeCqz1TxpnI1oCuU8UmzbdUoPSq90D16DWHf6ZfDbLoXutbwEOVHQaiDMd0tetEEVaQQsfqZ6BeuCUT9pEnZkPxEyhbPt10Dr/Hxtvzm8QTbco0eWLj4IddJIRiR3wpOn0KK+xi9EYRcYDXOQT2jhpVtrZ6pMAVaPuKaOK/v83V/T8PK6CSqCViH8UeNQCj1fz5hxW6EqQn2bi8TN5p5jcteG6jzF4FBMZBtJ++T1JvCMf/BSLd8lQlenKlrneZUc9/lV6azlPOtDxmFRhbJhbbenq4fqO7vK4bj5lADJxShP59LdDJLVue33eAF5SiDNdwLv/kJ++JLSpzL2oL3I4RtkVF55Dno5x3c3IlGePqkhojGgljVx+QDqmmdFGcm8AyZOIq4ViQFvK8VNXNUjaddTV8OWtLZarCrmsryHlfQYbSdDYvDrI0zylF4/xAuY/sQQSBv6WQMTFJSFJpkxKiXilniwPMnFQvlfRvAwM9x5L17geBsywLb25iC31yWBCSGwqKv0vYlpiSXBuqv8bcVD5Wm0ahf4Oi2AWt6MQ1UBCtsHgDDyQ/zL2VrwfQI6eFpHXke5mdfH46MZ5js4oezbtjSmugcb6v/nQt9cmuRmaQlYF/y+LebqtNB06tcgo+RSH/kCV/E6KdzEZhyho2ojpqvs6Pe+OYuPMiwQJlgNq/cAjQtFa+3vXBecZMOcUMhSPbXsB8uZDsBjvxaLUdePwhF0cVG9H01s0+tZR4POIQatvETClOWBie3kXeTDIBzc8oND/C+q963qoYKzVkY0WAJ1Cl2+CNLon40b4E7zEYQX1kphFc0X1KB+IprTiWxUKuBVZAZ5g5ymSTbEiI9ZGl702DYSVEciR17Da36dEFbUSAfhnns6tUMFiBfSdf38Ufi7RZejex2yxXI6zM+lw6RcDdZWXeC9p/VOMJG43FkTLiBt/7CU1l245xcUWni0aLg4+8iR3sY1dmoynwSP3RZQkNEt0+rkJm7BLcZzld/lU3FW0buw3LJr+snp8vxbf8D15uJbdtk6ymVXdURYe3UzCMtQmrEtFRVoGt+6ZrnGOkjAEh7Z0LX8QUHlrBAv6S8OYHZcaXbBmHnLwF4znQb9tNYo2j9b4JG3t0nNGiaTPj/F99lw4gUjJeLAi6lmwBozuGzdfcMRhHpMKtvA+IvGTNgkLHI7tDOu+0xZTpRmbHYpb4n8cHNviFcZ/9xYGeb3fa72mBht2Y7syLPSUYmNwlTvNPsQR7rM4uVBadf6x1x6pDf5t+BiMlQe7HACvqZA5KWmv2wNXuGikjOWQreMMvdzOS1h4pMOMMaESlWig4Ub8a+9DZb8FzJcofdbCPUJzB9pquXPJRYkMcorl9zVJfaLd0eM3wFqNkdEgig1DNcdiEZsY8TymwIg= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 11:48:58.1772 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79047777-dc6a-4368-ab6c-08dd565b8e1e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9186 X-Patchwork-Delegate: kuba@kernel.org From: Leon Romanovsky Prepare the code to addition of prefix handling logic which is needed to support matching logic based on source and/or destination network prefixes. Signed-off-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec.c | 32 ++++---- .../mellanox/mlx5/core/en_accel/ipsec.h | 26 +++---- .../mellanox/mlx5/core/en_accel/ipsec_fs.c | 75 +++++++++++-------- 3 files changed, 68 insertions(+), 65 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index 501709ac310f..beb7275d721a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -277,12 +277,12 @@ static void mlx5e_ipsec_init_macs(struct mlx5e_ipsec_sa_entry *sa_entry, case XFRM_DEV_OFFLOAD_IN: src = attrs->dmac; dst = attrs->smac; - pkey = &attrs->saddr.a4; + pkey = &attrs->addrs.saddr.a4; break; case XFRM_DEV_OFFLOAD_OUT: src = attrs->smac; dst = attrs->dmac; - pkey = &attrs->daddr.a4; + pkey = &attrs->addrs.daddr.a4; break; default: return; @@ -374,9 +374,10 @@ void mlx5e_ipsec_build_accel_xfrm_attrs(struct mlx5e_ipsec_sa_entry *sa_entry, attrs->spi = be32_to_cpu(x->id.spi); /* source , destination ips */ - memcpy(&attrs->saddr, x->props.saddr.a6, sizeof(attrs->saddr)); - memcpy(&attrs->daddr, x->id.daddr.a6, sizeof(attrs->daddr)); - attrs->family = x->props.family; + memcpy(&attrs->addrs.saddr, x->props.saddr.a6, + sizeof(attrs->addrs.saddr)); + memcpy(&attrs->addrs.daddr, x->id.daddr.a6, sizeof(attrs->addrs.daddr)); + attrs->addrs.family = x->props.family; attrs->type = x->xso.type; attrs->reqid = x->props.reqid; attrs->upspec.dport = ntohs(x->sel.dport); @@ -428,7 +429,8 @@ static int mlx5e_xfrm_validate_state(struct mlx5_core_dev *mdev, } if (x->encap) { if (!(mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_ESPINUDP)) { - NL_SET_ERR_MSG_MOD(extack, "Encapsulation is not supported"); + NL_SET_ERR_MSG_MOD(extack, + "Encapsulation is not supported"); return -EINVAL; } @@ -853,13 +855,13 @@ static int mlx5e_ipsec_netevent_event(struct notifier_block *nb, xa_for_each_marked(&ipsec->sadb, idx, sa_entry, MLX5E_IPSEC_TUNNEL_SA) { attrs = &sa_entry->attrs; - if (attrs->family == AF_INET) { - if (!neigh_key_eq32(n, &attrs->saddr.a4) && - !neigh_key_eq32(n, &attrs->daddr.a4)) + if (attrs->addrs.family == AF_INET) { + if (!neigh_key_eq32(n, &attrs->addrs.saddr.a4) && + !neigh_key_eq32(n, &attrs->addrs.daddr.a4)) continue; } else { - if (!neigh_key_eq128(n, &attrs->saddr.a4) && - !neigh_key_eq128(n, &attrs->daddr.a4)) + if (!neigh_key_eq128(n, &attrs->addrs.saddr.a4) && + !neigh_key_eq128(n, &attrs->addrs.daddr.a4)) continue; } @@ -1035,7 +1037,7 @@ static void mlx5e_xfrm_update_stats(struct xfrm_state *x) * by removing always available headers. */ headers = sizeof(struct ethhdr); - if (sa_entry->attrs.family == AF_INET) + if (sa_entry->attrs.addrs.family == AF_INET) headers += sizeof(struct iphdr); else headers += sizeof(struct ipv6hdr); @@ -1116,9 +1118,9 @@ mlx5e_ipsec_build_accel_pol_attrs(struct mlx5e_ipsec_pol_entry *pol_entry, sel = &x->selector; memset(attrs, 0, sizeof(*attrs)); - memcpy(&attrs->saddr, sel->saddr.a6, sizeof(attrs->saddr)); - memcpy(&attrs->daddr, sel->daddr.a6, sizeof(attrs->daddr)); - attrs->family = sel->family; + memcpy(&attrs->addrs.saddr, sel->saddr.a6, sizeof(attrs->addrs.saddr)); + memcpy(&attrs->addrs.daddr, sel->daddr.a6, sizeof(attrs->addrs.daddr)); + attrs->addrs.family = sel->family; attrs->dir = x->xdo.dir; attrs->action = x->action; attrs->type = XFRM_DEV_OFFLOAD_PACKET; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index ad8db9e1fd1d..37ef1e331135 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -76,11 +76,7 @@ struct mlx5_replay_esn { u8 trigger : 1; }; -struct mlx5_accel_esp_xfrm_attrs { - u32 spi; - u32 mode; - struct aes_gcm_keymat aes_gcm; - +struct mlx5e_ipsec_addr { union { __be32 a4; __be32 a6[4]; @@ -90,13 +86,19 @@ struct mlx5_accel_esp_xfrm_attrs { __be32 a4; __be32 a6[4]; } daddr; + u8 family; +}; +struct mlx5_accel_esp_xfrm_attrs { + u32 spi; + u32 mode; + struct aes_gcm_keymat aes_gcm; + struct mlx5e_ipsec_addr addrs; struct upspec upspec; u8 dir : 2; u8 type : 2; u8 drop : 1; u8 encap : 1; - u8 family; struct mlx5_replay_esn replay_esn; u32 authsize; u32 reqid; @@ -279,18 +281,8 @@ struct mlx5e_ipsec_sa_entry { }; struct mlx5_accel_pol_xfrm_attrs { - union { - __be32 a4; - __be32 a6[4]; - } saddr; - - union { - __be32 a4; - __be32 a6[4]; - } daddr; - + struct mlx5e_ipsec_addr addrs; struct upspec upspec; - u8 family; u8 action; u8 type : 2; u8 dir : 2; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index d51ace739637..23b63dea2f7f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -1484,9 +1484,12 @@ static void tx_ft_put_policy(struct mlx5e_ipsec *ipsec, u32 prio, int type) mutex_unlock(&tx->ft.mutex); } -static void setup_fte_addr4(struct mlx5_flow_spec *spec, __be32 *saddr, - __be32 *daddr) +static void setup_fte_addr4(struct mlx5_flow_spec *spec, + struct mlx5e_ipsec_addr *addrs) { + __be32 *saddr = &addrs->saddr.a4; + __be32 *daddr = &addrs->daddr.a4; + if (!*saddr && !*daddr) return; @@ -1510,9 +1513,12 @@ static void setup_fte_addr4(struct mlx5_flow_spec *spec, __be32 *saddr, } } -static void setup_fte_addr6(struct mlx5_flow_spec *spec, __be32 *saddr, - __be32 *daddr) +static void setup_fte_addr6(struct mlx5_flow_spec *spec, + struct mlx5e_ipsec_addr *addrs) { + __be32 *saddr = addrs->saddr.a6; + __be32 *daddr = addrs->daddr.a6; + if (addr6_all_zero(saddr) && addr6_all_zero(daddr)) return; @@ -1722,7 +1728,7 @@ setup_pkt_tunnel_reformat(struct mlx5_core_dev *mdev, if (attrs->dir == XFRM_DEV_OFFLOAD_OUT) { bfflen += sizeof(*esp_hdr) + 8; - switch (attrs->family) { + switch (attrs->addrs.family) { case AF_INET: bfflen += sizeof(*iphdr); break; @@ -1739,7 +1745,7 @@ setup_pkt_tunnel_reformat(struct mlx5_core_dev *mdev, return -ENOMEM; eth_hdr = (struct ethhdr *)reformatbf; - switch (attrs->family) { + switch (attrs->addrs.family) { case AF_INET: eth_hdr->h_proto = htons(ETH_P_IP); break; @@ -1762,11 +1768,11 @@ setup_pkt_tunnel_reformat(struct mlx5_core_dev *mdev, reformat_params->param_0 = attrs->authsize; hdr = reformatbf + sizeof(*eth_hdr); - switch (attrs->family) { + switch (attrs->addrs.family) { case AF_INET: iphdr = (struct iphdr *)hdr; - memcpy(&iphdr->saddr, &attrs->saddr.a4, 4); - memcpy(&iphdr->daddr, &attrs->daddr.a4, 4); + memcpy(&iphdr->saddr, &attrs->addrs.saddr.a4, 4); + memcpy(&iphdr->daddr, &attrs->addrs.daddr.a4, 4); iphdr->version = 4; iphdr->ihl = 5; iphdr->ttl = IPSEC_TUNNEL_DEFAULT_TTL; @@ -1775,8 +1781,8 @@ setup_pkt_tunnel_reformat(struct mlx5_core_dev *mdev, break; case AF_INET6: ipv6hdr = (struct ipv6hdr *)hdr; - memcpy(&ipv6hdr->saddr, &attrs->saddr.a6, 16); - memcpy(&ipv6hdr->daddr, &attrs->daddr.a6, 16); + memcpy(&ipv6hdr->saddr, &attrs->addrs.saddr.a6, 16); + memcpy(&ipv6hdr->daddr, &attrs->addrs.daddr.a6, 16); ipv6hdr->nexthdr = IPPROTO_ESP; ipv6hdr->version = 6; ipv6hdr->hop_limit = IPSEC_TUNNEL_DEFAULT_TTL; @@ -1810,7 +1816,7 @@ static int get_reformat_type(struct mlx5_accel_esp_xfrm_attrs *attrs) return MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP; return MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT; case XFRM_DEV_OFFLOAD_OUT: - if (attrs->family == AF_INET) { + if (attrs->addrs.family == AF_INET) { if (attrs->encap) return MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4; return MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4; @@ -2003,7 +2009,7 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry) struct mlx5_fc *counter; int err = 0; - rx = rx_ft_get(mdev, ipsec, attrs->family, attrs->type); + rx = rx_ft_get(mdev, ipsec, attrs->addrs.family, attrs->type); if (IS_ERR(rx)) return PTR_ERR(rx); @@ -2013,10 +2019,10 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry) goto err_alloc; } - if (attrs->family == AF_INET) - setup_fte_addr4(spec, &attrs->saddr.a4, &attrs->daddr.a4); + if (attrs->addrs.family == AF_INET) + setup_fte_addr4(spec, &attrs->addrs); else - setup_fte_addr6(spec, attrs->saddr.a6, attrs->daddr.a6); + setup_fte_addr6(spec, &attrs->addrs); setup_fte_spi(spec, attrs->spi, attrs->encap); if (!attrs->encap) @@ -2116,7 +2122,7 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry) err_mod_header: kvfree(spec); err_alloc: - rx_ft_put(ipsec, attrs->family, attrs->type); + rx_ft_put(ipsec, attrs->addrs.family, attrs->type); return err; } @@ -2148,10 +2154,10 @@ static int tx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry) switch (attrs->type) { case XFRM_DEV_OFFLOAD_CRYPTO: - if (attrs->family == AF_INET) - setup_fte_addr4(spec, &attrs->saddr.a4, &attrs->daddr.a4); + if (attrs->addrs.family == AF_INET) + setup_fte_addr4(spec, &attrs->addrs); else - setup_fte_addr6(spec, attrs->saddr.a6, attrs->daddr.a6); + setup_fte_addr6(spec, &attrs->addrs); setup_fte_spi(spec, attrs->spi, false); setup_fte_esp(spec); setup_fte_reg_a(spec); @@ -2235,10 +2241,10 @@ static int tx_add_policy(struct mlx5e_ipsec_pol_entry *pol_entry) } tx = ipsec_tx(ipsec, attrs->type); - if (attrs->family == AF_INET) - setup_fte_addr4(spec, &attrs->saddr.a4, &attrs->daddr.a4); + if (attrs->addrs.family == AF_INET) + setup_fte_addr4(spec, &attrs->addrs); else - setup_fte_addr6(spec, attrs->saddr.a6, attrs->daddr.a6); + setup_fte_addr6(spec, &attrs->addrs); setup_fte_no_frags(spec); setup_fte_upper_proto_match(spec, &attrs->upspec); @@ -2308,12 +2314,12 @@ static int rx_add_policy(struct mlx5e_ipsec_pol_entry *pol_entry) struct mlx5e_ipsec_rx *rx; int err, dstn = 0; - ft = rx_ft_get_policy(mdev, pol_entry->ipsec, attrs->family, attrs->prio, - attrs->type); + ft = rx_ft_get_policy(mdev, pol_entry->ipsec, attrs->addrs.family, + attrs->prio, attrs->type); if (IS_ERR(ft)) return PTR_ERR(ft); - rx = ipsec_rx(pol_entry->ipsec, attrs->family, attrs->type); + rx = ipsec_rx(pol_entry->ipsec, attrs->addrs.family, attrs->type); spec = kvzalloc(sizeof(*spec), GFP_KERNEL); if (!spec) { @@ -2321,10 +2327,10 @@ static int rx_add_policy(struct mlx5e_ipsec_pol_entry *pol_entry) goto err_alloc; } - if (attrs->family == AF_INET) - setup_fte_addr4(spec, &attrs->saddr.a4, &attrs->daddr.a4); + if (attrs->addrs.family == AF_INET) + setup_fte_addr4(spec, &attrs->addrs); else - setup_fte_addr6(spec, attrs->saddr.a6, attrs->daddr.a6); + setup_fte_addr6(spec, &attrs->addrs); setup_fte_no_frags(spec); setup_fte_upper_proto_match(spec, &attrs->upspec); @@ -2364,7 +2370,8 @@ static int rx_add_policy(struct mlx5e_ipsec_pol_entry *pol_entry) err_action: kvfree(spec); err_alloc: - rx_ft_put_policy(pol_entry->ipsec, attrs->family, attrs->prio, attrs->type); + rx_ft_put_policy(pol_entry->ipsec, attrs->addrs.family, attrs->prio, + attrs->type); return err; } @@ -2638,7 +2645,8 @@ void mlx5e_accel_ipsec_fs_del_rule(struct mlx5e_ipsec_sa_entry *sa_entry) mlx5_fc_destroy(mdev, ipsec_rule->replay.fc); } mlx5_esw_ipsec_rx_id_mapping_remove(sa_entry); - rx_ft_put(sa_entry->ipsec, sa_entry->attrs.family, sa_entry->attrs.type); + rx_ft_put(sa_entry->ipsec, sa_entry->attrs.addrs.family, + sa_entry->attrs.type); } int mlx5e_accel_ipsec_fs_add_pol(struct mlx5e_ipsec_pol_entry *pol_entry) @@ -2674,7 +2682,8 @@ void mlx5e_accel_ipsec_fs_del_pol(struct mlx5e_ipsec_pol_entry *pol_entry) mlx5e_ipsec_unblock_tc_offload(pol_entry->ipsec->mdev); if (pol_entry->attrs.dir == XFRM_DEV_OFFLOAD_IN) { - rx_ft_put_policy(pol_entry->ipsec, pol_entry->attrs.family, + rx_ft_put_policy(pol_entry->ipsec, + pol_entry->attrs.addrs.family, pol_entry->attrs.prio, pol_entry->attrs.type); return; } @@ -2814,7 +2823,7 @@ bool mlx5e_ipsec_fs_tunnel_enabled(struct mlx5e_ipsec_sa_entry *sa_entry) struct mlx5e_ipsec_rx *rx; struct mlx5e_ipsec_tx *tx; - rx = ipsec_rx(sa_entry->ipsec, attrs->family, attrs->type); + rx = ipsec_rx(sa_entry->ipsec, attrs->addrs.family, attrs->type); tx = ipsec_tx(sa_entry->ipsec, attrs->type); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Leon Romanovsky , "Tariq Toukan" , , , Subject: [PATCH net-next 6/6] net/mlx5e: Properly match IPsec subnet addresses Date: Wed, 26 Feb 2025 13:47:52 +0200 Message-ID: <20250226114752.104838-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250226114752.104838-1-tariqt@nvidia.com> References: <20250226114752.104838-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE9:EE_|MN2PR12MB4207:EE_ X-MS-Office365-Filtering-Correlation-Id: 43bc5d86-da56-4c36-a720-08dd565b8f36 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: xsgHdkmv9LNJs3Vkvrr4Hi5T8iDtTDBwiqM7c6JTOBLkTJxLpIgISqN6baDgdEeTo0zWFSvBzsWriL7uzVTuOT/aGZ+2YL+lrWjJ5LE6jvoy7W21NorW2QQ5ElIMVIIZXLLjc9YsDH9zmXBCKortTsic4pwSZ8ynIUQM5ccfyIykapkxFhgty7NydZGWA1hcwLCsKC3etRuaiYCAuWHrlwqaUMwDjLSOpiC4O1H3On9f8NsUrw/FWDTVbMRvRTjQhbrQLk1PskWTyL3gDGAc5mgaY5jj/FJlTzcKgKiNBiHEoMuFTV3uJbuV9XD5RowdoRzjuV0Qy2JaQskgdaaaF4MDbcACdK2WbaH2BkcmBhujzbdWvVfkrkuktgerbwAax3iNBaWTTi0GZJY/GfP5vXlMkW9tkfsxBN1s60hv2GKl48HOnRRowWqQJLy4i4vPYU2LmjFlLNF83nr0xp9bf9xc1mASpIhJ4093uaU2FR9Xj4Yu0FjOsd38IOpWIctQP9Otx2azbPm9x9p2Z4137pmCsqcV9Rtus6I3MnhKr3CqBzvqA/OoaxSlir5Gb7YkRyq1See6VxYmPN8qvkcdWWig/HVY0jOsuTQ/W+hbLng4JF+dZUZ0n4uiQHAqSro4ssdbymUWnJOHaRA3OhvqZqD/N5yb1k1BuDmofDv+CQTwC/qgo02EBuB1FOJWeCA2o6pvCwjjm+q71euFmxHsEw+MlCTmHOYSgZ+A+yEO++894NzJuptUbpYzOFLB+RBR+90GZlVrtg1vfd6s+K8hXc+e9N0HDJpH695gPDD5eF//9j2StlNIyxcP8lK+mDzJxdcL0Lif383HzvXfINBS1AU2vGeKmiWSV5+ncLUQbnSL35FK+Yjh2+7Q66tdodSyAy4NUBDH4HVKud+m6uQYIU04OyszqE6gPjPNOJ7+0Wu88CF5+JiOQRBCr4ZhbXVICQkfHxuL0kn2rpEWQxVQPvZueGJ7knsuXvI/T1YflN0/VGWmIXs31WhbVgR1UsElX8o1K4LsLF+RAncxJ8/HeM+JQIxWZ/yE4AvxB9oHnGGA+d0w/Z/hdLeDkCdQLts2vdN09vaH79lHWfVyQIMKDz9hhRCRhxn/42D+dcrTV0QmIQpl6m/pPACD14zKl6dLbEAaklgaespYJeN98oSjX+ztdoGTOi17mQZnELyi3fYevqlYnXwpG840qhp43ljfZ3dyh0PdGf572eyonvvnoslalFqYOsgIyv8vxEF7TPGKvZfPc7oo81s2e1nB6w9+Ja/WXDVBdeUMbfM7Tjm4t3S5tN9Qoc4JURIrr4rrul2a42svGvFFfpJbmi9o9R17109B4qFUJQgorAaU3US1MUlzE2gSCzwyeKwgtXNxvpRlEs6F/3cQB/xhmsL0LYrHNdP7dG+DRoLjmB17c5/zICXsAdtiM4xpbofqp0tkgglBvxvySOM/p2RkY1AiZ6vjtgZbi7tzSvyrwF2JEQqkyIqKIUrx67W55zQSKdEQQ54= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 11:49:00.0121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43bc5d86-da56-4c36-a720-08dd565b8f36 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4207 X-Patchwork-Delegate: kuba@kernel.org From: Leon Romanovsky Existing match criteria didn't allow to match whole subnet and only by specific addresses only. This caused to tunnel mode do not forward such traffic through relevant SA. In tunnel mode, policies look like this: src 192.169.0.0/16 dst 192.169.0.0/16 dir out priority 383615 ptype main tmpl src 192.169.101.2 dst 192.169.101.1 proto esp spi 0xc5141c18 reqid 1 mode tunnel crypto offload parameters: dev eth2 mode packet In this case, the XFRM core code handled all subnet calculations and forwarded network address to the drivers e.g. 192.169.0.0. For mlx5 devices, there is a need to set relevant prefix e.g. 0xFFFF00 to perform flow steering match operation. Signed-off-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec.c | 49 +++++++++++++++++++ .../mellanox/mlx5/core/en_accel/ipsec.h | 9 +++- .../mellanox/mlx5/core/en_accel/ipsec_fs.c | 20 +++++--- 3 files changed, 69 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index beb7275d721a..782f6d51434d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -303,6 +303,16 @@ static void mlx5e_ipsec_init_macs(struct mlx5e_ipsec_sa_entry *sa_entry, neigh_release(n); } +static void mlx5e_ipsec_state_mask(struct mlx5e_ipsec_addr *addrs) +{ + /* + * State doesn't have subnet prefixes in outer headers. + * The match is performed for exaxt source/destination addresses. + */ + memset(addrs->smask.m6, 0xFF, sizeof(__be32) * 4); + memset(addrs->dmask.m6, 0xFF, sizeof(__be32) * 4); +} + void mlx5e_ipsec_build_accel_xfrm_attrs(struct mlx5e_ipsec_sa_entry *sa_entry, struct mlx5_accel_esp_xfrm_attrs *attrs) { @@ -378,6 +388,7 @@ void mlx5e_ipsec_build_accel_xfrm_attrs(struct mlx5e_ipsec_sa_entry *sa_entry, sizeof(attrs->addrs.saddr)); memcpy(&attrs->addrs.daddr, x->id.daddr.a6, sizeof(attrs->addrs.daddr)); attrs->addrs.family = x->props.family; + mlx5e_ipsec_state_mask(&attrs->addrs); attrs->type = x->xso.type; attrs->reqid = x->props.reqid; attrs->upspec.dport = ntohs(x->sel.dport); @@ -1046,6 +1057,43 @@ static void mlx5e_xfrm_update_stats(struct xfrm_state *x) x->curlft.bytes += success_bytes - headers * success_packets; } +static __be32 word_to_mask(int prefix) +{ + if (prefix < 0) + return 0; + + if (!prefix || prefix > 31) + return cpu_to_be32(0xFFFFFFFF); + + return cpu_to_be32(((1U << prefix) - 1) << (32 - prefix)); +} + +static void mlx5e_ipsec_policy_mask(struct mlx5e_ipsec_addr *addrs, + struct xfrm_selector *sel) +{ + int i; + + if (addrs->family == AF_INET) { + addrs->smask.m4 = word_to_mask(sel->prefixlen_s); + addrs->saddr.a4 &= addrs->smask.m4; + addrs->dmask.m4 = word_to_mask(sel->prefixlen_d); + addrs->daddr.a4 &= addrs->dmask.m4; + return; + } + + for (i = 0; i < 4; i++) { + if (sel->prefixlen_s != 32 * i) + addrs->smask.m6[i] = + word_to_mask(sel->prefixlen_s - 32 * i); + addrs->saddr.a6[i] &= addrs->smask.m6[i]; + + if (sel->prefixlen_d != 32 * i) + addrs->dmask.m6[i] = + word_to_mask(sel->prefixlen_d - 32 * i); + addrs->daddr.a6[i] &= addrs->dmask.m6[i]; + } +} + static int mlx5e_xfrm_validate_policy(struct mlx5_core_dev *mdev, struct xfrm_policy *x, struct netlink_ext_ack *extack) @@ -1121,6 +1169,7 @@ mlx5e_ipsec_build_accel_pol_attrs(struct mlx5e_ipsec_pol_entry *pol_entry, memcpy(&attrs->addrs.saddr, sel->saddr.a6, sizeof(attrs->addrs.saddr)); memcpy(&attrs->addrs.daddr, sel->daddr.a6, sizeof(attrs->addrs.daddr)); attrs->addrs.family = sel->family; + mlx5e_ipsec_policy_mask(&attrs->addrs, sel); attrs->dir = x->xdo.dir; attrs->action = x->action; attrs->type = XFRM_DEV_OFFLOAD_PACKET; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index 37ef1e331135..a63c2289f8af 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -81,11 +81,18 @@ struct mlx5e_ipsec_addr { __be32 a4; __be32 a6[4]; } saddr; - + union { + __be32 m4; + __be32 m6[4]; + } smask; union { __be32 a4; __be32 a6[4]; } daddr; + union { + __be32 m4; + __be32 m6[4]; + } dmask; u8 family; }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index 23b63dea2f7f..98b6a3a623f9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -1488,7 +1488,9 @@ static void setup_fte_addr4(struct mlx5_flow_spec *spec, struct mlx5e_ipsec_addr *addrs) { __be32 *saddr = &addrs->saddr.a4; + __be32 *smask = &addrs->smask.m4; __be32 *daddr = &addrs->daddr.a4; + __be32 *dmask = &addrs->dmask.m4; if (!*saddr && !*daddr) return; @@ -1501,15 +1503,15 @@ static void setup_fte_addr4(struct mlx5_flow_spec *spec, if (*saddr) { memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers.src_ipv4_src_ipv6.ipv4_layout.ipv4), saddr, 4); - MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, - outer_headers.src_ipv4_src_ipv6.ipv4_layout.ipv4); + memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_criteria, + outer_headers.src_ipv4_src_ipv6.ipv4_layout.ipv4), smask, 4); } if (*daddr) { memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers.dst_ipv4_dst_ipv6.ipv4_layout.ipv4), daddr, 4); - MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, - outer_headers.dst_ipv4_dst_ipv6.ipv4_layout.ipv4); + memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_criteria, + outer_headers.dst_ipv4_dst_ipv6.ipv4_layout.ipv4), dmask, 4); } } @@ -1517,7 +1519,9 @@ static void setup_fte_addr6(struct mlx5_flow_spec *spec, struct mlx5e_ipsec_addr *addrs) { __be32 *saddr = addrs->saddr.a6; + __be32 *smask = addrs->smask.m6; __be32 *daddr = addrs->daddr.a6; + __be32 *dmask = addrs->dmask.m6; if (addr6_all_zero(saddr) && addr6_all_zero(daddr)) return; @@ -1530,15 +1534,15 @@ static void setup_fte_addr6(struct mlx5_flow_spec *spec, if (!addr6_all_zero(saddr)) { memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers.src_ipv4_src_ipv6.ipv6_layout.ipv6), saddr, 16); - memset(MLX5_ADDR_OF(fte_match_param, spec->match_criteria, - outer_headers.src_ipv4_src_ipv6.ipv6_layout.ipv6), 0xff, 16); + memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_criteria, + outer_headers.src_ipv4_src_ipv6.ipv6_layout.ipv6), dmask, 16); } if (!addr6_all_zero(daddr)) { memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers.dst_ipv4_dst_ipv6.ipv6_layout.ipv6), daddr, 16); - memset(MLX5_ADDR_OF(fte_match_param, spec->match_criteria, - outer_headers.dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 0xff, 16); + memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_criteria, + outer_headers.dst_ipv4_dst_ipv6.ipv6_layout.ipv6), smask, 16); } }