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Wed, 26 Feb 2025 11:06:23 GMT Received: from yuanfang4-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Feb 2025 03:06:16 -0800 From: Yuanfang Zhang Date: Wed, 26 Feb 2025 19:05:50 +0800 Subject: [PATCH v2 1/5] dt-bindings: arm: Add Coresight device Trace NOC definition MIME-Version: 1.0 Message-ID: <20250226-trace-noc-driver-v2-1-8afc6584afc5@quicinc.com> References: <20250226-trace-noc-driver-v2-0-8afc6584afc5@quicinc.com> In-Reply-To: <20250226-trace-noc-driver-v2-0-8afc6584afc5@quicinc.com> To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740567972; l=3550; i=quic_yuanfang@quicinc.com; s=20241209; h=from:subject:message-id; bh=mQRaiDx0oUaGa2qOav58eJ/XL1EVd3She1ceBivGTsg=; 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Signed-off-by: Yuanfang Zhang --- .../bindings/arm/qcom,coresight-tnoc.yaml | 116 +++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2d806cc34c381d27b47dcce126ce5bcf468826a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tnoc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Ttrace NOC(Network On Chip) + +maintainers: + - yuanfang Zhang + +description: + The Trace NoC is an integration hierarchy which is a replacement of Dragonlink + tile configuration. It brings together debug component like TPDA, funnel and + interconnect Trace Noc which collects trace from subsystems and transfers to + QDSS sink. + + It sits in the different subsystem of SOC and aggregates the trace and + transports it to Aggregation TNoC or to QDSS trace sink eventually. Trace NoC + embeds bridges for all the interfaces(APB, ATB, QPMDA & NTS). + + Trace NoC can take inputs from different trace sources i.e. ATB, QPMDA. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tnoc + required: + - compatible + +properties: + $nodename: + pattern: "^tn(@[0-9a-f]+)$" + + compatible: + items: + - const: qcom,coresight-tnoc + - const: arm,primecell + + reg: + minItems: 1 + maxItems: 2 + description: + Physical address space of the device. + + clocks: + maxItems: 1 + description: + Clock sources used by the device. + + clock-names: + items: + - const: apb_pclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-9a-f]+)?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: + Output connection to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + tn@109ab000 { + compatible = "qcom,coresight-tnoc", "arm,primecell"; + reg = <0x0 0x109ab000 0x0 0x4200>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tn_ag_in_tpdm_gcc: endpoint { + remote-endpoint = <&tpdm_gcc_out_tn_ag>; + }; + }; + }; + + out-ports { + port { + tn_ag_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_tn_ag>; + }; + }; + }; + }; +... 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Wed, 26 Feb 2025 11:06:27 GMT Received: from yuanfang4-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Feb 2025 03:06:20 -0800 From: Yuanfang Zhang Date: Wed, 26 Feb 2025 19:05:51 +0800 Subject: [PATCH v2 2/5] coresight: add coresight Trace NOC driver MIME-Version: 1.0 Message-ID: <20250226-trace-noc-driver-v2-2-8afc6584afc5@quicinc.com> References: <20250226-trace-noc-driver-v2-0-8afc6584afc5@quicinc.com> In-Reply-To: <20250226-trace-noc-driver-v2-0-8afc6584afc5@quicinc.com> To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740567972; l=9704; i=quic_yuanfang@quicinc.com; s=20241209; h=from:subject:message-id; bh=fXNjSONmCAabHmnfKn/QyPfEQCzYBYciP1vudtbPH/Y=; b=phxGAhWtAdgIrgZ2UQmFA01C8vIPn3bmVpeGs8jvMIbsedqmH8WUnQpfbiX23YI6OZOR/dQ1B CQg/8uOwbsZC60oGvAU3o5k0rlWltJHBHcQAbNuo+5tzgBwrI8SDXeC X-Developer-Key: i=quic_yuanfang@quicinc.com; a=ed25519; pk=ZrIjRVq9LN8/zCQGbDEwrZK/sfnVjwQ2elyEZAOaV1Q= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -LhF7aYCtjkfHeLQlG3oolL01FCOV2Jn X-Proofpoint-ORIG-GUID: -LhF7aYCtjkfHeLQlG3oolL01FCOV2Jn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-26_02,2025-02-26_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502260088 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250226_030635_146286_88864EF0 X-CRM114-Status: GOOD ( 25.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add driver to support Coresight device Trace NOC(Network On Chip). Trace NOC is an integration hierarchy which is a replacement of Dragonlink configuration. It brings together debug components like TPDA, funnel and interconnect Trace Noc. It sits in the different subsystem of SOC and aggregates the trace and transports to QDSS trace bus. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 190 +++++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.h | 53 ++++++++ 4 files changed, 257 insertions(+) diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 06f0a7594169c5f03ca5f893b7debd294587de78..6cfd160f09d383ab5f5aa276fa57496a52c8f961 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -247,4 +247,17 @@ config CORESIGHT_DUMMY To compile this driver as a module, choose M here: the module will be called coresight-dummy. + +config CORESIGHT_TNOC + tristate "Coresight Trace Noc driver" + help + This driver provides support for Trace NoC component. + Trace NoC is a interconnect that is used to collect trace from + various subsystems and transport it QDSS trace sink.It sits in + the different tiles of SOC and aggregates the trace local to the + tile and transports it another tile or to QDSS trace sink eventually. + + To compile this driver as a module, choose M here: the module will be + called coresight-tnoc. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4ba478211b318ea5305f9f98dda40a041759f09f..60b729979f19c8f8848c77c290605132dba1a991 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ coresight-replicator.o +obj-$(CONFIG_CORESIGHT_TNOC) += coresight-tnoc.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \ coresight-etm3x-sysfs.o diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c new file mode 100644 index 0000000000000000000000000000000000000000..fad8e61f05ef25989aba1be342c547f835e8953a --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-tnoc.h" +#include "coresight-trace-id.h" + +static void trace_noc_enable_hw(struct trace_noc_drvdata *drvdata) +{ + u32 val; + + /* Set ATID */ + writel_relaxed(drvdata->atid, drvdata->base + TRACE_NOC_XLD); + + /* Config sync CR */ + writel_relaxed(0xffff, drvdata->base + TRACE_NOC_SYNCR); + + /* Set frequency value */ + writel_relaxed(drvdata->freq_req_val, drvdata->base + TRACE_NOC_FREQVAL); + + /* Set Ctrl register */ + val = readl_relaxed(drvdata->base + TRACE_NOC_CTRL); + + if (drvdata->flag_type == FLAG_TS) + val = val | TRACE_NOC_CTRL_FLAGTYPE; + else + val = val & ~TRACE_NOC_CTRL_FLAGTYPE; + + if (drvdata->freq_type == FREQ_TS) + val = val | TRACE_NOC_CTRL_FREQTYPE; + else + val = val & ~TRACE_NOC_CTRL_FREQTYPE; + + val = val | TRACE_NOC_CTRL_PORTEN; + writel_relaxed(val, drvdata->base + TRACE_NOC_CTRL); + + dev_dbg(drvdata->dev, "Trace NOC is enabled\n"); +} + +static int trace_noc_enable(struct coresight_device *csdev, struct coresight_connection *inport, + struct coresight_connection *outport) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (csdev->refcnt == 0) + trace_noc_enable_hw(drvdata); + + csdev->refcnt++; + spin_unlock(&drvdata->spinlock); + + return 0; +} + +static void trace_noc_disable_hw(struct trace_noc_drvdata *drvdata) +{ + writel_relaxed(0x0, drvdata->base + TRACE_NOC_CTRL); + dev_dbg(drvdata->dev, "Trace NOC is disabled\n"); +} + +static void trace_noc_disable(struct coresight_device *csdev, struct coresight_connection *inport, + struct coresight_connection *outport) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (--csdev->refcnt == 0) + trace_noc_disable_hw(drvdata); + + spin_unlock(&drvdata->spinlock); + dev_info(drvdata->dev, "Trace NOC is disabled\n"); +} + +static const struct coresight_ops_link trace_noc_link_ops = { + .enable = trace_noc_enable, + .disable = trace_noc_disable, +}; + +static const struct coresight_ops trace_noc_cs_ops = { + .link_ops = &trace_noc_link_ops, +}; + +static int trace_noc_init_default_data(struct trace_noc_drvdata *drvdata) +{ + int atid; + + atid = coresight_trace_id_get_system_id(); + if (atid < 0) + return atid; + + drvdata->atid = atid; + + drvdata->freq_type = FREQ_TS; + drvdata->flag_type = FLAG; + drvdata->freq_req_val = 0; + + return 0; +} + +static int trace_noc_probe(struct amba_device *adev, const struct amba_id *id) +{ + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata; + struct trace_noc_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + int ret; + + desc.name = coresight_alloc_device_name(&trace_noc_devs, dev); + if (!desc.name) + return -ENOMEM; + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base = devm_ioremap_resource(dev, &adev->res); + if (!drvdata->base) + return -ENOMEM; + + spin_lock_init(&drvdata->spinlock); + + ret = trace_noc_init_default_data(drvdata); + if (ret) + return ret; + + desc.ops = &trace_noc_cs_ops; + desc.type = CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.pdata = adev->dev.platform_data; + desc.dev = &adev->dev; + desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + pm_runtime_put(&adev->dev); + + return 0; +} + +static void trace_noc_remove(struct amba_device *adev) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_trace_id_put_system_id(drvdata->atid); + coresight_unregister(drvdata->csdev); +} + +static struct amba_id trace_noc_ids[] = { + { + .id = 0x000f0c00, + .mask = 0x000fff00, + }, + {}, +}; +MODULE_DEVICE_TABLE(amba, trace_noc_ids); + +static struct amba_driver trace_noc_driver = { + .drv = { + .name = "coresight-trace-noc", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = trace_noc_probe, + .remove = trace_noc_remove, + .id_table = trace_noc_ids, +}; + +module_amba_driver(trace_noc_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Trace NOC driver"); diff --git a/drivers/hwtracing/coresight/coresight-tnoc.h b/drivers/hwtracing/coresight/coresight-tnoc.h new file mode 100644 index 0000000000000000000000000000000000000000..b6bd1ef659897d8e0994c5e8514e8cbdd16eebd8 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tnoc.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define TRACE_NOC_CTRL 0x008 +#define TRACE_NOC_XLD 0x010 +#define TRACE_NOC_FREQVAL 0x018 +#define TRACE_NOC_SYNCR 0x020 + +/* Enable generation of output ATB traffic.*/ +#define TRACE_NOC_CTRL_PORTEN BIT(0) +/* Writing 1 to issue a FREQ or FREQ_TS packet*/ +#define TRACE_NOC_CTRL_FREQTSREQ BIT(5) +/* Sets the type of issued ATB FLAG packets. 0: 'FLAG' packets; 1: 'FLAG_TS' packets.*/ +#define TRACE_NOC_CTRL_FLAGTYPE BIT(7) +/* sets the type of issued ATB FREQ packets. 0: 'FREQ' packets; 1: 'FREQ_TS' packets.*/ +#define TRACE_NOC_CTRL_FREQTYPE BIT(8) +DEFINE_CORESIGHT_DEVLIST(trace_noc_devs, "traceNoc"); + +/** + * struct trace_noc_drvdata - specifics associated to a trace noc component + * @base: memory mapped base address for this component. + * @dev: device node for trace_noc_drvdata. + * @csdev: component vitals needed by the framework. + * @spinlock: only one at a time pls. + * @atid: id for the trace packet. + * @freqtype: 0: 'FREQ' packets; 1: 'FREQ_TS' packets. + * @flagtype: 0: 'FLAG' packets; 1: 'FLAG_TS' packets. + * @freq_req_val: set frequency values carried by 'FREQ' and 'FREQ_TS' packets. + */ +struct trace_noc_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; /* lock for the drvdata. */ + u32 atid; + u32 freq_type; + u32 flag_type; + u32 freq_req_val; +}; + +/* freq type */ +enum freq_type { + FREQ, + FREQ_TS, +}; + +/* flag type */ +enum flag_type { + FLAG, + FLAG_TS, +}; From patchwork Wed Feb 26 11:05:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanfang Zhang X-Patchwork-Id: 13992412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9FD06C021BF for ; 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1: sequence has been completed. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tnoc.c | 73 ++++++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.h | 4 ++ 2 files changed, 77 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c index fad8e61f05ef25989aba1be342c547f835e8953a..20231f28ddcb6a60d9b3c1ca3e0ca4d731dac39c 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -16,6 +16,78 @@ #include "coresight-tnoc.h" #include "coresight-trace-id.h" +static ssize_t flush_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct coresight_device *csdev = drvdata->csdev; + unsigned long val; + u32 reg; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + if (val != 1) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (csdev->refcnt == 0) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + reg = readl_relaxed(drvdata->base + TRACE_NOC_CTRL); + reg = reg | TRACE_NOC_CTRL_FLUSHREQ; + writel_relaxed(reg, drvdata->base + TRACE_NOC_CTRL); + + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_WO(flush_req); + +/* + * flush-sequence status: + * value 0: sequence in progress; + * value 1: sequence has been completed. + */ +static ssize_t flush_status_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct coresight_device *csdev = drvdata->csdev; + u32 val; + + spin_lock(&drvdata->spinlock); + if (csdev->refcnt == 0) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + val = readl_relaxed(drvdata->base + TRACE_NOC_CTRL); + spin_unlock(&drvdata->spinlock); + return sysfs_emit(buf, "%lu\n", BMVAL(val, 2, 2)); +} +static DEVICE_ATTR_RO(flush_status); + +static struct attribute *trace_noc_attrs[] = { + &dev_attr_flush_req.attr, + &dev_attr_flush_status.attr, + NULL, +}; + +static struct attribute_group trace_noc_attr_grp = { + .attrs = trace_noc_attrs, +}; + +static const struct attribute_group *trace_noc_attr_grps[] = { + &trace_noc_attr_grp, + NULL, +}; + static void trace_noc_enable_hw(struct trace_noc_drvdata *drvdata) { u32 val; @@ -142,6 +214,7 @@ static int trace_noc_probe(struct amba_device *adev, const struct amba_id *id) return ret; desc.ops = &trace_noc_cs_ops; + desc.groups = trace_noc_attr_grps; desc.type = CORESIGHT_DEV_TYPE_LINK; desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG; desc.pdata = adev->dev.platform_data; diff --git a/drivers/hwtracing/coresight/coresight-tnoc.h b/drivers/hwtracing/coresight/coresight-tnoc.h index b6bd1ef659897d8e0994c5e8514e8cbdd16eebd8..d0fe8f52709ff4147d66dbf90987595012cfaa4e 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.h +++ b/drivers/hwtracing/coresight/coresight-tnoc.h @@ -10,6 +10,10 @@ /* Enable generation of output ATB traffic.*/ #define TRACE_NOC_CTRL_PORTEN BIT(0) +/* Writing 1 to initiate a flush sequence.*/ +#define TRACE_NOC_CTRL_FLUSHREQ BIT(1) +/* 0: sequence in progress; 1: sequence has been completed.*/ +#define TRACE_NOC_CTRL_FLUSHSTATUS BIT(2) /* Writing 1 to issue a FREQ or FREQ_TS packet*/ #define TRACE_NOC_CTRL_FREQTSREQ BIT(5) /* Sets the type of issued ATB FLAG packets. 0: 'FLAG' packets; 1: 'FLAG_TS' packets.*/ From patchwork Wed Feb 26 11:05:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yuanfang Zhang X-Patchwork-Id: 13992410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54AF2C021B8 for ; Wed, 26 Feb 2025 13:25:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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1: 'FLAG_TS' packets. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tnoc.c | 42 +++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c index 20231f28ddcb6a60d9b3c1ca3e0ca4d731dac39c..ad973749250644760adc4dfd855240026d0a744c 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -26,7 +26,7 @@ static ssize_t flush_req_store(struct device *dev, unsigned long val; u32 reg; - if (kstrtoul(buf, 10, &val)) + if (kstrtoul(buf, 0, &val)) return -EINVAL; if (val != 1) @@ -73,9 +73,49 @@ static ssize_t flush_status_show(struct device *dev, } static DEVICE_ATTR_RO(flush_status); +/* + * Sets the type of issued ATB FLAG packets: + * 0: 'FLAG' packets; + * 1: 'FLAG_TS' packets. + */ +static ssize_t flag_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + if (val != 1 && val != 0) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->flag_type = FLAG_TS; + else + drvdata->flag_type = FLAG; + spin_unlock(&drvdata->spinlock); + + return size; +} + +static ssize_t flag_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", drvdata->flag_type); +} +static DEVICE_ATTR_RW(flag_type); + static struct attribute *trace_noc_attrs[] = { &dev_attr_flush_req.attr, &dev_attr_flush_status.attr, + &dev_attr_flag_type.attr, NULL, }; From patchwork Wed Feb 26 11:05:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanfang Zhang X-Patchwork-Id: 13992411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7E43C19778 for ; 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Wed, 26 Feb 2025 11:06:42 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51QB6bcX013117 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Feb 2025 11:06:37 GMT Received: from yuanfang4-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Feb 2025 03:06:31 -0800 From: Yuanfang Zhang Date: Wed, 26 Feb 2025 19:05:54 +0800 Subject: [PATCH v2 5/5] coresight-tnoc: add nodes to configure freq packet MIME-Version: 1.0 Message-ID: <20250226-trace-noc-driver-v2-5-8afc6584afc5@quicinc.com> References: <20250226-trace-noc-driver-v2-0-8afc6584afc5@quicinc.com> In-Reply-To: <20250226-trace-noc-driver-v2-0-8afc6584afc5@quicinc.com> To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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1: 'FREQ_TS' packets. 2. freq_req_val: used to set frequency values carried by 'FREQ' and 'FREQ_TS' packets. 3. freq_ts_req: writing '1' to issue a 'FREQ' or 'FREQ_TS' packet. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tnoc.c | 97 ++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c index ad973749250644760adc4dfd855240026d0a744c..24b1add4c921866b944d756e563d50b4172d583a 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -112,10 +112,107 @@ static ssize_t flag_type_show(struct device *dev, } static DEVICE_ATTR_RW(flag_type); +static ssize_t freq_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", drvdata->freq_type); +} + +static ssize_t freq_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val != 1 && val != 0) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->freq_type = FREQ_TS; + else + drvdata->freq_type = FREQ; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_RW(freq_type); + +static ssize_t freq_req_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", drvdata->freq_req_val); +} + +static ssize_t freq_req_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val) { + spin_lock(&drvdata->spinlock); + drvdata->freq_req_val = val; + spin_unlock(&drvdata->spinlock); + } + + return size; +} +static DEVICE_ATTR_RW(freq_req_val); + +static ssize_t freq_ts_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct coresight_device *csdev = drvdata->csdev; + unsigned long val; + u32 reg; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (csdev->refcnt == 0) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + if (val) { + reg = readl_relaxed(drvdata->base + TRACE_NOC_CTRL); + reg = reg | TRACE_NOC_CTRL_FREQTSREQ; + writel_relaxed(reg, drvdata->base + TRACE_NOC_CTRL); + } + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_WO(freq_ts_req); + static struct attribute *trace_noc_attrs[] = { &dev_attr_flush_req.attr, &dev_attr_flush_status.attr, &dev_attr_flag_type.attr, + &dev_attr_freq_type.attr, + &dev_attr_freq_req_val.attr, + &dev_attr_freq_ts_req.attr, NULL, };