From patchwork Wed Feb 26 19:58:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ma=C3=ADra_Canal?= X-Patchwork-Id: 13993095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B20F7C021B8 for ; Wed, 26 Feb 2025 19:59:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 82E1710E2F8; Wed, 26 Feb 2025 19:59:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=igalia.com header.i=@igalia.com header.b="Kt1eAYtW"; dkim-atps=neutral Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by gabe.freedesktop.org (Postfix) with ESMTPS id 65B5910E2F8 for ; Wed, 26 Feb 2025 19:59:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=e9Cn6ByLPah154+p0cfCiGDTEchGM+HAhFQn+4UWbM0=; b=Kt1eAYtWfvnnI23KtV0iD+g6oy 8onJGhgbsCEHMnR5ZQ8tPW/B4gV0aKJZ3T5xvqEA6/ts6VDNWQfX9rhGd7aVhUCfLugDMaDXc50+j j9toaLaAdugnRUE0u4GN/FZtE20sDhSGFicFYHR5RWIFUuizXFYpRDsgK2vw/EiKKQfnxI1kLQmA4 tRWkxQ1jNQ99sK4VZVFHqrGAS+iW8YT6VlQE6bgzBeqm0GdJcmG7esQTZXPRfmZ39fkWN6bXKowXd Y1BgrKIJUHMzXubzywy6w31WK4iHhdtVSF0mQXdvrOZ+RwOXeJFjCDKZOrKBv8lmjmBNmZ1f61qvR 7QaQpZ5g==; Received: from [187.36.213.55] (helo=1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1tnNZ3-0019lA-HS; Wed, 26 Feb 2025 20:59:35 +0100 From: =?utf-8?q?Ma=C3=ADra_Canal?= Date: Wed, 26 Feb 2025 16:58:59 -0300 Subject: [PATCH 1/6] drm/v3d: Don't run jobs that have errors flagged in its fence MIME-Version: 1.0 Message-Id: <20250226-v3d-gpu-reset-fixes-v1-1-83a969fdd9c1@igalia.com> References: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> In-Reply-To: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> To: Melissa Wen , Iago Toral , Jose Maria Casanova Crespo Cc: dri-devel@lists.freedesktop.org, kernel-dev@igalia.com, stable@vger.kernel.org, =?utf-8?q?Ma=C3=ADra_Canal?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2147; i=mcanal@igalia.com; h=from:subject:message-id; bh=bUryKYLtnN/BEwb4kNwZZ92cWDNa8JE7Wj0Szh70uSc=; b=owEBbQGS/pANAwAIAT/zDop2iPqqAcsmYgBnv3KfDfDWWj8qczEVtu3v+dkTMoqFXTQVzUUFH UtCIkSXjbSJATMEAAEIAB0WIQT45F19ARZ3Bymmd9E/8w6Kdoj6qgUCZ79ynwAKCRA/8w6Kdoj6 qpuJCACN80fHtqEHQF75lH1xT/V+7c1yD4OjYWK2HmI+sC+18Ym7S8TL1iacNyZBKCR8RvRFGXs Yx+iwD85dJL/CfhxkIiD0dz7oNXAe1bTW1ufJvITwtlWnZQib02D/GAKAQxddrT2cf1yCzIBg5z EG/dvC8wQzqD/mr0yV7TM2rhsYueKv7LRgWx1L0aBlkM2SfYVzEYi0e1WCi2XLpNYbgc43j+3Uv 9xi48TEdQoj8ggOwCjbtg2xeceOsBCCoVMl/J/Q7DXuKDd0NVakusK6vi3raZqUcPQuJrC1n3u3 vTpU+tH5MEeSMM416QXJGJr3TS5FQ2I3GqXvg+T4TyjSVCwR X-Developer-Key: i=mcanal@igalia.com; a=openpgp; fpr=F8E45D7D0116770729A677D13FF30E8A7688FAAA X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The V3D driver still relies on `drm_sched_increase_karma()` and `drm_sched_resubmit_jobs()` for resubmissions when a timeout occurs. The function `drm_sched_increase_karma()` marks the job as guilty, while `drm_sched_resubmit_jobs()` sets an error (-ECANCELED) in the DMA fence of that guilty job. Because of this, we must check whether the job’s DMA fence has been flagged with an error before executing the job. Otherwise, the same guilty job may be resubmitted indefinitely, causing repeated GPU resets. This patch adds a check for an error on the job's fence to prevent running a guilty job that was previously flagged when the GPU timed out. Note that the CPU and CACHE_CLEAN queues do not require this check, as their jobs are executed synchronously once the DRM scheduler starts them. Cc: stable@vger.kernel.org Fixes: d223f98f0209 ("drm/v3d: Add support for compute shader dispatch.") Fixes: 1584f16ca96e ("drm/v3d: Add support for submitting jobs to the TFU.") Signed-off-by: Maíra Canal --- drivers/gpu/drm/v3d/v3d_sched.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c index 80466ce8c7df669280e556c0793490b79e75d2c7..c2010ecdb08f4ba3b54f7783ed33901552d0eba1 100644 --- a/drivers/gpu/drm/v3d/v3d_sched.c +++ b/drivers/gpu/drm/v3d/v3d_sched.c @@ -327,11 +327,15 @@ v3d_tfu_job_run(struct drm_sched_job *sched_job) struct drm_device *dev = &v3d->drm; struct dma_fence *fence; + if (unlikely(job->base.base.s_fence->finished.error)) + return NULL; + + v3d->tfu_job = job; + fence = v3d_fence_create(v3d, V3D_TFU); if (IS_ERR(fence)) return NULL; - v3d->tfu_job = job; if (job->base.irq_fence) dma_fence_put(job->base.irq_fence); job->base.irq_fence = dma_fence_get(fence); @@ -369,6 +373,9 @@ v3d_csd_job_run(struct drm_sched_job *sched_job) struct dma_fence *fence; int i, csd_cfg0_reg; + if (unlikely(job->base.base.s_fence->finished.error)) + return NULL; + v3d->csd_job = job; v3d_invalidate_caches(v3d); From patchwork Wed Feb 26 19:59:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ma=C3=ADra_Canal?= X-Patchwork-Id: 13993094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C33F0C021B8 for ; Wed, 26 Feb 2025 19:59:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C5F710E2F2; Wed, 26 Feb 2025 19:59:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=igalia.com header.i=@igalia.com header.b="nbv3h4GV"; dkim-atps=neutral Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by gabe.freedesktop.org (Postfix) with ESMTPS id E140B10E9D1 for ; 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Wed, 26 Feb 2025 20:59:38 +0100 From: =?utf-8?q?Ma=C3=ADra_Canal?= Date: Wed, 26 Feb 2025 16:59:00 -0300 Subject: [PATCH 2/6] drm/v3d: Set job pointer to NULL when the job's fence has an error MIME-Version: 1.0 Message-Id: <20250226-v3d-gpu-reset-fixes-v1-2-83a969fdd9c1@igalia.com> References: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> In-Reply-To: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> To: Melissa Wen , Iago Toral , Jose Maria Casanova Crespo Cc: dri-devel@lists.freedesktop.org, kernel-dev@igalia.com, =?utf-8?q?Ma?= =?utf-8?q?=C3=ADra_Canal?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2786; i=mcanal@igalia.com; h=from:subject:message-id; bh=akT7R3rJ6Uf368r0WfvgEH8YcbaEI+Q1q0VGx+/dWPQ=; b=owEBbQGS/pANAwAIAT/zDop2iPqqAcsmYgBnv3KfUQ2tvdNWbOy4Fe3R7YGNyzrAL7m8b6av1 nlAqtKESBCJATMEAAEIAB0WIQT45F19ARZ3Bymmd9E/8w6Kdoj6qgUCZ79ynwAKCRA/8w6Kdoj6 qmnCCACh+P9jocUUk/1zZC8HFcpDDJuLtHN8KK205tAnc3J3Lba7FR+RBPDRkn1QAgD/xKYZDxi cel7Q7SiGS5aRGeLWp38a/y0hhhqJQDEqM1MZGENcNF/JiBWsFdzlQ8zYdrPuID3qRFyQwI0XqR uly7ZXUnYDH9dIuD5lvM7QSfKc9CIs17UFGdbPoFRFydXPGfuNoeyTyai+NcH4/7pIJsZMQmY2u RYXSQijwqQ35OjKq/wP9/xi9cyPjb4oLwnigSGIgAfSO/amoHT+BAjUkXUKhUEQfizLUcLbf1wj QUNrCLXLURRIG7OSi0v3g1za9xXw3w7dTxryMSAyaRgvaN0J X-Developer-Key: i=mcanal@igalia.com; a=openpgp; fpr=F8E45D7D0116770729A677D13FF30E8A7688FAAA X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Similar to commit e4b5ccd392b9 ("drm/v3d: Ensure job pointer is set to NULL after job completion"), ensure the job pointer is set to `NULL` when a job's fence has an error. Failing to do so can trigger kernel warnings in specific scenarios, such as: 1. v3d_csd_job_run() assigns `v3d->csd_job = job` 2. CSD job exceeds hang limit, causing a timeout → v3d_gpu_reset_for_timeout() 3. GPU reset 4. drm_sched_resubmit_jobs() sets the job's fence to `-ECANCELED`. 5. v3d_csd_job_run() detects the fence error and returns NULL, not submitting the job to the GPU 6. User-space runs `modprobe -r v3d` 7. v3d_gem_destroy() v3d_gem_destroy() triggers a warning indicating that the CSD job never ended, as we didn't set `v3d->csd_job` to NULL after the timeout. The same can also happen to BIN, RENDER, and TFU jobs. Signed-off-by: Maíra Canal --- drivers/gpu/drm/v3d/v3d_sched.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c index c2010ecdb08f4ba3b54f7783ed33901552d0eba1..34c42d6e12cde656d3b51a18be324976199eceae 100644 --- a/drivers/gpu/drm/v3d/v3d_sched.c +++ b/drivers/gpu/drm/v3d/v3d_sched.c @@ -226,8 +226,12 @@ static struct dma_fence *v3d_bin_job_run(struct drm_sched_job *sched_job) struct dma_fence *fence; unsigned long irqflags; - if (unlikely(job->base.base.s_fence->finished.error)) + if (unlikely(job->base.base.s_fence->finished.error)) { + spin_lock_irqsave(&v3d->job_lock, irqflags); + v3d->bin_job = NULL; + spin_unlock_irqrestore(&v3d->job_lock, irqflags); return NULL; + } /* Lock required around bin_job update vs * v3d_overflow_mem_work(). @@ -281,8 +285,10 @@ static struct dma_fence *v3d_render_job_run(struct drm_sched_job *sched_job) struct drm_device *dev = &v3d->drm; struct dma_fence *fence; - if (unlikely(job->base.base.s_fence->finished.error)) + if (unlikely(job->base.base.s_fence->finished.error)) { + v3d->render_job = NULL; return NULL; + } v3d->render_job = job; @@ -327,8 +333,10 @@ v3d_tfu_job_run(struct drm_sched_job *sched_job) struct drm_device *dev = &v3d->drm; struct dma_fence *fence; - if (unlikely(job->base.base.s_fence->finished.error)) + if (unlikely(job->base.base.s_fence->finished.error)) { + v3d->tfu_job = NULL; return NULL; + } v3d->tfu_job = job; @@ -373,8 +381,10 @@ v3d_csd_job_run(struct drm_sched_job *sched_job) struct dma_fence *fence; int i, csd_cfg0_reg; - if (unlikely(job->base.base.s_fence->finished.error)) + if (unlikely(job->base.base.s_fence->finished.error)) { + v3d->csd_job = NULL; return NULL; + } v3d->csd_job = job; From patchwork Wed Feb 26 19:59:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ma=C3=ADra_Canal?= X-Patchwork-Id: 13993097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13C3BC021B8 for ; Wed, 26 Feb 2025 19:59:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EED2E10E9D2; Wed, 26 Feb 2025 19:59:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=igalia.com header.i=@igalia.com header.b="cfdF0/KH"; dkim-atps=neutral Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by gabe.freedesktop.org (Postfix) with ESMTPS id 83B7310E9D2 for ; Wed, 26 Feb 2025 19:59:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=86JPmdxwe2LsA/nl1WU6ceGnFYY2LrlCANZO1hLIr/Y=; b=cfdF0/KHjGeAZXqNQ36ClFSjxO 548V/PLHC+zWWMJoYLLM5xSZTMmdo9WIfOI++cZ5Ko/5LKeuI7WHa+vIjcWZRsRSLk7UyJeM0zPKF BjssTQ2sIJd+3V4BTEmuRwrF6QXujbb+MxADWw5aJSskOJ73LcKnAP6Zm+A8N6yYoJwn9ArtlmbSM MrQE6lcRC0zpr1tJ4mowH5kS6gc8pNVlzJYKuEc7us+5iWE3I8X58eAPpzqzokbNnn9pFsIYFzyf4 QKZYuFy7MbphpYgrLZYIA9vji6a+idHoB71SwSHGCbRkxr+QAAJzE4Lu4adSDEQhCtVDKW3j4CGGy +SbgqebA==; Received: from [187.36.213.55] (helo=1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1tnNZ8-0019lA-PU; Wed, 26 Feb 2025 20:59:40 +0100 From: =?utf-8?q?Ma=C3=ADra_Canal?= Date: Wed, 26 Feb 2025 16:59:01 -0300 Subject: [PATCH 3/6] drm/v3d: Associate a V3D tech revision to all supported devices MIME-Version: 1.0 Message-Id: <20250226-v3d-gpu-reset-fixes-v1-3-83a969fdd9c1@igalia.com> References: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> In-Reply-To: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> To: Melissa Wen , Iago Toral , Jose Maria Casanova Crespo Cc: dri-devel@lists.freedesktop.org, kernel-dev@igalia.com, =?utf-8?q?Ma?= =?utf-8?q?=C3=ADra_Canal?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3506; i=mcanal@igalia.com; h=from:subject:message-id; bh=RhcwA9JkfBHLo/G3gaQ2ajOhUspmoGHJ05yM61gi4hQ=; b=owEBbQGS/pANAwAIAT/zDop2iPqqAcsmYgBnv3KfbLQzw+EHvd+X5R11bT+NgQax+42wJWGZ4 zMMUP1UMMqJATMEAAEIAB0WIQT45F19ARZ3Bymmd9E/8w6Kdoj6qgUCZ79ynwAKCRA/8w6Kdoj6 qn/yB/wPsi5v5Y1j+shdVMyA/XfOYPBAHMpvW5FJzGS6VvhSREgvFqhNELbmiy2Y2rUwz6f9haP F/8GVO9uhtIgR1dyeQqg/ksWDca2d7oIIzx4QP+ktrFhZhKDqTks4Jd2lOEyf/m0MbcSQizoNy/ BFYjMg7tXuq6AeFr+DpsoxqpSDj661Jqo56pAY4Wm2rvXzSc9vZk4HJQ94XDtOK3Tl8vvNstZ93 A7AIokepnCEQPuK2a8RFdjXYQQtxOH2h/JEXCUbAGTc4Ay7gTZyBZJQa3nhJWii/efaaIlZh4VM uTLUn9TdjpakvUce2sJvjyqFADD50h7U3IkK4SNuMBBBOSEn X-Developer-Key: i=mcanal@igalia.com; a=openpgp; fpr=F8E45D7D0116770729A677D13FF30E8A7688FAAA X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The V3D driver currently determines the GPU tech version (33, 41...) by reading a register. This approach has worked so far since this information wasn’t needed before powering on the GPU. V3D 7.1 introduces new registers that must be written to power on the GPU, requiring us to know the V3D version beforehand. To address this, associate each supported SoC with the corresponding VideoCore GPU version as part of the device data. To prevent possible mistakes, add an assertion to verify that the version specified in the device data matches the one reported by the hardware. If there is a mismatch, the kernel will trigger a warning. Signed-off-by: Maíra Canal --- drivers/gpu/drm/v3d/v3d_drv.c | 18 ++++++++++++++---- drivers/gpu/drm/v3d/v3d_drv.h | 7 +++++++ 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/v3d/v3d_drv.c b/drivers/gpu/drm/v3d/v3d_drv.c index 852015214e971c60f9939d34d893d8d8cb4e9b01..c5e5bec1c72d32128fb16136f136f5fa7f76a6bd 100644 --- a/drivers/gpu/drm/v3d/v3d_drv.c +++ b/drivers/gpu/drm/v3d/v3d_drv.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -254,10 +255,10 @@ static const struct drm_driver v3d_drm_driver = { }; static const struct of_device_id v3d_of_match[] = { - { .compatible = "brcm,2711-v3d" }, - { .compatible = "brcm,2712-v3d" }, - { .compatible = "brcm,7268-v3d" }, - { .compatible = "brcm,7278-v3d" }, + { .compatible = "brcm,2711-v3d", .data = (void *)V3D_GEN_42 }, + { .compatible = "brcm,2712-v3d", .data = (void *)V3D_GEN_71 }, + { .compatible = "brcm,7268-v3d", .data = (void *)V3D_GEN_33 }, + { .compatible = "brcm,7278-v3d", .data = (void *)V3D_GEN_41 }, {}, }; MODULE_DEVICE_TABLE(of, v3d_of_match); @@ -274,6 +275,7 @@ static int v3d_platform_drm_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct drm_device *drm; struct v3d_dev *v3d; + enum v3d_gen gen; int ret; u32 mmu_debug; u32 ident1, ident3; @@ -287,6 +289,9 @@ static int v3d_platform_drm_probe(struct platform_device *pdev) platform_set_drvdata(pdev, drm); + gen = (enum v3d_gen)of_device_get_match_data(dev); + v3d->ver = gen; + ret = map_regs(v3d, &v3d->hub_regs, "hub"); if (ret) return ret; @@ -316,6 +321,11 @@ static int v3d_platform_drm_probe(struct platform_device *pdev) ident1 = V3D_READ(V3D_HUB_IDENT1); v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); + /* Make sure that the V3D tech version retrieved from the HW is equal + * to the one advertised by the device tree. + */ + WARN_ON(v3d->ver != gen); + v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ diff --git a/drivers/gpu/drm/v3d/v3d_drv.h b/drivers/gpu/drm/v3d/v3d_drv.h index 9deaefa0f95b71b842f1c5bef2c6a8a8ffc21fe2..a3a0a4c2e1c354766d6c7dda37d15c4a5e12a637 100644 --- a/drivers/gpu/drm/v3d/v3d_drv.h +++ b/drivers/gpu/drm/v3d/v3d_drv.h @@ -94,6 +94,13 @@ struct v3d_perfmon { u64 values[] __counted_by(ncounters); }; +enum v3d_gen { + V3D_GEN_33 = 33, + V3D_GEN_41 = 41, + V3D_GEN_42 = 42, + V3D_GEN_71 = 71, +}; + struct v3d_dev { struct drm_device drm; From patchwork Wed Feb 26 19:59:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ma=C3=ADra_Canal?= X-Patchwork-Id: 13993098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6992AC021B8 for ; Wed, 26 Feb 2025 19:59:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BACB110E9D3; Wed, 26 Feb 2025 19:59:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; 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As BCM2712 has a V3D 7.1 core, add a new register item to the list. Similar to the GCA and bridge register, SMS is optional and should only be added for V3D 7.1 variants. Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Nicolas Saenz Julienne Cc: devicetree@vger.kernel.org Signed-off-by: Maíra Canal --- Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml index dc078ceeca9ac3447ba54a7c8830821f0b2a7f9f..8a3d3fc6065d7756da141bda4dc522f63be5e9a1 100644 --- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml @@ -27,14 +27,16 @@ properties: - description: core0 register (required) - description: GCA cache controller register (if GCA controller present) - description: bridge register (if no external reset controller) + - description: SMS register (if SMS controller present) minItems: 2 reg-names: items: - const: hub - const: core0 - - enum: [ bridge, gca ] - - enum: [ bridge, gca ] + - enum: [ bridge, gca, sms ] + - enum: [ bridge, gca, sms ] + - enum: [ bridge, gca, sms ] minItems: 2 interrupts: From patchwork Wed Feb 26 19:59:03 2025 Content-Type: text/plain; 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Wed, 26 Feb 2025 20:59:47 +0100 From: =?utf-8?q?Ma=C3=ADra_Canal?= Date: Wed, 26 Feb 2025 16:59:03 -0300 Subject: [PATCH 5/6] drm/v3d: Use V3D_SMS registers for power on/off and reset on V3D 7.x MIME-Version: 1.0 Message-Id: <20250226-v3d-gpu-reset-fixes-v1-5-83a969fdd9c1@igalia.com> References: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> In-Reply-To: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> To: Melissa Wen , Iago Toral , Jose Maria Casanova Crespo Cc: dri-devel@lists.freedesktop.org, kernel-dev@igalia.com, =?utf-8?q?Ma?= =?utf-8?q?=C3=ADra_Canal?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7638; i=mcanal@igalia.com; h=from:subject:message-id; bh=+UCUkPcnJKVBmep1Kpn7g9Ed3qswmSHgp97NYbvsRx8=; b=owEBbQGS/pANAwAIAT/zDop2iPqqAcsmYgBnv3KgNrB0+IDe9lMBrnRSCP9i/78tz7A0CBGZv sCWlEYQPfqJATMEAAEIAB0WIQT45F19ARZ3Bymmd9E/8w6Kdoj6qgUCZ79yoAAKCRA/8w6Kdoj6 qs8CB/90cm2sRL20nxVLVXyvOpaKI3VlswIP0+m9yHIHbYjWcQ2VCXc35uRlHmtlGp3wZMYBS0/ B9noShkQpPmMQi505kGU3N0QZY4DGYz1GsUQ1yeqjNLDL6dXRFvJNY97rigkFuDEl0sUR3b4/4Y Cx5fnqV6zaN3q8wlf6g3NP+rcyqRY7C5IkJk0FuExoTZiZm8LFl85JO6tUJXxfurkLdCOJjqHo/ EVJzYJaGFHHBZJnnzBiBDFNKlMNSLjLzhkBZQoib4sx3XRKrYVj3TAoZVy7jPn1so5rccGqu9+P zV1s0V0xK2JuEcr3IBx7vpWjlKGIwDCJJsjIFy2tOlWokGzk X-Developer-Key: i=mcanal@igalia.com; a=openpgp; fpr=F8E45D7D0116770729A677D13FF30E8A7688FAAA X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In addition to the standard reset controller, V3D 7.x requires configuring the V3D_SMS registers for proper power on/off and reset. Add the new registers to `v3d_regs.h` and ensure they are properly configured during device probing, removal, and reset. This change fixes GPU reset issues on the Raspberry Pi 5 (BCM2712). Without exposing these registers, a GPU reset causes the GPU to hang, stopping any further job execution and freezing the desktop GUI. The same issue occurs when unloading and loading the v3d driver. Link: https://github.com/raspberrypi/linux/issues/6660 Signed-off-by: Maíra Canal --- drivers/gpu/drm/v3d/v3d_drv.c | 40 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/v3d/v3d_drv.h | 11 +++++++++++ drivers/gpu/drm/v3d/v3d_gem.c | 17 +++++++++++++++++ drivers/gpu/drm/v3d/v3d_regs.h | 26 ++++++++++++++++++++++++++ 4 files changed, 94 insertions(+) diff --git a/drivers/gpu/drm/v3d/v3d_drv.c b/drivers/gpu/drm/v3d/v3d_drv.c index c5e5bec1c72d32128fb16136f136f5fa7f76a6bd..d573cb8e79671c95dbb4cde0a6dfc1b94c8874d5 100644 --- a/drivers/gpu/drm/v3d/v3d_drv.c +++ b/drivers/gpu/drm/v3d/v3d_drv.c @@ -263,6 +263,36 @@ static const struct of_device_id v3d_of_match[] = { }; MODULE_DEVICE_TABLE(of, v3d_of_match); +static void +v3d_idle_sms(struct v3d_dev *v3d) +{ + if (v3d->ver < 71) + return; + + V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF); + + if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), + V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) { + DRM_ERROR("Failed to power up SMS\n"); + } + + v3d_reset_sms(v3d); +} + +static void +v3d_power_off_sms(struct v3d_dev *v3d) +{ + if (v3d->ver < 71) + return; + + V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF); + + if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), + V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) { + DRM_ERROR("Failed to power off SMS\n"); + } +} + static int map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) { @@ -300,6 +330,12 @@ static int v3d_platform_drm_probe(struct platform_device *pdev) if (ret) return ret; + if (v3d->ver >= 71) { + ret = map_regs(v3d, &v3d->sms_regs, "sms"); + if (ret) + return ret; + } + v3d->clk = devm_clk_get_optional(dev, NULL); if (IS_ERR(v3d->clk)) return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n"); @@ -310,6 +346,8 @@ static int v3d_platform_drm_probe(struct platform_device *pdev) return ret; } + v3d_idle_sms(v3d); + mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); ret = dma_set_mask_and_coherent(dev, mask); @@ -410,6 +448,8 @@ static void v3d_platform_drm_remove(struct platform_device *pdev) dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); + v3d_power_off_sms(v3d); + clk_disable_unprepare(v3d->clk); } diff --git a/drivers/gpu/drm/v3d/v3d_drv.h b/drivers/gpu/drm/v3d/v3d_drv.h index a3a0a4c2e1c354766d6c7dda37d15c4a5e12a637..be8c71afbe6a3517774f1bac0c9ae4cb2e16417a 100644 --- a/drivers/gpu/drm/v3d/v3d_drv.h +++ b/drivers/gpu/drm/v3d/v3d_drv.h @@ -118,6 +118,7 @@ struct v3d_dev { void __iomem *core_regs[3]; void __iomem *bridge_regs; void __iomem *gca_regs; + void __iomem *sms_regs; struct clk *clk; struct reset_control *reset; @@ -268,6 +269,15 @@ to_v3d_fence(struct dma_fence *fence) #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) +#define V3D_SMS_IDLE 0x0 +#define V3D_SMS_ISOLATING_FOR_RESET 0xa +#define V3D_SMS_RESETTING 0xb +#define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc +#define V3D_SMS_POWER_OFF_STATE 0xd + +#define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset)) +#define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset)) + #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) @@ -546,6 +556,7 @@ struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); /* v3d_gem.c */ int v3d_gem_init(struct drm_device *dev); void v3d_gem_destroy(struct drm_device *dev); +void v3d_reset_sms(struct v3d_dev *v3d); void v3d_reset(struct v3d_dev *v3d); void v3d_invalidate_caches(struct v3d_dev *v3d); void v3d_clean_caches(struct v3d_dev *v3d); diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c index b1e681630ded098de8aee691884368a959443812..325b432dcb5bbd11532ca062f88cf6b41054d055 100644 --- a/drivers/gpu/drm/v3d/v3d_gem.c +++ b/drivers/gpu/drm/v3d/v3d_gem.c @@ -104,6 +104,22 @@ v3d_reset_v3d(struct v3d_dev *v3d) v3d_init_hw_state(v3d); } +void +v3d_reset_sms(struct v3d_dev *v3d) +{ + if (v3d->ver < 71) + return; + + V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE)); + + if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), + V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) && + !(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), + V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) { + DRM_ERROR("Failed to wait for SMS reset\n"); + } +} + void v3d_reset(struct v3d_dev *v3d) { @@ -119,6 +135,7 @@ v3d_reset(struct v3d_dev *v3d) v3d_idle_axi(v3d, 0); v3d_idle_gca(v3d); + v3d_reset_sms(v3d); v3d_reset_v3d(v3d); v3d_mmu_set_page_table(v3d); diff --git a/drivers/gpu/drm/v3d/v3d_regs.h b/drivers/gpu/drm/v3d/v3d_regs.h index 6da3c69082bd6d5954bf88bd9ff2543a5e4e04c4..c1870265eaeecc188afc4f09cf13a5201d3aa1c6 100644 --- a/drivers/gpu/drm/v3d/v3d_regs.h +++ b/drivers/gpu/drm/v3d/v3d_regs.h @@ -515,4 +515,30 @@ # define V3D_ERR_VPAERGS BIT(1) # define V3D_ERR_VPAEABB BIT(0) +#define V3D_SMS_REE_CS 0x00000 +#define V3D_SMS_TEE_CS 0x00400 +# define V3D_SMS_INTERRUPT BIT(31) +# define V3D_SMS_POWER_OFF BIT(30) +# define V3D_SMS_CLEAR_POWER_OFF BIT(29) +# define V3D_SMS_LOCK BIT(28) +# define V3D_SMS_CLEAR_LOCK BIT(27) +# define V3D_SMS_SVP_MODE_EXIT BIT(26) +# define V3D_SMS_CLEAR_SVP_MODE_EXIT BIT(25) +# define V3D_SMS_SVP_MODE_ENTER BIT(24) +# define V3D_SMS_CLEAR_SVP_MODE_ENTER BIT(23) +# define V3D_SMS_THEIR_MODE_EXIT BIT(22) +# define V3D_SMS_THEIR_MODE_ENTER BIT(21) +# define V3D_SMS_OUR_MODE_EXIT BIT(20) +# define V3D_SMS_CLEAR_OUR_MODE_EXIT BIT(19) +# define V3D_SMS_SEQ_PC_MASK V3D_MASK(16, 10) +# define V3D_SMS_SEQ_PC_SHIFT 10 +# define V3D_SMS_HUBCORE_STATUS_MASK V3D_MASK(9, 8) +# define V3D_SMS_HUBCORE_STATUS_SHIFT 8 +# define V3D_SMS_NEW_MODE_MASK V3D_MASK(7, 6) +# define V3D_SMS_NEW_MODE_SHIFT 6 +# define V3D_SMS_OLD_MODE_MASK V3D_MASK(5, 4) +# define V3D_SMS_OLD_MODE_SHIFT 4 +# define V3D_SMS_STATE_MASK V3D_MASK(3, 0) +# define V3D_SMS_STATE_SHIFT 0 + #endif /* V3D_REGS_H */ From patchwork Wed Feb 26 19:59:04 2025 Content-Type: text/plain; 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Wed, 26 Feb 2025 20:59:50 +0100 From: =?utf-8?q?Ma=C3=ADra_Canal?= Date: Wed, 26 Feb 2025 16:59:04 -0300 Subject: [PATCH 6/6] dt-bindings: gpu: Add V3D driver maintainer as DT maintainer MIME-Version: 1.0 Message-Id: <20250226-v3d-gpu-reset-fixes-v1-6-83a969fdd9c1@igalia.com> References: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> In-Reply-To: <20250226-v3d-gpu-reset-fixes-v1-0-83a969fdd9c1@igalia.com> To: Melissa Wen , Iago Toral , Jose Maria Casanova Crespo Cc: dri-devel@lists.freedesktop.org, kernel-dev@igalia.com, Krzysztof Kozlowski , Conor Dooley , Nicolas Saenz Julienne , devicetree@vger.kernel.org, =?utf-8?q?Ma=C3=ADra_Canal?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1238; i=mcanal@igalia.com; h=from:subject:message-id; bh=57fWKRv9+K7Vas+bEJyhapzSfgJcdRPGqr3tqBM82Zg=; b=owEBbQGS/pANAwAIAT/zDop2iPqqAcsmYgBnv3KgEVanEDW/Nd/cRsQoEfYNCfMZBzusBsdpj XC/1uwLx6+JATMEAAEIAB0WIQT45F19ARZ3Bymmd9E/8w6Kdoj6qgUCZ79yoAAKCRA/8w6Kdoj6 qmUoB/0bN+M6JtKkdudMiF3Pd2DFa44dcovElPqf5apNG8YcLrPSlEa8b54nibgNrKMpwhvOzsS fE6UloG4dk+xVndJCogoJwreQbBk9D8BaVD22qrGG/UZ1OyrQaaDDzj00nLOn6J4BWROagvsJAP MnJtySZR+ZO9nxX5iw5v9JsNbafrCTbqgKsILA3kjwoG5jocVXP+6zEgCiBLyqeybDaPH0jKVTT EZe3BLEzd8Wggu1+ClCLYYWpB2c/+gPjeafB+6OJBrAtRhsyUmNZAqdiGmMm7w8YU9CUozkRwcx +0dpDtZiK8ZwbZqf4Cs8v9RblLdWKxjnun44uE0MhPMUp77o X-Developer-Key: i=mcanal@igalia.com; a=openpgp; fpr=F8E45D7D0116770729A677D13FF30E8A7688FAAA X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" As established in commit 89d04995f76c ("MAINTAINERS: Drop Emma Anholt from all M lines."), Emma is no longer active in the Linux kernel and dropped the V3D maintainership. Therefore, remove Emma as one of the DT maintainers and add the current V3D driver maintainer. Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: Nicolas Saenz Julienne Cc: devicetree@vger.kernel.org Signed-off-by: Maíra Canal --- Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml index 8a3d3fc6065d7756da141bda4dc522f63be5e9a1..13eaa1a40485153eea0e5d4bb164009d1030e314 100644 --- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Broadcom V3D GPU maintainers: - - Eric Anholt + - Maíra Canal - Nicolas Saenz Julienne properties: