From patchwork Wed Feb 26 12:18:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13993388 X-Patchwork-Delegate: bhelgaas@google.com Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B50B34C7C for ; Thu, 27 Feb 2025 00:50:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.0.225.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740617448; cv=none; b=J1T1/tU2bErOIrQpTYp3BsFPr8EGi9ekvZNwcAfkMCtXz94BFPZUlaz6A8cEQGit0ur7WkVH/eElqJd8xEf21Vnw4687k+NBT3XXZowTnVlhqut8UW1Svbpytd0GGz17C+d2YqSB49o8A51EdFfhihgmNQTKet1GF29VqM8A2Dk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740617448; c=relaxed/simple; bh=j5VlhD8OttG1TFi5AuCSDRzNMFwzhmW3UW7rDA921z8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rcQGCRSFU7QjLDFKjZCmrFEWSs5XR654AkqOeJhr0H0OBM0cCHEpLzDDzyhpPybosh5Td+kDz+l7CFJygRri90no4qbiyG+BgaUcNJ6xond9Qa8wyKECXsu9YYdbBYx1zCFIIrYdI25c7tnVlp2V3fCuJvxB8FJQWCJEZ0UZ0oI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com; spf=pass smtp.mailfrom=zhaoxin.com; arc=none smtp.client-ip=210.0.225.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1740616659-086e23601815e2e0001-0c9NHn Received: from ZXSHMBX1.zhaoxin.com (ZXSHMBX1.zhaoxin.com [10.28.252.163]) by mx1.zhaoxin.com with ESMTP id lLmKaKwFdinfIM7V (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Thu, 27 Feb 2025 08:37:40 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from ZXSHMBX2.zhaoxin.com (10.28.252.164) by ZXSHMBX1.zhaoxin.com (10.28.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.44; Thu, 27 Feb 2025 08:37:39 +0800 Received: from ZXSHMBX2.zhaoxin.com ([fe80::4dfc:4f6a:c0cf:4298]) by ZXSHMBX2.zhaoxin.com ([fe80::4dfc:4f6a:c0cf:4298%4]) with mapi id 15.01.2507.044; Thu, 27 Feb 2025 08:37:39 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from xin.lan (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Feb 2025 20:18:46 +0800 From: LeoLiu-oc To: , , , , , , , , , , , , CC: , , , , LeoLiuoc Subject: [PATCH v5 1/4] ACPI: APEI: Move apei_hest_parse() to apei.h Date: Wed, 26 Feb 2025 20:18:35 +0800 X-ASG-Orig-Subj: [PATCH v5 1/4] ACPI: APEI: Move apei_hest_parse() to apei.h Message-ID: <20250226121838.364533-2-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226121838.364533-1-LeoLiu-oc@zhaoxin.com> References: <20250226121838.364533-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 2/27/2025 8:37:38 AM X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1740616659 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1238 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.137757 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc Remove static from apei_hest_parse() so that it can be called in another file. Signed-off-by: LeoLiuoc --- drivers/acpi/apei/hest.c | 2 +- include/acpi/apei.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/apei/hest.c b/drivers/acpi/apei/hest.c index 20d757687e3d..35d08f4e50e6 100644 --- a/drivers/acpi/apei/hest.c +++ b/drivers/acpi/apei/hest.c @@ -134,7 +134,7 @@ static bool is_ghes_assist_struct(struct acpi_hest_header *hest_hdr) typedef int (*apei_hest_func_t)(struct acpi_hest_header *hest_hdr, void *data); -static int apei_hest_parse(apei_hest_func_t func, void *data) +int apei_hest_parse(apei_hest_func_t func, void *data) { struct acpi_hest_header *hest_hdr; int i, rc, len; diff --git a/include/acpi/apei.h b/include/acpi/apei.h index dc60f7db5524..b79976daa4bb 100644 --- a/include/acpi/apei.h +++ b/include/acpi/apei.h @@ -33,6 +33,8 @@ void __init acpi_ghes_init(void); static inline void acpi_ghes_init(void) { } #endif +int apei_hest_parse(apei_hest_func_t func, void *data); + #ifdef CONFIG_ACPI_APEI void __init acpi_hest_init(void); #else From patchwork Wed Feb 26 12:18:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13993362 X-Patchwork-Delegate: bhelgaas@google.com Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [61.152.208.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A245B270058 for ; Thu, 27 Feb 2025 00:37:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=61.152.208.219 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740616675; cv=none; b=fnQZ7Ng+1F6zTeZaExGYbEo7mIh35CYLJwvM88TWwhU097tJvLMji5NVVsX6YaBXFkEUeCemEjArbNaFjC5watDAVDkGBs2yarSKbtKNoUhQxM5ggFyOADFqC+Car/t90D4wBVtA4KlVP3LS+o2GmXw29znm1j6C0Aben8jyhqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740616675; c=relaxed/simple; bh=xf6aa909pkiri3/XbRp02yuy6janMrg6fh9L8J/CqZg=; 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Thu, 27 Feb 2025 08:37:41 +0800 Received: from ZXSHMBX2.zhaoxin.com ([fe80::4dfc:4f6a:c0cf:4298]) by ZXSHMBX2.zhaoxin.com ([fe80::4dfc:4f6a:c0cf:4298%4]) with mapi id 15.01.2507.044; Thu, 27 Feb 2025 08:37:41 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from xin.lan (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Feb 2025 20:18:54 +0800 From: LeoLiu-oc To: , , , , , , , , , , , , CC: , , , , LeoLiuoc Subject: [PATCH v5 2/4] ACPI: APEI: Add new hest_parse_pcie_aer() Date: Wed, 26 Feb 2025 20:18:36 +0800 X-ASG-Orig-Subj: [PATCH v5 2/4] ACPI: APEI: Add new hest_parse_pcie_aer() Message-ID: <20250226121838.364533-3-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226121838.364533-1-LeoLiu-oc@zhaoxin.com> References: <20250226121838.364533-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 2/27/2025 8:37:40 AM X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1740616661 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 3598 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.137756 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc The purpose of the function apei_hest_parse_aer() is used to parse and extract register value from HEST PCIe AER structures. This applies to all hardware platforms that has a PCI Express AER structure in HEST. Signed-off-by: LeoLiuoc --- drivers/acpi/apei/hest.c | 52 +++++++++++++++++++++++++++++++++++++++- include/acpi/apei.h | 11 +++++++++ 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/apei/hest.c b/drivers/acpi/apei/hest.c index 35d08f4e50e6..e7a15d60ecc1 100644 --- a/drivers/acpi/apei/hest.c +++ b/drivers/acpi/apei/hest.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -132,7 +133,56 @@ static bool is_ghes_assist_struct(struct acpi_hest_header *hest_hdr) return false; } -typedef int (*apei_hest_func_t)(struct acpi_hest_header *hest_hdr, void *data); +static bool hest_match_pci_devfn(struct acpi_hest_aer_common *p, struct pci_dev *dev) +{ + return ACPI_HEST_SEGMENT(p->bus) == pci_domain_nr(dev->bus) && + ACPI_HEST_BUS(p->bus) == dev->bus->number && + p->device == PCI_SLOT(dev->devfn) && + p->function == PCI_FUNC(dev->devfn); +} + +static bool hest_source_is_pcie_aer(struct acpi_hest_header *hest_hdr, struct pci_dev *dev) +{ + u16 hest_type = hest_hdr->type; + u8 pcie_type = pci_pcie_type(dev); + struct acpi_hest_aer_common *common = (struct acpi_hest_aer_common *)(hest_hdr + 1); + + switch (hest_type) { + case ACPI_HEST_TYPE_AER_ROOT_PORT: + if (pcie_type != PCI_EXP_TYPE_ROOT_PORT) + return false; + break; + case ACPI_HEST_TYPE_AER_ENDPOINT: + if (pcie_type != PCI_EXP_TYPE_ENDPOINT) + return false; + break; + case ACPI_HEST_TYPE_AER_BRIDGE: + if (pcie_type != PCI_EXP_TYPE_PCI_BRIDGE && pcie_type != PCI_EXP_TYPE_PCIE_BRIDGE) + return false; + break; + default: + return false; + } + + if (common->flags & ACPI_HEST_GLOBAL) + return true; + + if (hest_match_pci_devfn(common, dev)) + return true; + + return false; +} + +int hest_parse_pcie_aer(struct acpi_hest_header *hest_hdr, void *data) +{ + struct hest_parse_aer_info *info = data; + + info->data = (void *)hest_hdr; + if (!hest_source_is_pcie_aer(hest_hdr, info->pci_dev)) + return 0; + else + return 1; +} int apei_hest_parse(apei_hest_func_t func, void *data) { diff --git a/include/acpi/apei.h b/include/acpi/apei.h index b79976daa4bb..047e0469927c 100644 --- a/include/acpi/apei.h +++ b/include/acpi/apei.h @@ -23,6 +23,11 @@ enum hest_status { HEST_NOT_FOUND, }; +struct hest_parse_aer_info { + struct pci_dev *pci_dev; + void *data; +}; + extern int hest_disable; extern int erst_disable; #ifdef CONFIG_ACPI_APEI_GHES @@ -33,12 +38,18 @@ void __init acpi_ghes_init(void); static inline void acpi_ghes_init(void) { } #endif +typedef int (*apei_hest_func_t)(struct acpi_hest_header *hest_hdr, void *data); int apei_hest_parse(apei_hest_func_t func, void *data); #ifdef CONFIG_ACPI_APEI void __init acpi_hest_init(void); +int hest_parse_pcie_aer(struct acpi_hest_header *hest_hdr, void *data); #else static inline void acpi_hest_init(void) { } +static inline int hest_parse_pcie_aer(struct acpi_hest_header *hest_hdr, void *data) +{ + return 0; +} #endif int erst_write(const struct cper_record_header *record); From patchwork Wed Feb 26 12:18:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13993363 X-Patchwork-Delegate: bhelgaas@google.com Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67F8427005B for ; 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Wed, 26 Feb 2025 20:19:02 +0800 From: LeoLiu-oc To: , , , , , , , , , , , , CC: , , , , LeoLiuoc Subject: [PATCH v5 3/4] PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge Date: Wed, 26 Feb 2025 20:18:37 +0800 X-ASG-Orig-Subj: [PATCH v5 3/4] PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge Message-ID: <20250226121838.364533-4-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226121838.364533-1-LeoLiu-oc@zhaoxin.com> References: <20250226121838.364533-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 2/27/2025 8:37:38 AM X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1740616660 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1179 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.137757 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc Define secondary uncorrectable error mask register, secondary uncorrectable error severity register and secondary error capabilities and control register bits in AER capability for PCIe to PCI/PCI-X Bridge. Please refer to PCIe to PCI/PCI-X Bridge Specification r1.0, sec 5.2.3.2, 5.2.3.3 and 5.2.3.4. Signed-off-by: LeoLiuoc --- include/uapi/linux/pci_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3445c4970e4d..0566c663beb7 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -812,6 +812,10 @@ #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ #define PCI_ERR_PREFIX_LOG 0x38 /* TLP Prefix LOG Register (up to 16 bytes) */ +#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */ + /* Virtual Channel */ #define PCI_VC_PORT_CAP1 0x04 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ From patchwork Wed Feb 26 12:18:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13993384 X-Patchwork-Delegate: bhelgaas@google.com Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [61.152.208.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF28076034 for ; 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Wed, 26 Feb 2025 20:19:04 +0800 From: LeoLiu-oc To: , , , , , , , , , , , , CC: , , , , LeoLiuoc Subject: [PATCH v5 4/4] PCI: ACPI: Add new pci_acpi_program_hest_aer_params() Date: Wed, 26 Feb 2025 20:18:38 +0800 X-ASG-Orig-Subj: [PATCH v5 4/4] PCI: ACPI: Add new pci_acpi_program_hest_aer_params() Message-ID: <20250226121838.364533-5-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250226121838.364533-1-LeoLiu-oc@zhaoxin.com> References: <20250226121838.364533-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 2/27/2025 8:37:39 AM X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1740616660 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 5086 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.137756 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc Call the func pci_acpi_program_hest_aer_params() for every PCIe device, the purpose of this function is to extract register value from HEST PCIe AER structures and program them into AER Capabilities. This function applies to all hardware platforms that has a PCI Express AER structure in HEST. Signed-off-by: LeoLiuoc --- drivers/pci/pci-acpi.c | 90 ++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 6 +++ drivers/pci/probe.c | 1 + 3 files changed, 97 insertions(+) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index af370628e583..2e9a50fc7433 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "pci.h" /* @@ -806,6 +807,95 @@ int pci_acpi_program_hp_params(struct pci_dev *dev) return -ENODEV; } +#ifdef CONFIG_ACPI_APEI +/* + * program_hest_aer_common() - configure AER common registers for Root Ports, + * Endpoints and PCIe to PCI/PCI-X bridges + */ +static void program_hest_aer_common(struct acpi_hest_aer_common aer_common, struct pci_dev *dev, + int pos) +{ + u32 uncor_mask = aer_common.uncorrectable_mask; + u32 uncor_severity = aer_common.uncorrectable_severity; + u32 cor_mask = aer_common.correctable_mask; + u32 adv_cap = aer_common.advanced_capabilities; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncor_mask); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncor_severity); + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, cor_mask); + pci_write_config_dword(dev, pos + PCI_ERR_CAP, adv_cap); +} + +static void program_hest_aer_root(struct acpi_hest_aer_root *aer_root, struct pci_dev *dev, int pos) +{ + u32 root_err_cmd = aer_root->root_error_command; + + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, root_err_cmd); +} + +static void program_hest_aer_bridge(struct acpi_hest_aer_bridge *hest_aer_bridge, + struct pci_dev *dev, int pos) +{ + u32 uncor_mask2 = hest_aer_bridge->uncorrectable_mask2; + u32 uncor_severity2 = hest_aer_bridge->uncorrectable_severity2; + u32 adv_cap2 = hest_aer_bridge->advanced_capabilities2; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK2, uncor_mask2); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER2, uncor_severity2); + pci_write_config_dword(dev, pos + PCI_ERR_CAP2, adv_cap2); +} + +static void program_hest_aer_params(struct hest_parse_aer_info info) +{ + struct pci_dev *dev; + int port_type; + int pos; + struct acpi_hest_aer_root *hest_aer_root; + struct acpi_hest_aer *hest_aer_endpoint; + struct acpi_hest_aer_bridge *hest_aer_bridge; + + dev = info.pci_dev; + port_type = pci_pcie_type(dev); + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + if (!pos) + return; + + switch (port_type) { + case PCI_EXP_TYPE_ROOT_PORT: + hest_aer_root = (struct acpi_hest_aer_root *)info.data; + program_hest_aer_common(hest_aer_root->aer, dev, pos); + program_hest_aer_root(hest_aer_root, dev, pos); + break; + case PCI_EXP_TYPE_ENDPOINT: + hest_aer_endpoint = (struct acpi_hest_aer *)info.data; + program_hest_aer_common(hest_aer_endpoint->aer, dev, pos); + break; + case PCI_EXP_TYPE_PCI_BRIDGE: + hest_aer_bridge = (struct acpi_hest_aer_bridge *)info.data; + program_hest_aer_common(hest_aer_bridge->aer, dev, pos); + program_hest_aer_bridge(hest_aer_bridge, dev, pos); + break; + default: + break; + } +} + +void pci_acpi_program_hest_aer_params(struct pci_dev *dev) +{ + struct hest_parse_aer_info info = { + .pci_dev = dev + }; + + if (!pci_is_pcie(dev)) + return; + + if (apei_hest_parse(hest_parse_pcie_aer, &info) > 0) + program_hest_aer_params(info); + + return; +} +#endif + /** * pciehp_is_native - Check whether a hotplug port is handled by the OS * @bridge: Hotplug port to check diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 01e51db8d285..6ce44a2a3a69 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -902,6 +902,12 @@ static inline void pci_save_aer_state(struct pci_dev *dev) { } static inline void pci_restore_aer_state(struct pci_dev *dev) { } #endif +#ifdef CONFIG_ACPI_APEI +void pci_acpi_program_hest_aer_params(struct pci_dev *dev); +#else +static inline void pci_acpi_program_hest_aer_params(struct pci_dev *dev){ } +#endif + #ifdef CONFIG_ACPI bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); int pci_acpi_program_hp_params(struct pci_dev *dev); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 246744d8d268..40ef918c049c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2352,6 +2352,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_serr(dev); pci_acpi_program_hp_params(dev); + pci_acpi_program_hest_aer_params(dev); } static void pci_release_capabilities(struct pci_dev *dev)