From patchwork Thu Feb 27 16:58:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994928 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 782581D4335 for ; Thu, 27 Feb 2025 17:00:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675655; cv=none; b=iWZnGa+wg3h0LP3FAWwzAjsgBqhDaCXAb+K93wwViAHPpLPPSs873fqjpEBWbumElZQ0/OrTZtnJs0tHjxTKjbLJUzArZQ+4skEaqq9AHYgCx5rR30S1+BToIURhJw+Ypz3eCi3M0QvpB0HJbU+Ceb6j+TtAEbKkGHyoL3NB2X8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675655; c=relaxed/simple; bh=aOLdfrJgG4xijrWsw1Q6AbfF+TEncusrKqqhCnXwUoo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JCqoCbY+4CTjBHSceID+757hd++hh6FjqLvDTCkf3EgacM+IMgOXyqnZDhdIUZ+FdhasgU1rPLPal7xy7icQcleq6Rj+kjHMler47znokH4SEMGh6KrAc3KJkAYy4XnW/n9m3w2KGlMIrnTv65e//NHEhMbHXNW5d5cdFEvDvvc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=KQNxjRXp; arc=none smtp.client-ip=89.58.32.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="KQNxjRXp" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8A02410382F1A; Thu, 27 Feb 2025 18:00:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1740675645; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=q+0tAWt+Qjct3O4SDcG8rZZ2o6M/LcHVGvtP3po6lSY=; b=KQNxjRXpcvJbz9cgkcZQoHo9j6WJlFA4+eHsi+79LIXltTLb8A2GR9urWj7yMW/wa4fC++ O7re390e2VOV3buJ5/H6NnTQ2nJ9lhtq8tQ8dJKEU9I6CIgBgfQpklf8Qh1wkKodqvMZgY 1kXjSslr0OIIA+HI6ZwkwsQA9/bl3iTU5+jCdZ4O3fei8TLnvxUThvGT7PIe3I+tUxP5WX uCsYX7xWdJ0IziUY+ZGVfNDARw9uFflLV38qjFs/KZGwnouYXYptpWA0Yr68dV5dhbd45a 608JCAPJkOQTBgxfxoEMdJe/nPXD4hDYp6Xxg/Og7YOgn2xnNNJQp0hfdSF7Pw== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH 1/9] dt-bindings: reset: imx95-gpu-blk-ctrl: Document Freescale i.MX95 GPU reset Date: Thu, 27 Feb 2025 17:58:01 +0100 Message-ID: <20250227170012.124768-2-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250227170012.124768-1-marex@denx.de> References: <20250227170012.124768-1-marex@denx.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The instance of the GPU populated in Freescale i.MX95 does require release from reset by writing into a single GPUMIX block controller GPURESET register bit 0. Document support for this reset register. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- .../reset/fsl,imx95-gpu-blk-ctrl.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml new file mode 100644 index 0000000000000..dc701bd556c0b --- /dev/null +++ b/Documentation/devicetree/bindings/reset/fsl,imx95-gpu-blk-ctrl.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/fsl,imx95-gpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX95 GPU Block Controller + +maintainers: + - Marek Vasut + +description: | + This reset controller is a block of ad-hoc debug registers, one of + which is a single-bit GPU reset. + +properties: + compatible: + - const: fsl,imx95-gpu-blk-ctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - '#reset-cells' + +additionalProperties: false + +examples: + - | + reset-controller@4d810000 { + compatible = "fsl,imx95-gpu-blk-ctrl"; + reg = <0x0 0x4d810000 0x0 0xc>; + clocks = <&scmi_clk IMX95_CLK_GPUAPB>; + power-domains = <&scmi_devpd IMX95_PD_GPU>; + #reset-cells = <1>; + }; From patchwork Thu Feb 27 16:58:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994930 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34BC4192B71 for ; Thu, 27 Feb 2025 17:00:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675656; cv=none; b=hqMRspl4us/i/P0mGhyTEVEsEmEJurzHB+RxbDSOIhZEn6SgRStVq5MiiTIdypm/Pov+40ud1SVE6+NaB9aQM6xQoOza46XL3g2Pnw3yHgltYF8Fqp0aQvV2xuYCcaReZ0PgWhbRv4U+5/1Qt3d1Vnvq0T1kiCFmDMSxEQnd+JY= ARC-Message-Signature: i=1; a=rsa-sha256; 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Thu, 27 Feb 2025 18:00:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1740675647; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iVuupfJxe+koLI0yNqZJPyXcPdbXN4NhcUu5eQOsaOs=; b=QkDgSvx6fm0XF7Ki7aCEqP2I1+aCtG49/hYEhC1CvHgsX0b6wEjfnSAqLiKujc9WtcCM0c +f8Tx6KiKm0tlUvnY82KovdThYQUmqkmlsjOXaerWv/4ILJvHJ5CtH9N3mW75WSCMDhYpN QwK0mbA2ZaE2t+m6K0pG/nLei3HnLEfObNQloNKOg2ETpOlw0JcR23sAdnwkrWDyubd2Il WWoo58A1l/qUU+m/zAnKP4oTvBHcxbX7kWmJVHJ2mR83nv9nfvk+zmJrP7PhCCTlVKeJV6 K5mZRb83fo5mj1OZ+AKKT0K/0W30vx6wWFuZmHXgxFgJ45wXGM8x1gWcLIaDOw== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH 2/9] reset: simple: Add support for Freescale i.MX95 GPU reset Date: Thu, 27 Feb 2025 17:58:02 +0100 Message-ID: <20250227170012.124768-3-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250227170012.124768-1-marex@denx.de> References: <20250227170012.124768-1-marex@denx.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The instance of the GPU populated in Freescale i.MX95 does require release from reset by writing into a single GPUMIX block controller GPURESET register bit 0. Implement support for this reset register. Signed-off-by: Marek Vasut Reviewed-by: Frank Li --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- drivers/reset/reset-simple.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 2760678398308..1415a941fd6eb 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -133,9 +133,17 @@ static const struct reset_simple_devdata reset_simple_active_low = { .status_active_low = true, }; +static const struct reset_simple_devdata reset_simple_fsl_imx95_gpu_blk_ctrl = { + .reg_offset = 0x8, + .active_low = true, + .status_active_low = true, +}; + static const struct of_device_id reset_simple_dt_ids[] = { { .compatible = "altr,stratix10-rst-mgr", .data = &reset_simple_socfpga }, + { .compatible = "fsl,imx95-gpu-blk-ctrl", + .data = &reset_simple_fsl_imx95_gpu_blk_ctrl }, { .compatible = "st,stm32-rcc", }, { .compatible = "allwinner,sun6i-a31-clock-reset", .data = &reset_simple_active_low }, From patchwork Thu Feb 27 16:58:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994932 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C64C1DCB09 for ; Thu, 27 Feb 2025 17:00:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675658; cv=none; b=flORGizR0EcDDyJ+43cEMhmA2NxgAed4nrV/fyN9j6y0OijOCWQsszopmwpW5IwmJOCYei0UgEjtCi4NkT8/dT16KYCANeYlcPPwVnmcfNzxmOMPVE3ph7uqrQreikSm686Tz4pZq/+qrIgcjTj9+as8Si0s3iZl0yrgXY1kT4k= ARC-Message-Signature: i=1; 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Thu, 27 Feb 2025 18:00:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1740675648; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rBr0cQee0ICtEgGCoLJb0hDKj8AQwhHIxt049wAgmYA=; b=LbbTlbjwQbsg6PEnktAyQeVoYU26GGNb16ZmQXDCe6pl4IpTdNp2N2HM0+vc6riTm6O9Tu grDd/Cn/6jEVDpbgY++QH4Pdg1xtgHz71iD8+HzFoyuzGhRBBrHgZtoYxyP74MotFWV/TI LbhZdNPYPKbqXDVkDc5BzpAv7BANHjTrGwKuxx6YavDfl+69SkZJW6oT/X8i+IZGW7XPEx NHBGiKX6hbcQSttm/DLwNfIT60VtkLBCZH9RPN33HtezfL7nhbuMLH5seRJB/xxstQTUx5 TiLo8INRhoSlLsWqPt3w1MVBBou/rGRr8APk2inl1qqezMiMzZ1HIi0RlhVaZA== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH 3/9] dt-bindings: gpu: mali-valhall-csf: Document optional reset Date: Thu, 27 Feb 2025 17:58:03 +0100 Message-ID: <20250227170012.124768-4-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250227170012.124768-1-marex@denx.de> References: <20250227170012.124768-1-marex@denx.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The instance of the GPU populated in Freescale i.MX95 does require release from reset by writing into a single GPUMIX block controller GPURESET register bit 0. Document support for one optional reset. Signed-off-by: Marek Vasut Reviewed-by: Frank Li Acked-by: Rob Herring (Arm) --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index a5b4e00217587..0efa06822a543 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -61,6 +61,9 @@ properties: minItems: 1 maxItems: 5 + resets: + maxItems: 1 + sram-supply: true "#cooling-cells": From patchwork Thu Feb 27 16:58:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994929 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72D7614E2E2 for ; Thu, 27 Feb 2025 17:00:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675655; cv=none; b=qAHX8B96feFVF1DSkC1IdBL2AgemiaUVvE/ySbl0FPOw5eBuHHoVsaVX3orC7/7w9IPVJEaKNRCSpkARdCjCufMH9WWv1HJXQk9c+1SETc6vroGxA1aKKoMi530Yoqjm/mvRdlf4qrwDI1oFTMuxOQIopT0179wZd2x7gXiOXiM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675655; c=relaxed/simple; bh=ljKfgJCVimgtdvN53O6i8tuaaRPgqVXVzu89sWou08s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JbqGry1km6Heiv4YuR9uvRiiZ4F7Fx0Xu1dI88v8hdaBHk9IOBsB/RjfexvmgGpQR/VKQcLTTDveJMjeV16i/9LkpZRLUOOO+p2fDoiowtafjdijBF+DCVMcEl418cMk0SspDm/03/kegT3VJw2pgjdwZkvFuGT+DH8NuBaDWKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=C9u7OYl/; arc=none smtp.client-ip=89.58.32.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="C9u7OYl/" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3656710382F22; Thu, 27 Feb 2025 18:00:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1740675650; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Cr2T/qLGB0lwW96DWD8/vn79iF6uSlhDoMgeSvZtY94=; b=C9u7OYl/kCgGFNXv4fgqJPN5xUljK3pSWs9pfuRzXI7Z2Ok0IBxAIkJopoHgkFZgm6oqU3 RCT16E2KiWU/pBZFZtinFrdrOjU4CwXCJ79ddZzqAMPLHKQbhE8Rp3StAkdrXd1XhudYkR 8qmj+dtW3bJRAPRzmWkRKEKPfeBzPvH6kvZoJncJslrOSam6RzGrFcCpRo7DqQzUKgZ0ic 18ZNB0MGmhVymPTifxaRH30Sh2K4PEQ1iWAgjRoTwMpo+lbc0iw1xK0q+A61eShDVoy4Hn GLmr37DUmqNoMpgGNpAqK/Crt1lqH8WDAX1KoeoFZqhJHp2F8ys6kyFrv9dOjw== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH 4/9] drm/panthor: Implement optional reset Date: Thu, 27 Feb 2025 17:58:04 +0100 Message-ID: <20250227170012.124768-5-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250227170012.124768-1-marex@denx.de> References: <20250227170012.124768-1-marex@denx.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The instance of the GPU populated in Freescale i.MX95 does require release from reset by writing into a single GPUMIX block controller GPURESET register bit 0. Implement support for one optional reset. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- drivers/gpu/drm/panthor/Kconfig | 1 + drivers/gpu/drm/panthor/panthor_device.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_device.h | 3 +++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/panthor/Kconfig b/drivers/gpu/drm/panthor/Kconfig index 55b40ad07f3b0..ab62bd6a0750f 100644 --- a/drivers/gpu/drm/panthor/Kconfig +++ b/drivers/gpu/drm/panthor/Kconfig @@ -14,6 +14,7 @@ config DRM_PANTHOR select IOMMU_IO_PGTABLE_LPAE select IOMMU_SUPPORT select PM_DEVFREQ + select RESET_SIMPLE if SOC_IMX9 help DRM driver for ARM Mali CSF-based GPUs. diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c index a9da1d1eeb707..51ee9cae94504 100644 --- a/drivers/gpu/drm/panthor/panthor_device.c +++ b/drivers/gpu/drm/panthor/panthor_device.c @@ -64,6 +64,17 @@ static int panthor_clk_init(struct panthor_device *ptdev) return 0; } +static int panthor_reset_init(struct panthor_device *ptdev) +{ + ptdev->resets = devm_reset_control_get_optional_exclusive_deasserted(ptdev->base.dev, NULL); + if (IS_ERR(ptdev->resets)) + return dev_err_probe(ptdev->base.dev, + PTR_ERR(ptdev->resets), + "get reset failed"); + + return 0; +} + void panthor_device_unplug(struct panthor_device *ptdev) { /* This function can be called from two different path: the reset work @@ -217,6 +228,10 @@ int panthor_device_init(struct panthor_device *ptdev) if (ret) return ret; + ret = panthor_reset_init(ptdev); + if (ret) + return ret; + ret = panthor_devfreq_init(ptdev); if (ret) return ret; @@ -470,6 +485,10 @@ int panthor_device_resume(struct device *dev) if (ret) goto err_disable_stacks_clk; + ret = reset_control_deassert(ptdev->resets); + if (ret) + goto err_disable_coregroup_clk; + panthor_devfreq_resume(ptdev); if (panthor_device_is_initialized(ptdev) && @@ -512,6 +531,9 @@ int panthor_device_resume(struct device *dev) err_suspend_devfreq: panthor_devfreq_suspend(ptdev); + reset_control_assert(ptdev->resets); + +err_disable_coregroup_clk: clk_disable_unprepare(ptdev->clks.coregroup); err_disable_stacks_clk: @@ -563,6 +585,7 @@ int panthor_device_suspend(struct device *dev) panthor_devfreq_suspend(ptdev); + reset_control_assert(ptdev->resets); clk_disable_unprepare(ptdev->clks.coregroup); clk_disable_unprepare(ptdev->clks.stacks); clk_disable_unprepare(ptdev->clks.core); diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h index da6574021664b..fea3a05778e2e 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -111,6 +111,9 @@ struct panthor_device { struct clk *coregroup; } clks; + /** @resets: GPU reset. */ + struct reset_control *resets; + /** @coherent: True if the CPU/GPU are memory coherent. */ bool coherent; From patchwork Thu Feb 27 16:58:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994931 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54CEF1DAC9C for ; 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arc=none smtp.client-ip=89.58.32.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="RyGTCHUJ" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6439A10382F24; Thu, 27 Feb 2025 18:00:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1740675652; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jAy9BJopIfDRaRGU70xDkuGWNXBYiG90Up6CXvmcxjc=; b=RyGTCHUJxyfRnUoIyaSrH53V2swypwkm65CKxKetYqOBRW3syANw3cWlunyEebUq5VoHiz 42P9966TRmUgufEazL8bs9P5HRwPXh0eWqiwgMpQqAY0SDRjbdhaQYanatU9EggL1VzIks rn/2Pn3PBguFlZOj6b/nxEisVdEOZ6ifF/WyC2I6pUf2c8zGaOKh/8OpAnY2Z4tYEKQxGD PlB+2RlPxLAmjo7In1Sdqeqw+QSqJcjaIbzk4eCQb7HblxkISnCZw9jtgmrxwtEZ3Qknw2 V9rWieZQwsjLAnnJPEWCXHZZcSLxYj4aXecCWk2WYYZducR6Gnt5EnWmGDfFQg== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH 5/9] drm/panthor: Implement support for multiple power domains Date: Thu, 27 Feb 2025 17:58:05 +0100 Message-ID: <20250227170012.124768-6-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250227170012.124768-1-marex@denx.de> References: <20250227170012.124768-1-marex@denx.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The driver code power domain binding to driver instances only works for single power domain, in case there are multiple power domains, it is necessary to explicitly attach via dev_pm_domain_attach*(). As DT bindings list support for up to 5 power domains, add support for attaching them all. This is useful on Freescale i.MX95 which does have two power domains. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- drivers/gpu/drm/panthor/panthor_device.c | 56 ++++++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_device.h | 5 +++ 2 files changed, 61 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c index 51ee9cae94504..4348b7e917b64 100644 --- a/drivers/gpu/drm/panthor/panthor_device.c +++ b/drivers/gpu/drm/panthor/panthor_device.c @@ -75,6 +75,58 @@ static int panthor_reset_init(struct panthor_device *ptdev) return 0; } +/* Generic power domain handling code, see drivers/gpu/drm/tiny/simpledrm.c */ +static void panthor_detach_genpd(void *res) +{ + struct panthor_device *ptdev = res; + int i; + + if (ptdev->pwr_dom_count <= 1) + return; + + for (i = ptdev->pwr_dom_count - 1; i >= 0; i--) + dev_pm_domain_detach(ptdev->pwr_dom_devs[i], true); +} + +static int panthor_genpd_init(struct panthor_device *ptdev) +{ + struct device *dev = ptdev->base.dev; + int i, ret; + + ptdev->pwr_dom_count = of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + /* + * Single power-domain devices are handled by driver core nothing to do + * here. The same for device nodes without "power-domains" property. + */ + if (ptdev->pwr_dom_count <= 1) + return 0; + + if (ptdev->pwr_dom_count > ARRAY_SIZE(ptdev->pwr_dom_devs)) { + drm_warn(&ptdev->base, "Too many power domains (%d) for this device\n", + ptdev->pwr_dom_count); + return -EINVAL; + } + + for (i = 0; i < ptdev->pwr_dom_count; i++) { + ptdev->pwr_dom_devs[i] = dev_pm_domain_attach_by_id(dev, i); + if (!IS_ERR(ptdev->pwr_dom_devs[i])) + continue; + + ret = PTR_ERR(ptdev->pwr_dom_devs[i]); + if (ret != -EPROBE_DEFER) { + drm_warn(&ptdev->base, "pm_domain_attach_by_id(%u) failed: %d\n", i, ret); + continue; + } + + /* Missing dependency, try again. */ + panthor_detach_genpd(ptdev); + return ret; + } + + return devm_add_action_or_reset(dev, panthor_detach_genpd, ptdev); +} + void panthor_device_unplug(struct panthor_device *ptdev) { /* This function can be called from two different path: the reset work @@ -232,6 +284,10 @@ int panthor_device_init(struct panthor_device *ptdev) if (ret) return ret; + ret = panthor_genpd_init(ptdev); + if (ret) + return ret; + ret = panthor_devfreq_init(ptdev); if (ret) return ret; diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h index fea3a05778e2e..7fb65447253e9 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -114,6 +114,11 @@ struct panthor_device { /** @resets: GPU reset. */ struct reset_control *resets; + /** @pwr_dom_count: Power domain count */ + int pwr_dom_count; + /** @pwr_dom_dev: Power domain devices */ + struct device *pwr_dom_devs[5]; + /** @coherent: True if the CPU/GPU are memory coherent. */ bool coherent; From patchwork Thu Feb 27 16:58:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994933 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E82DA1DD0C7 for ; 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Without this, if only the L2 is powered down on RPM entry, the GPU gets stuck and does not indicate the firmware is booted after RPM resume. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- drivers/gpu/drm/panthor/panthor_gpu.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c index 671049020afaa..0f07ef7d9aea7 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -470,11 +470,12 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev) */ void panthor_gpu_suspend(struct panthor_device *ptdev) { - /* On a fast reset, simply power down the L2. */ - if (!ptdev->reset.fast) - panthor_gpu_soft_reset(ptdev); - else - panthor_gpu_power_off(ptdev, L2, 1, 20000); + /* + * Power off the L2 and soft reset the GPU, that makes + * iMX95 Mali G310 resume without firmware boot timeout. + */ + panthor_gpu_power_off(ptdev, L2, 1, 20000); + panthor_gpu_soft_reset(ptdev); panthor_gpu_irq_suspend(&ptdev->gpu->irq); } From patchwork Thu Feb 27 16:58:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994934 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E17E61DC9AB for ; Thu, 27 Feb 2025 17:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675660; cv=none; b=krbUOOtsIBONWc/EsoQbzbjNW5PzDlpX2OC/1qPJqt9kCt2eZgeK4IBaYaRShC8H/BAZ/LJEeW8Mre1hahzxgUc9mLQP9km+7tEmmUoFuDJz0cWDjaz89UJNWS0Q56DSBZ4/1InAaWGxKDnugo3IyGiIfTa78EGuM3qED0KywN4= ARC-Message-Signature: i=1; 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Thu, 27 Feb 2025 18:00:55 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1740675656; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PKmkyZsvoEXQ3oHPek2RaKdUe/+800h3uZ080lhDXM0=; b=IuhA8IB8s4QYIMIERpFZTKD8rXnESB1uTfOseZ/4mAt2ieHPTA2t82movTel8DiWMXpFTT W9nSQCFv2WncvpaCpbxjuS6eZnt/IbKWn58TGA65MPL12ply6YE1kbheYeRAN3v+XXSFyE Rg4E01AN3qKwj4wjuGcG8HWQlf+r+DMNcjVmryR7ezdEZAs6NmJIVGWpaglh2WA4N8vLLB C1h7QhHNORYFS10iUH0NUJjnDJIFDUEsanHCXd4Ber1CogYwyBnpkInBNnnhd4AtCdYDPk xhD21PwyI+I3jWIZaqkr8NifIY8ziPxCXDGEv/TLYqsziqWP/huHIELpXsJjgQ== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH 7/9] dt-bindings: gpu: mali-valhall-csf: Document i.MX95 support Date: Thu, 27 Feb 2025 17:58:07 +0100 Message-ID: <20250227170012.124768-8-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250227170012.124768-1-marex@denx.de> References: <20250227170012.124768-1-marex@denx.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The instance of the GPU populated in Freescale i.MX95 is the Mali G310, document support for this variant. Signed-off-by: Marek Vasut Reviewed-by: Frank Li Reviewed-by: Alexander Stein --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index 0efa06822a543..3ab62bd424e41 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -18,6 +18,7 @@ properties: oneOf: - items: - enum: + - fsl,imx95-mali # G310 - rockchip,rk3588-mali - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable From patchwork Thu Feb 27 16:58:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994935 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B07ED1DDC16 for ; Thu, 27 Feb 2025 17:01:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675662; cv=none; b=By9jgVCO1XVTt1syqLrrrHNwm4+bJa9sInmZarK6TwKMXON5Ca8clhrWeTApKnq4nOEQ/Pc3JUrlJSsO5MM+JjV6AJloD/U4oz2NT2Jq5wsae77imYL3N6ZXpfFPD6zssG4p9xgHnM5lRGBfBpHXW4xxmDLmpUCgu7AdVCY3s2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675662; c=relaxed/simple; bh=BSgCx7NE6nrinVvv1LAiEbgFR+HeYzjL62HCTacxYjo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WqZfMRYItIT6ZBn/3i6/uH935gQDSnID8A2LX1+VAt3FNJscdHMFe6LbrJen/6R9K1jROlHvLgoRbCo7SPPXqox8KcfkdJbE+LQzWs/BnJvJxzsi1Mh4AOupjCR2G+/gkY0ZGzX09Z1bGZSTRCzw13SMk1Z1Wz9DhWEyvXzFi1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=ODvEJVWI; arc=none smtp.client-ip=89.58.32.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="ODvEJVWI" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 19ACC10375A1E; Thu, 27 Feb 2025 18:00:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1740675658; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dLRiMt6/Dpy2Jty4UVTf/yvA7e/j44jHTgLx5ffQrLk=; b=ODvEJVWIhWmh+IobAVZwz92gr/HgIwjafRAW0V3ehEqsbQUOr8VqAzwPsDu2OOFd38Z/YT /wk0C7uAVnPyhMroKz0MWro3S9ixeeI2xnoEY24vjN5zYyXWxNnOgyIqABdJF2aJzPLsss GG3m1Rd+Zl7k9oUaNlQ3EXbMv0fdx6JaKbDXuC6nXa/Y5IOM2bvBu72UaRv6E/VkLteRIM SK3OCq+ZqoCaZj7dX+2s6osBzXmB8XJaqIu6jY+Haz/muhMDPTFLDvFUreBNOdlhc/Nn2U ICc84CI6rDTYs9nrjDEa6sJfB1LYz527IAMr52Jwa0uLyZjm5lLrG7ZWkbB46Q== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH 8/9] drm/panthor: Add i.MX95 support Date: Thu, 27 Feb 2025 17:58:08 +0100 Message-ID: <20250227170012.124768-9-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250227170012.124768-1-marex@denx.de> References: <20250227170012.124768-1-marex@denx.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The instance of the GPU populated in Freescale i.MX95 is the Mali G310, add support for this variant. Signed-off-by: Marek Vasut Reviewed-by: Frank Li --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- drivers/gpu/drm/panthor/panthor_drv.c | 1 + drivers/gpu/drm/panthor/panthor_gpu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/panthor/panthor_drv.c index 06fe46e320738..2504a456d45c4 100644 --- a/drivers/gpu/drm/panthor/panthor_drv.c +++ b/drivers/gpu/drm/panthor/panthor_drv.c @@ -1591,6 +1591,7 @@ static struct attribute *panthor_attrs[] = { ATTRIBUTE_GROUPS(panthor); static const struct of_device_id dt_match[] = { + { .compatible = "fsl,imx95-mali" }, /* G310 */ { .compatible = "rockchip,rk3588-mali" }, { .compatible = "arm,mali-valhall-csf" }, {} diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c index 0f07ef7d9aea7..2371ab8e50627 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -67,6 +67,7 @@ struct panthor_model { } static const struct panthor_model gpu_models[] = { + GPU_MODEL(g310, 0, 0), /* NXP i.MX95 */ GPU_MODEL(g610, 10, 7), {}, }; From patchwork Thu Feb 27 16:58:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13994936 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0DB91DBB37 for ; Thu, 27 Feb 2025 17:01:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675664; cv=none; b=WzgBrnV3vb9RpOnpTek8HDNUgB7gRXLTvGeNuKI48ehPBR0eyCHITI69at5rGJam1McgKOgaIOKNsAnyRz68biQ6eN7yXfWzZ5ke0fvfiHXlAyTGYPg10grip49QFg2lzAvEYO0VKfm8vOIcTXXLBvio4+jRhMl+a1+wtXki7FA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740675664; c=relaxed/simple; bh=Tpj2kAyKeMlsVqLzWxWNh4wDresVNbiRTFb9TM6WUzk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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bh=80ISeY7DDf1yy5uWTMBnUjkKTvDUwesh5b01Bc/k5X0=; b=QUM6ZqO5tHSNtzDnhtd4p5ZL4LiWkQdSQZexHRrS83MopTiyTlhNNjjMzIy/oLeixVlZdd uUpx49bGRzb0kHs52yiVWMd6PCsO5w3eQhTmv7cyQy4NscTCyKuoVeA1dN4iWxF+NOqpcJ VWl48Xg6FSruutDN5v8q8ulOwqHfPXaHY3ozDlHvVpDGQEUsxAItjObsVqmvKMgDA1nMPh qbXJlxAj9tyEXl4kjcojBauMrvSprBvYnXpuxcUoRqOuwx+zyzKb+bwox5ems5+N2iFb9b v/Weo9c+N5xzhiHYInpXtZNhpF5w4RjtseNW4eOv97nRt57f00Y626VC7h0X1w== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH 9/9] arm64: dts: imx95: Describe Mali G310 GPU Date: Thu, 27 Feb 2025 17:58:09 +0100 Message-ID: <20250227170012.124768-10-marex@denx.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250227170012.124768-1-marex@denx.de> References: <20250227170012.124768-1-marex@denx.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The instance of the GPU populated in i.MX95 is the G310, describe this GPU in the DT. Include description of the GPUMIX block controller, which can be operated as a simple reset. Include dummy GPU voltage regulator and OPP tables. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- arch/arm64/boot/dts/freescale/imx95.dtsi | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 3af13173de4bd..36bad211e5558 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -249,6 +249,37 @@ dummy: clock-dummy { clock-output-names = "dummy"; }; + gpu_fixed_reg: fixed-gpu-reg { + compatible = "regulator-fixed"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + }; + + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-hz-real = /bits/ 64 <500000000>; + opp-microvolt = <920000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-hz-real = /bits/ 64 <800000000>; + opp-microvolt = <920000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-hz-real = /bits/ 64 <1000000000>; + opp-microvolt = <920000>; + }; + }; + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -1846,6 +1877,37 @@ netc_emdio: mdio@0,0 { }; }; + gpu_blk_ctrl: reset-controller@4d810000 { + compatible = "fsl,imx95-gpu-blk-ctrl"; + reg = <0x0 0x4d810000 0x0 0xc>; + #reset-cells = <1>; + clocks = <&scmi_clk IMX95_CLK_GPUAPB>; + assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <133333333>; + power-domains = <&scmi_devpd IMX95_PD_GPU>; + status = "disabled"; + }; + + gpu: gpu@4d900000 { + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf"; + reg = <0 0x4d900000 0 0x480000>; + clocks = <&scmi_clk IMX95_CLK_GPU>; + clock-names = "core"; + interrupts = , + , + ; + interrupt-names = "gpu", "job", "mmu"; + mali-supply = <&gpu_fixed_reg>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; + power-domain-names = "mix", "perf"; + resets = <&gpu_blk_ctrl 0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <1013>; + status = "disabled"; + }; + ddr-pmu@4e090dc0 { compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>;