From patchwork Fri Feb 28 09:47:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Dannapel X-Patchwork-Id: 13996035 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC8CC258CEC; Fri, 28 Feb 2025 09:47:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740736064; cv=none; b=OAWqZvcBpuscdC4gYXP0s5hskYrLy5ZtfymGuEr0KtJDfOC0I5RgjJtgRJnI1UARCfCAyAEI+Dqn+BgpvKHV2NdBvXZt6mUU5POUh02nXLoHrkN/4C4Lq7kRRwtno6Xcn19IAS7Xi7Wy5S3jcPes5eNWVC8WJeRZfhoQLzQ2VnI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740736064; c=relaxed/simple; bh=iGftiqL71bbhW6OyXghoFbHOaXQUNWvZWkWS15q4IQ4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HH2Md1jpi06JZKbuCf4QKTdT/j+flFdzEgpEVbo1LKW21+86M0UqFYKptV6zfVcGpAno++xHGHgyGzlAWm088shkKKDBrhNwWCxw9X3CHqlwmbvZSI97rsp+eMnqpVhN86fyOInC3Wg/FWnG5lisZQlPX5u0BHfvwBWx5rqanEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PKEVsygn; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PKEVsygn" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-ab78e6edb99so257166966b.2; Fri, 28 Feb 2025 01:47:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740736061; x=1741340861; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lSwbc0Ocosx+IYbNPNu2RmJuzW8p4optBGLY8UNnRq0=; b=PKEVsygnf0D6MLx9YNRYOQPovJqdEpTd6pw2965Ui83B6RYBvTJQSAPkyFB6cREULp 0te5hJQKXbw0gBUevPfwvfXMSMsCD0X7W5rR+3FzQy9q7mmZzYChfa/McmDphEUaQ37C UHlpV+zLqjCMMjKYWtVFKNYbVCEt44GZEwCmysAbCWvz7yyaC/BqqqRMYJsEo9rOF1QQ t7MbgEfEuz5na2i+bXWdKEtRvBiAlb4bgBGbHaWQRZieZIKimo6bdWHzpSc+KUNx7gpP WYJF3ei9R+/jdDUHneqAR4SwAazArPc0P1442jdt7uWPgtp7G8jPaWUiGOcfJ+3caL96 +94g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740736061; x=1741340861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lSwbc0Ocosx+IYbNPNu2RmJuzW8p4optBGLY8UNnRq0=; b=cWGR4DZhbNcBQ9dszLf//Le+ZR0gS4A9fgDCJrsE59yVze94GaSaPyXT3XSWhLV214 uvMy39bkyImXsgjNz/zhT/VmQJZK4VuC63U2VUJF+DAwYT1nyiznCe9Dy1kAedQ+2J6j ZVMTweS+xO0t4qp/5EOoekbRqV5KDi1CXPaGcsGReAjsy/M754EOMTkF89f2FfsyWodK hZwMoR9kHLDn7ne0T0amMI8sO+52ypJxrxLIkOThMzuxag7WhGWt+fkAmRAb1paRztL9 NWEMSui3pVLLdOD3WFKL1p51UkdIyadyI82nHFrPP6J363uqvxDZokmQaFO+jOsyAm6t qHuQ== X-Forwarded-Encrypted: i=1; AJvYcCUcGzjFZH2Ag+mGLPCd05d/8d2QWcuBU4JMdF/zEkRn4EX8Qm175qPp41ltMuj4TyPDPTKv9a3OYxPA@vger.kernel.org, AJvYcCXEPi5XbXddQ20+OV7Bo9rzjnGgbOv8QrGkP9WblZLso1Xj2Air9ye7Y/JeRneDCH1FulBckew0fq89wBAp@vger.kernel.org X-Gm-Message-State: AOJu0YwcK4LaZvgj5fugeBPvkKFxxFGAyvKwZhtvaTLwjRAndk2wp6vj RlmYDQ0ijOKi0QD4/c4kLIuwq+HJ+hhNotJatHjc7Z9E8dHBFX3UJVdEeVpC X-Gm-Gg: ASbGncsJilt1vOiZQpfAZGHe0Jty6Uboe7vsqo0LmHXxFnvPg4woX+Nz+raY41TFES2 NziB3q5p+u/l5eCkErRcDPMo4LeHBsUslp4hs4FKC0AflDCQYIUDL9JjIMxceyMX7UISXNIwllY QBTAvvqsxvY/ITD8k2phWHx0BLzhdCbqoKHLYKcKuuy8uvUa0t8HNdpjsaFN45ymsOP9BODsgK6 rW3eYb28qBHBgL0Q7Jj64HHJyi5VP7iHnXk3yyAGQSgVb45F2jjmrgIncIRz2XsCjeBzL+BSMXB 7QrMujx3QxPQQwitrLUz4CSBYwdqGqyuaP0qBJFzLcfdziN6u+SzFRZIZLQR/KYLjxK/f4PSdK1 ov8GguXnF4zisL290lhKkWg== X-Google-Smtp-Source: AGHT+IFpXEmznOoObI43h9IF5p/EadTZulJMuW5Ustxl017DDa7LRvUEIMc66rIZIJBBT8vBVVPiKw== X-Received: by 2002:a17:907:781:b0:abe:f6f5:93fa with SMTP id a640c23a62f3a-abf261d3b82mr299485766b.33.1740736060878; Fri, 28 Feb 2025 01:47:40 -0800 (PST) Received: from iris-Ian.fritz.box (p200300eb5f0300004dcedf2362c26f55.dip0.t-ipconnect.de. [2003:eb:5f03:0:4dce:df23:62c2:6f55]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abf1a60de5esm209289566b.100.2025.02.28.01.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 01:47:40 -0800 (PST) From: iansdannapel@gmail.com To: linux-fpga@vger.kernel.org Cc: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jonathan Cameron , =?utf-8?b?UmFmYcWCIE1pxYJl?= =?utf-8?b?Y2tp?= , Aradhya Bhatia , Ian Dannapel , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [v4 1/3] dt-bindings: vendor-prefix: Add prefix for Efinix, Inc. Date: Fri, 28 Feb 2025 10:47:30 +0100 Message-ID: <20250228094732.54642-2-iansdannapel@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250228094732.54642-1-iansdannapel@gmail.com> References: <20250228094732.54642-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ian Dannapel Add entry for Efinix, Inc. (https://www.efinixinc.com/) Signed-off-by: Ian Dannapel Acked-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5079ca6ce1d1..f0e0da4e1ec0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -438,6 +438,8 @@ patternProperties: description: Emtop Embedded Solutions "^eeti,.*": description: eGalax_eMPIA Technology Inc + "^efinix,.*": + description: Efinix, Inc. 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[2003:eb:5f03:0:4dce:df23:62c2:6f55]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abf1a60de5esm209289566b.100.2025.02.28.01.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 01:47:42 -0800 (PST) From: iansdannapel@gmail.com To: linux-fpga@vger.kernel.org Cc: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jonathan Cameron , =?utf-8?b?UmFmYcWCIE1pxYJl?= =?utf-8?b?Y2tp?= , Aradhya Bhatia , Ian Dannapel , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [v4 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings Date: Fri, 28 Feb 2025 10:47:31 +0100 Message-ID: <20250228094732.54642-3-iansdannapel@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250228094732.54642-1-iansdannapel@gmail.com> References: <20250228094732.54642-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ian Dannapel Add device tree bindings documentation for configuring Efinix FPGA using serial SPI passive programming mode. Signed-off-by: Ian Dannapel --- .../devicetree/bindings/fpga/efinix,spi.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/efinix,spi.yaml diff --git a/Documentation/devicetree/bindings/fpga/efinix,spi.yaml b/Documentation/devicetree/bindings/fpga/efinix,spi.yaml new file mode 100644 index 000000000000..145c96f38e45 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/efinix,spi.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efinix,spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +maintainers: + - Ian Dannapel + +description: | + Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitstreams + through "SPI Passive Mode". + Note 1: Only bus width 1x is supported. + Note 2: Additional pins hogs for bus width configuration must be set + elsewhere, if necessary. + Note 3: Topaz and Titanium support is based on documentation but remains + untested. + + References: + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.3.pdf + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.8.pdf + - https://www.efinixinc.com/docs/an061-configuring-topaz-fpgas-v1.1.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - efinix,trion-spi + - efinix,titanium-spi + - efinix,topaz-spi + - efinix,fpga-spi + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + reset-gpios: + description: + reset and re-configuration trigger pin (low active) + maxItems: 1 + + cdone-gpios: + description: + optional configuration done status pin (high active) + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible = "efinix,trion-spi"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +... 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[2003:eb:5f03:0:4dce:df23:62c2:6f55]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abf1a60de5esm209289566b.100.2025.02.28.01.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 01:47:46 -0800 (PST) From: iansdannapel@gmail.com To: linux-fpga@vger.kernel.org Cc: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jonathan Cameron , =?utf-8?b?UmFmYcWCIE1pxYJl?= =?utf-8?b?Y2tp?= , Aradhya Bhatia , Ian Dannapel , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [v4 3/3] fpga-mgr: Add Efinix SPI programming driver Date: Fri, 28 Feb 2025 10:47:32 +0100 Message-ID: <20250228094732.54642-4-iansdannapel@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250228094732.54642-1-iansdannapel@gmail.com> References: <20250228094732.54642-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ian Dannapel Add a new driver for loading binary firmware to configuration RAM using "SPI passive mode" on Efinix FPGAs. Signed-off-by: Ian Dannapel --- drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/efinix-spi.c | 212 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 220 insertions(+) create mode 100644 drivers/fpga/efinix-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 37b35f58f0df..b5d60ba62900 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -83,6 +83,13 @@ config FPGA_MGR_XILINX_SPI FPGA manager driver support for Xilinx FPGA configuration over slave serial interface. +config FPGA_MGR_EFINIX_SPI + tristate "Efinix FPGA configuration over SPI" + depends on SPI + help + FPGA manager driver support for Efinix FPGAs configuration over SPI + (passive mode only). + config FPGA_MGR_ICE40_SPI tristate "Lattice iCE40 SPI" depends on OF && SPI diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index aeb89bb13517..adbd51d2cd1e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o diff --git a/drivers/fpga/efinix-spi.c b/drivers/fpga/efinix-spi.c new file mode 100644 index 000000000000..07885110a8a8 --- /dev/null +++ b/drivers/fpga/efinix-spi.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * FPGA Manager Driver for Efinix + * + * Copyright (C) 2025 iris-GmbH infrared & intelligent sensors + * + * Ian Dannapel + * + * Load Efinix FPGA firmware over SPI using the serial configuration interface. + * + * Note 1: Only passive mode (host initiates transfer) is currently supported. + * Note 2: Topaz and Titanium support is based on documentation but remains + * untested. + */ + +#include +#include +#include +#include +#include +#include + +struct efinix_spi_conf { + struct spi_device *spi; + struct gpio_desc *cdone; + struct gpio_desc *reset; +}; + +static void efinix_spi_reset(struct efinix_spi_conf *conf) +{ + gpiod_set_value(conf->reset, 1); + /* tCRESET_N > 320 ns */ + usleep_range(1, 2); + gpiod_set_value(conf->reset, 0); + + /* tDMIN > 32 us */ + usleep_range(35, 40); +} + +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + + if (conf->cdone && gpiod_get_value(conf->cdone) == 1) + return FPGA_MGR_STATE_OPERATING; + + return FPGA_MGR_STATE_UNKNOWN; +} + +static int efinix_spi_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); + return -EOPNOTSUPP; + } + return 0; +} + +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct efinix_spi_conf *conf = mgr->priv; + int ret; + struct spi_message message; + struct spi_transfer assert_cs = { + .cs_change = 1 + }; + struct spi_transfer write_xfer = { + .tx_buf = buf, + .len = count + }; + struct spi_transfer clk_cycles = { + .len = 13, // > 100 clock cycles + .tx_buf = NULL + }; + u8 *dummy_buf; + + dummy_buf = kzalloc(13, GFP_KERNEL); + if (!dummy_buf) { + ret = -ENOMEM; + goto fail; + } + + spi_bus_lock(conf->spi->controller); + spi_message_init(&message); + spi_message_add_tail(&assert_cs, &message); + ret = spi_sync_locked(conf->spi, &message); + if (ret) + goto fail_unlock; + + /* reset with asserted cs */ + efinix_spi_reset(conf); + + spi_message_init(&message); + spi_message_add_tail(&write_xfer, &message); + + clk_cycles.tx_buf = dummy_buf; + spi_message_add_tail(&clk_cycles, &message); + + ret = spi_sync_locked(conf->spi, &message); + if (ret) + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", ret); + +fail_unlock: + spi_bus_unlock(conf->spi->controller); + kfree(dummy_buf); +fail: + return ret; +} + +static int efinix_spi_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct efinix_spi_conf *conf = mgr->priv; + unsigned long timeout = + jiffies + usecs_to_jiffies(info->config_complete_timeout_us); + bool expired = false; + int done; + + if (conf->cdone) { + while (!expired) { + expired = time_after(jiffies, timeout); + + done = gpiod_get_value(conf->cdone); + if (done < 0) + return done; + + if (done) + break; + } + } + + if (expired) + return -ETIMEDOUT; + + /* tUSER > 25 us */ + usleep_range(30, 35); + return 0; +} + +static const struct fpga_manager_ops efinix_spi_ops = { + .state = efinix_spi_state, + .write_init = efinix_spi_write_init, + .write = efinix_spi_write, + .write_complete = efinix_spi_write_complete, +}; + +static int efinix_spi_probe(struct spi_device *spi) +{ + struct efinix_spi_conf *conf; + struct fpga_manager *mgr; + + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); + if (!conf) + return -ENOMEM; + + conf->spi = spi; + + conf->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(conf->reset)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->reset), + "Failed to get RESET gpio\n"); + + if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL)) + return dev_err_probe(&spi->dev, -EINVAL, + "Unsupported SPI mode, set CPHA and CPOL\n"); + + conf->cdone = devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN); + if (IS_ERR(conf->cdone)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone), + "Failed to get CDONE gpio\n"); + + mgr = devm_fpga_mgr_register(&spi->dev, + "Efinix FPGA Manager", + &efinix_spi_ops, conf); + + return PTR_ERR_OR_ZERO(mgr); +} + +static const struct of_device_id efinix_spi_of_match[] = { + { .compatible = "efinix,trion-spi", }, + { .compatible = "efinix,titanium-spi", }, + { .compatible = "efinix,topaz-spi", }, + { .compatible = "efinix,fpga-spi", }, + {} +}; +MODULE_DEVICE_TABLE(of, efinix_spi_of_match); + +static const struct spi_device_id efinix_ids[] = { + { "trion-spi", 0 }, + { "titanium-spi", 0 }, + { "topaz-spi", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(spi, efinix_ids); + +static struct spi_driver efinix_spi_driver = { + .driver = { + .name = "efinix-spi", + .of_match_table = efinix_spi_of_match, + }, + .probe = efinix_spi_probe, + .id_table = efinix_ids, +}; + +module_spi_driver(efinix_spi_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ian Dannapel "); +MODULE_DESCRIPTION("Efinix FPGA SPI Programming Driver (Topaz/Titanium untested)");