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Fri, 28 Feb 2025 04:40:49 -0800 (PST) From: Zixian Zeng Date: Fri, 28 Feb 2025 20:40:23 +0800 Subject: [PATCH v2] riscv: sophgo: dts: Add spi controller for SG2042 MIME-Version: 1.0 Message-Id: <20250228-sfg-spi-v2-1-8bbf23b85d0e@gmail.com> X-B4-Tracking: v=1; b=H4sIALauwWcC/2XMywrCMBCF4Vcps3YkGRUaV75H6SJNJ+mAvZBIU Ere3dity/9w+HZIHIUT3JsdImdJsi416NSAm+wSGGWsDaTopohaTD5g2gT54smys8rYAep7i+z lfUhdX3uS9Frj54Cz/q3/RtaocTCtsTyaq9H6EWYrz7NbZ+hLKV//58KnngAAAA== X-Change-ID: 20250228-sfg-spi-e3f2aeca09ab To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen Wang , Inochi Amaoto , Alexandre Ghiti Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, sophgo@lists.linux.dev, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, Zixian Zeng X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740746442; l=2729; i=sycamoremoon376@gmail.com; s=20250113; h=from:subject:message-id; bh=pPMhzcYM3CTCeeRM3hVc0R8I+4MebI7ljV90QEYY07s=; b=MXqgr2mcGpw61fx8C5ZrYZfxi0VQxHbEiCtbasaOy/l+UsC9ySW1oMZiECMbe7Z6EzrpdMDf3 8e33dSukgSJCTHvc6ot+tBqGiX8pxcZzdamJjhsWdceYQTAQyZI5FqC X-Developer-Key: i=sycamoremoon376@gmail.com; a=ed25519; pk=OYfH6Z2Nx3aU1r0UZdvhskmddV6KC6V1nyFjsQQt4J8= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250228_044051_601518_BE3A8D49 X-CRM114-Status: UNSURE ( 9.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add spi controllers for SG2042. SG2042 uses the upstreamed Synopsys DW SPI IP. Signed-off-by: Zixian Zeng --- For this spi controller patch, only bindings are included. This is tested on milkv-pioneer board. Using driver/spi/spidev.c for creating /dev/spidevX.Y and tools/spi/spidev_test for testing functionality. --- Changes in v2: - rebase v1 to sophgo/master(github.com/sophgo/linux.git). - order properties in device node. - remove unevaluated properties `clock-frequency`. - set default status to disable. - Link to v1: https://lore.kernel.org/r/20250228-sfg-spi-v1-1-b989aed94911@gmail.com --- .../riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 8 +++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 28 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) --- base-commit: aa5ee7180ec41bb77c3e327e95d119f2294babea change-id: 20250228-sfg-spi-e3f2aeca09ab Best regards, diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index be596d01ff8d33bcdbe431d9731a55ee190ad5b3..c43a807af2f827b5267afe5e4fdf6e9e857dfa20 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -72,6 +72,14 @@ &uart0 { status = "okay"; }; +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + / { thermal-zones { soc-thermal { diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index e62ac51ac55abd922b5ef796ba8c2196383850c4..500645147b1f8ed0a08ad3cafb38ea79cf57d737 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -545,5 +545,33 @@ sd: mmc@704002b000 { "timer"; status = "disabled"; }; + + spi0: spi@7040004000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x70 0x40004000 0x00 0x1000>; + clocks = <&clkgen GATE_CLK_APB_SPI>, + <&clkgen GATE_CLK_SYSDMA_AXI>; + interrupt-parent = <&intc>; + interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <0x01>; + #size-cells = <0x00>; + num-cs = <0x02>; + resets = <&rstgen RST_SPI0>; + status = "disabled"; + }; + + spi1: spi@7040005000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x70 0x40005000 0x00 0x1000>; + clocks = <&clkgen GATE_CLK_APB_SPI>, + <&clkgen GATE_CLK_SYSDMA_AXI>; + interrupt-parent = <&intc>; + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <0x01>; + #size-cells = <0x00>; + num-cs = <0x02>; + resets = <&rstgen RST_SPI1>; + status = "disabled"; + }; }; };