From patchwork Fri Feb 28 14:06:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13996473 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AF4026E963; Fri, 28 Feb 2025 14:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740752033; cv=none; b=FBSl9RqQPVEhMVLDhRYVDI9LPUXTc6BcXyxwnmz7yJ+bKAxwRdJq72tHVxLtpmfQBfwYSxH0firvruQM7Ub/Gwto6jERZ0oeYXETXA/NY4nEePiVM8xMhLMUGI8VnlZP8Ma7p1yDBp527FGgeWiRycwlm6RLzoVrQoYf2THjBPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740752033; c=relaxed/simple; bh=sQHjhSRRKKvn2KS2pRwShOeKMhbOJsbpGQJ+gRuEUlc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BVMSJwbfdl/tbnLPd2YNnzx9dMQrAG7K0ZYyB//yFypXxjzfgEqWkI7pduMCvosfJOksymJZouKQNj7m/Qo6fstvyN5df8/mvJnl9bvtOFt1DFypCjIilhtc+a9ooJFUpwk5llk3nvPEQjMHA7p1bGND4JQeGfeoeAJ4d/tLMPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=apoaV2cy; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="apoaV2cy" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43994ef3872so14422595e9.2; Fri, 28 Feb 2025 06:13:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740752030; x=1741356830; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kyu0U6EVnwR7jmKKslxFmBDM5pJLOoJgHmbUIvRU74E=; b=apoaV2cyG9Dy3/Rdrg4Btvli9edBg1/uI+IHBO8/wEpV3qdSKRUcdA7u7ZPteUUCUj em4mzw4WDRJErQVXfBTlo1Lca0KxhaA9fmBvEIYJIApN+PoD/5izKgehXuEKad4h/Txx d98mDFxiimwnHWXfdmKwDw5bwAwOX1xbIbfHtvBC/hXq8LaOWa9+V47wLqJehEAjSxFE OYSd6HzOMvzABI4ZccVIXh7ZUL88F0E4JXeNfVlA4oGH30L4US7PYRFv/7eAsK0ZXu+B ZfQNMtTMtZLTSIcvK2zSlqnPMIx+ZxN8NM5R0L4U1rOv11F/+MmMfD2OmxxW7EsItf71 EJKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740752030; x=1741356830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kyu0U6EVnwR7jmKKslxFmBDM5pJLOoJgHmbUIvRU74E=; b=WnLTUikLo9zKLIGUcqVy0wBLvCzPXMnAiyQ2Vpc7s5sOCYdqSt3IbHBnAcMl0kJFzW LdDRGRSgqkjcXorTPthbS3wIa/3WpkaX9S/kmUk53801z99eZD2c++IgLXQImeeWqIQI SwQhJMZ24AEAzCk1MHyC8Sdpdv+qa1yPzPa36eLTjrTu2Uhb0z8PSMqxaxEBkjZdzm7f rIGLhLzo/Jx/s/p9c7899L5VXPJqJxoMxTrW0NLrgbEJViy6u3yoc8N96yRBE3UCG35o ncflBTglFbx8aAFOKOINjlOUd0t49abIqu0CAPbYiQ+6DrT8uF5vRB5kjxFPdFmVnAro sfrw== X-Forwarded-Encrypted: i=1; AJvYcCUCAxMbAEH/UYC1ZGzwfGwcP+oB7AhRUZc1wGGCP808dQW1hwj5BWqof1Bbca4rOsRsA4Zx+aEvd/qRvxOw@vger.kernel.org, AJvYcCWm1pCUVYq0ObevXOg2F4eMD7mFOldsM1VMfwBD1wa1+FtY7NopRSjSxj4U87LDtcTvMY2XlwNY/O4X@vger.kernel.org, AJvYcCWuQJbqWaPpIhbOStutaCDE5L7pRV+lL35yO84af95AJV59gzgZ3g/RUfhYuIz3O8lrkkv4Oa+TGYUL@vger.kernel.org, AJvYcCXbQ9oWyDzQH0HXMIyBhBo8odtD+sA0ZLfZJZalEzNSTbtweomy6qGThVlHCriHNlqvy03VSA7j/o34@vger.kernel.org X-Gm-Message-State: AOJu0Yw9SKbQ3xHd08iqdoy9LQ/5Nb0wx7um0W2lnfORB50RhAQlRa0w 2kqRSv1EhCbvbaeTog49GIgFbD00Dl+qWX2bIyZcTFfwVuVolw0f X-Gm-Gg: ASbGnctpawGiYMGRJRDM3XLBta0Wv1/oY6tqcL9UHKByZls2MBUUHfIg/Kv2q7MlsxW JEbbXwZyvCvSzB7MAu38AMBTb7FkoyAsrp3nCnKpcbwN2cAXTJ2LMVFPke1z9Pe+tZThrsrkpo5 cvNNc4dVw5Tvj4CxfctwPQpiV+zTBo6LQyGErJj/kxQCvY2D9PkfWbQCqsNvB+g26EyOR6a0pO7 74tVJ+HvFwSz+8qBCq52L7q7SW1tTkkDyrZfLqJJj8BDD6TeFdwPCnLhI2fvJ/h5ux58gpoAF3M 7DYp49M/ChJS0nAELj5LpA== X-Google-Smtp-Source: AGHT+IHcJnA9bKXjtVLz+yE76Z0QZ4CmOo099FLbQ8yYxwkbiPgU/Mii9m2oIxTJgCOMWJ/3q/f6Zw== X-Received: by 2002:a05:600c:5014:b0:439:9a40:aa09 with SMTP id 5b1f17b1804b1-43ba730d731mr23068745e9.25.1740752029931; Fri, 28 Feb 2025 06:13:49 -0800 (PST) Received: from spiri.. ([82.77.155.83]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43b736f75c6sm58221645e9.1.2025.02.28.06.13.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 06:13:49 -0800 (PST) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , "Rob Herring (Arm)" , Jonathan Cameron , Ramona Gradinariu , David Lechner , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Subject: [PATCH v6 1/3] dt-bindings: iio: adc: add AD7191 Date: Fri, 28 Feb 2025 16:06:00 +0200 Message-ID: <20250228141327.262488-2-alisa.roman@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250228141327.262488-1-alisa.roman@analog.com> References: <20250228141327.262488-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 AD7191 is a pin-programmable, ultra-low noise 24-bit sigma-delta ADC designed for precision bridge sensor measurements. It features two differential analog input channels, selectable output rates, programmable gain, internal temperature sensor and simultaneous 50Hz/60Hz rejection. Signed-off-by: Alisa-Dariana Roman Reviewed-by: Rob Herring (Arm) --- .../bindings/iio/adc/adi,ad7191.yaml | 149 ++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 156 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml new file mode 100644 index 000000000000..801ed319ee82 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2025 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7191.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD7191 ADC + +maintainers: + - Alisa-Dariana Roman + +description: | + Bindings for the Analog Devices AD7191 ADC device. Datasheet can be + found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD7191.pdf + The device's PDOWN pin must be connected to the SPI controller's chip select + pin. + +properties: + compatible: + enum: + - adi,ad7191 + + reg: + maxItems: 1 + + spi-cpol: true + + spi-cpha: true + + clocks: + maxItems: 1 + description: + Must be present when CLKSEL pin is tied HIGH to select external clock + source (either a crystal between MCLK1 and MCLK2 pins, or a + CMOS-compatible clock driving MCLK2 pin). Must be absent when CLKSEL pin + is tied LOW to use the internal 4.92MHz clock. + + interrupts: + maxItems: 1 + + avdd-supply: + description: AVdd voltage supply + + dvdd-supply: + description: DVdd voltage supply + + vref-supply: + description: Vref voltage supply + + odr-gpios: + description: + ODR1 and ODR2 pins for output data rate selection. Should be defined if + adi,odr-value is absent. + minItems: 2 + maxItems: 2 + + adi,odr-value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Should be present if ODR pins are pin-strapped. Possible values: + 120 Hz (ODR1=0, ODR2=0) + 60 Hz (ODR1=0, ODR2=1) + 50 Hz (ODR1=1, ODR2=0) + 10 Hz (ODR1=1, ODR2=1) + If defined, odr-gpios must be absent. + enum: [120, 60, 50, 10] + + pga-gpios: + description: + PGA1 and PGA2 pins for gain selection. Should be defined if adi,pga-value + is absent. + minItems: 2 + maxItems: 2 + + adi,pga-value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Should be present if PGA pins are pin-strapped. Possible values: + Gain 1 (PGA1=0, PGA2=0) + Gain 8 (PGA1=0, PGA2=1) + Gain 64 (PGA1=1, PGA2=0) + Gain 128 (PGA1=1, PGA2=1) + If defined, pga-gpios must be absent. + enum: [1, 8, 64, 128] + + temp-gpios: + description: TEMP pin for temperature sensor enable. + maxItems: 1 + + chan-gpios: + description: CHAN pin for input channel selection. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - avdd-supply + - dvdd-supply + - vref-supply + - spi-cpol + - spi-cpha + - temp-gpios + - chan-gpios + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - oneOf: + - required: + - adi,odr-value + - required: + - odr-gpios + - oneOf: + - required: + - adi,pga-value + - required: + - pga-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7191"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; + clocks = <&ad7191_mclk>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + avdd-supply = <&avdd>; + dvdd-supply = <&dvdd>; + vref-supply = <&vref>; + adi,pga-value = <1>; + odr-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>, <&gpio 24 GPIO_ACTIVE_HIGH>; + temp-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + chan-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index bd04375ab4a2..ac1f61256932 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1346,6 +1346,13 @@ W: http://ez.analog.com/community/linux-device-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7091r* F: drivers/iio/adc/ad7091r* +ANALOG DEVICES INC AD7191 DRIVER +M: Alisa-Dariana Roman +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml + ANALOG DEVICES INC AD7192 DRIVER M: Alisa-Dariana Roman L: linux-iio@vger.kernel.org From patchwork Fri Feb 28 14:06:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13996474 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 060F526E62D; Fri, 28 Feb 2025 14:13:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740752037; cv=none; b=DlPlOZuasOjLdlZEk/fyFEZBW1zBtMAGxamVUlTS/bwUGVr6R7MpqlgaV8IN4zGus7OK1+hT3UauOPDJ2SZTGrXP11pyBv3LwGy+7yy3et71RdMu604ggAUJR1eGBu+OMTEM8KibPgtW7VSHwP+g5suuQF6HS5qiSPTm+mHM/b4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740752037; c=relaxed/simple; bh=wfMCC90o/tFeMUl8+uEoaMeva01AU1SLt23AOjB1M8c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=L4pkzbg7abE6pZ5PrR5AyQQaKUfOKq5p4BR7exqrvQm2xA8FivuW5+loW7S2yXCeE+26GZKTHhI2kcty+8ynxjz9dtLWinnIXKjIwC27pLZkZM1Kow28JHByeYaqHVxtWz5Oz9GonjN7//4fmScla1lLj0UEcBnPt4NbSZghGok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=GEMtyypa; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GEMtyypa" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-390ddf037ffso1047474f8f.2; Fri, 28 Feb 2025 06:13:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740752033; x=1741356833; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EpZe+iZ/XtbudId+KKCG4M9Nfk7uBA9r7wj2JrAZBjo=; b=GEMtyypamWBWYorPMHUYV/Gt1Y4AeeJ9OSAK+0EhtSp9rf+NtkiYy8HUPEevt3PiCw l3fPYzBwP9G0XgswLqPzwErfc877+/rDS4dAhmBrvvjSVZ9a9UMU4qhMwWNvuNO/Nf1V J0eeTTgZtLUE17SZkvnVq7y0r83il+LO9IgPDJTyKe1sJgfp3SQuA+rWzdQLaomfhXzB 2Cb0D5M9YHtRgx6zUGjJj5GUkSOlqMN+ivYhOd0snXeX0Hl4MxpdFCrZAzQtKCR1sk6C TQuvIsJ3XyvHokoOss8k5d2Mkvpf1obYWfmM8v3o+bQdrv+BJ+xuOqzhd2UK0fI3kBm6 Bv1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740752033; x=1741356833; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EpZe+iZ/XtbudId+KKCG4M9Nfk7uBA9r7wj2JrAZBjo=; b=m9dy5v7NS0qEK1nqTRSg/asHoI1Uvdl0FCG2DhKgRBGchVXi0uxienBcL2MvXQiDvb A2GXSIZC0GuniGFYm260XihTVR6HZ8Cu99GfCImgZl0+g8BpY42RPPuePTNj9PezZyIb Dr6jiBQoL+QO/8pd7/UIKJR0br2RqwPkBJ25kqoeJrCwtqnCje7kD+FVVHKliuLYvZre M66NfkIRNx+BEp9+w2qPzvKvluFCqEOEDQR56T86F+jQfw60pNESekDdEEAwQNgmN3b+ reCssaHTigu5P39kRegjzyW0af6toSgd2AHJDRXToGp7LfneB6VfIYVh+YWzFuqzq0hk oaeA== X-Forwarded-Encrypted: i=1; AJvYcCU1mouI/usbZps/lT2ONXX62ozbrRjPGDcHXvGZJ61VMn4iiMHOWEdTBk7cRqAunpbBXijfYX8Fwo4u@vger.kernel.org, AJvYcCUzdw7Yz5H8IA2fA30F9D5RJ+LgTwPXvrkpxBrkf8uo+DvjRTIr8pJ1DRAnBG0a3heILpJShuckFhdD@vger.kernel.org, AJvYcCVgAxWyAkhtT0eG2Zw2wm+2txkb8wIJwMAM+Tbd5Ov3py0mKVp8sq9roLUSfJptJyGdA24L9sHWcrrW@vger.kernel.org, AJvYcCXy+kcnTuACvYHcZK1xu8sZdNCIcG4stYoBeLPL5RogUu04uUU4XsddhcUPEWhXfZo1zHjPs/cQDcuak0tX@vger.kernel.org X-Gm-Message-State: AOJu0Ywf3r/yJZ+xGyBpU99DCZMmwopqP6/9L18aGvVMNjb+hlyux+6Z xCT2FEbui8hglSHlDC8IU/aCbERNcYkIFeohreLZLZRZKIOzHyud X-Gm-Gg: ASbGncukRDaIM0OF7r7MD6mUln/FrMH14vtR73mE5rzDdNC4mVYYRMpQ7eNfH3Cnl0L XUo2SyltD9bFfz/p/JEvCr51xf2ySGIR4RVhF8Fp3067gz7tZybBSXcZl5EwAL3VMGbiHDwlLd2 MNhH4uuInaKztqqmwLPpxubzElWd1dme1fpCFlYQ6Px1AXlC5zjKsLyZaDYYvZA+4ZeibFPw+02 RsSJ9TYtEdgh8FC8VZDvUiz8gpQu4zlApEWWisRU54NGUBLza3ILpdup+lE5+BaSdmNj5fueGwm V9z+y1Vc4cFfjQ/lALr59A== X-Google-Smtp-Source: AGHT+IG4Stblmr0LflPSE7Y78QV9KHPifMZRrPab3/uHNBPrJyb08hjcLIHZ+VC4djCeBA1vkjHSQg== X-Received: by 2002:a5d:5f84:0:b0:385:ee40:2d88 with SMTP id ffacd0b85a97d-390ec7c6a3bmr3224377f8f.3.1740752032872; Fri, 28 Feb 2025 06:13:52 -0800 (PST) Received: from spiri.. ([82.77.155.83]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43b736f75c6sm58221645e9.1.2025.02.28.06.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 06:13:52 -0800 (PST) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , "Rob Herring (Arm)" , Jonathan Cameron , Ramona Gradinariu , David Lechner , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Subject: [PATCH v6 2/3] iio: adc: ad7191: add AD7191 Date: Fri, 28 Feb 2025 16:06:01 +0200 Message-ID: <20250228141327.262488-3-alisa.roman@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250228141327.262488-1-alisa.roman@analog.com> References: <20250228141327.262488-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 AD7191 is a pin-programmable, ultra-low noise 24-bit sigma-delta ADC designed for precision bridge sensor measurements. It features two differential analog input channels, selectable output rates, programmable gain, internal temperature sensor and simultaneous 50Hz/60Hz rejection. Signed-off-by: Alisa-Dariana Roman --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad7191.c | 554 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 566 insertions(+) create mode 100644 drivers/iio/adc/ad7191.c diff --git a/MAINTAINERS b/MAINTAINERS index ac1f61256932..87c491975ced 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1352,6 +1352,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml +F: drivers/iio/adc/ad7191.c ANALOG DEVICES INC AD7192 DRIVER M: Alisa-Dariana Roman diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 27413516216c..b7ae6e0ae0df 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -142,6 +142,16 @@ config AD7173 To compile this driver as a module, choose M here: the module will be called ad7173. +config AD7191 + tristate "Analog Devices AD7191 ADC driver" + depends on SPI + select AD_SIGMA_DELTA + help + Say yes here to build support for Analog Devices AD7191. + + To compile this driver as a module, choose M here: the + module will be called ad7191. + config AD7192 tristate "Analog Devices AD7192 and similar ADC driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 9f26d5eca822..3e918c3eec69 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_AD7091R5) += ad7091r5.o obj-$(CONFIG_AD7091R8) += ad7091r8.o obj-$(CONFIG_AD7124) += ad7124.o obj-$(CONFIG_AD7173) += ad7173.o +obj-$(CONFIG_AD7191) += ad7191.o obj-$(CONFIG_AD7192) += ad7192.o obj-$(CONFIG_AD7266) += ad7266.o obj-$(CONFIG_AD7280) += ad7280a.o diff --git a/drivers/iio/adc/ad7191.c b/drivers/iio/adc/ad7191.c new file mode 100644 index 000000000000..d9cd903ffdd2 --- /dev/null +++ b/drivers/iio/adc/ad7191.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AD7191 ADC driver + * + * Copyright 2025 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define ad_sigma_delta_to_ad7191(sigmad) \ + container_of((sigmad), struct ad7191_state, sd) + +#define AD7191_TEMP_CODES_PER_DEGREE 2815 + +#define AD7191_CHAN_MASK BIT(0) +#define AD7191_TEMP_MASK BIT(1) + +enum ad7191_channel { + AD7191_CH_AIN1_AIN2, + AD7191_CH_AIN3_AIN4, + AD7191_CH_TEMP, +}; + +/* + * NOTE: + * The AD7191 features a dual-use data out ready DOUT/RDY output. + * In order to avoid contentions on the SPI bus, it's therefore necessary + * to use SPI bus locking. + * + * The DOUT/RDY output must also be wired to an interrupt-capable GPIO. + * + * The SPI controller's chip select must be connected to the PDOWN pin + * of the ADC. When CS (PDOWN) is high, it powers down the device and + * resets the internal circuitry. + */ + +struct ad7191_state { + struct ad_sigma_delta sd; + struct mutex lock; /* Protect device state */ + + struct gpio_descs *odr_gpios; + struct gpio_descs *pga_gpios; + struct gpio_desc *temp_gpio; + struct gpio_desc *chan_gpio; + + u16 int_vref_mv; + const u32 (*scale_avail)[2]; + size_t scale_avail_size; + u32 scale_index; + const u32 *samp_freq_avail; + size_t samp_freq_avail_size; + u32 samp_freq_index; + + struct clk *mclk; +}; + +static int ad7191_set_channel(struct ad_sigma_delta *sd, unsigned int address) +{ + struct ad7191_state *st = ad_sigma_delta_to_ad7191(sd); + u8 temp_gpio_val, chan_gpio_val; + + if (!FIELD_FIT(AD7191_CHAN_MASK | AD7191_TEMP_MASK, address)) + return -EINVAL; + + chan_gpio_val = FIELD_GET(AD7191_CHAN_MASK, address); + temp_gpio_val = FIELD_GET(AD7191_TEMP_MASK, address); + + gpiod_set_value(st->chan_gpio, chan_gpio_val); + gpiod_set_value(st->temp_gpio, temp_gpio_val); + + return 0; +} + +static int ad7191_set_cs(struct ad_sigma_delta *sigma_delta, int assert) +{ + struct spi_transfer t = { + .len = 0, + .cs_change = assert, + }; + struct spi_message m; + + spi_message_init_with_transfers(&m, &t, 1); + + return spi_sync_locked(sigma_delta->spi, &m); +} + +static int ad7191_set_mode(struct ad_sigma_delta *sd, + enum ad_sigma_delta_mode mode) +{ + struct ad7191_state *st = ad_sigma_delta_to_ad7191(sd); + + switch (mode) { + case AD_SD_MODE_CONTINUOUS: + case AD_SD_MODE_SINGLE: + return ad7191_set_cs(&st->sd, 1); + case AD_SD_MODE_IDLE: + return ad7191_set_cs(&st->sd, 0); + default: + return -EINVAL; + } +} + +static const struct ad_sigma_delta_info ad7191_sigma_delta_info = { + .set_channel = ad7191_set_channel, + .set_mode = ad7191_set_mode, + .has_registers = false, +}; + +static int ad7191_init_regulators(struct iio_dev *indio_dev) +{ + struct ad7191_state *st = iio_priv(indio_dev); + struct device *dev = &st->sd.spi->dev; + int ret; + + ret = devm_regulator_get_enable(dev, "avdd"); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable specified AVdd supply\n"); + + ret = devm_regulator_get_enable(dev, "dvdd"); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n"); + + ret = devm_regulator_get_enable_read_voltage(dev, "vref"); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get Vref voltage\n"); + + st->int_vref_mv = ret / 1000; + + return 0; +} + +static int ad7191_config_setup(struct iio_dev *indio_dev) +{ + struct ad7191_state *st = iio_priv(indio_dev); + struct device *dev = &st->sd.spi->dev; + /* Sampling frequencies in Hz, see Table 5 */ + static const u32 samp_freq[4] = { 120, 60, 50, 10 }; + /* Gain options, see Table 7 */ + const u32 gain[4] = { 1, 8, 64, 128 }; + static u32 scale_buffer[4][2]; + int odr_value, odr_index = 0, pga_value, pga_index = 0, i, ret; + u64 scale_uv; + + st->samp_freq_index = 0; + st->scale_index = 0; + + ret = device_property_read_u32(dev, "adi,odr-value", &odr_value); + if (ret && ret != -EINVAL) + return dev_err_probe(dev, ret, "Failed to get odr value.\n"); + + if (ret == -EINVAL) { + st->odr_gpios = devm_gpiod_get_array(dev, "odr", GPIOD_OUT_LOW); + if (IS_ERR(st->odr_gpios)) + return dev_err_probe(dev, PTR_ERR(st->odr_gpios), + "Failed to get odr gpios.\n"); + + if (st->odr_gpios->ndescs != 2) + return dev_err_probe(dev, -EINVAL, "Expected 2 odr gpio pins.\n"); + + st->samp_freq_avail = samp_freq; + st->samp_freq_avail_size = ARRAY_SIZE(samp_freq); + } else { + for (i = 0; i < ARRAY_SIZE(samp_freq); i++) { + if (odr_value != samp_freq[i]) + continue; + odr_index = i; + break; + } + + st->samp_freq_avail = &samp_freq[odr_index]; + st->samp_freq_avail_size = 1; + + st->odr_gpios = NULL; + } + + mutex_lock(&st->lock); + + for (i = 0; i < ARRAY_SIZE(scale_buffer); i++) { + scale_uv = ((u64)st->int_vref_mv * NANO) >> + (indio_dev->channels[0].scan_type.realbits - 1); + do_div(scale_uv, gain[i]); + scale_buffer[i][1] = do_div(scale_uv, NANO); + scale_buffer[i][0] = scale_uv; + } + + mutex_unlock(&st->lock); + + ret = device_property_read_u32(dev, "adi,pga-value", &pga_value); + if (ret && ret != -EINVAL) + return dev_err_probe(dev, ret, "Failed to get pga value.\n"); + + if (ret == -EINVAL) { + st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); + if (IS_ERR(st->pga_gpios)) + return dev_err_probe(dev, PTR_ERR(st->pga_gpios), + "Failed to get pga gpios.\n"); + + if (st->pga_gpios->ndescs != 2) + return dev_err_probe(dev, -EINVAL, "Expected 2 pga gpio pins.\n"); + + st->scale_avail = scale_buffer; + st->scale_avail_size = ARRAY_SIZE(scale_buffer); + } else { + for (i = 0; i < ARRAY_SIZE(gain); i++) { + if (pga_value != gain[i]) + continue; + pga_index = i; + break; + } + + st->scale_avail = &scale_buffer[pga_index]; + st->scale_avail_size = 1; + + st->pga_gpios = NULL; + } + + st->temp_gpio = devm_gpiod_get(dev, "temp", GPIOD_OUT_LOW); + if (IS_ERR(st->temp_gpio)) + return dev_err_probe(dev, PTR_ERR(st->temp_gpio), + "Failed to get temp gpio.\n"); + + st->chan_gpio = devm_gpiod_get(dev, "chan", GPIOD_OUT_LOW); + if (IS_ERR(st->chan_gpio)) + return dev_err_probe(dev, PTR_ERR(st->chan_gpio), + "Failed to get chan gpio.\n"); + + return 0; +} + +static int ad7191_clock_setup(struct ad7191_state *st) +{ + struct device *dev = &st->sd.spi->dev; + + st->mclk = devm_clk_get_optional_enabled(dev, "mclk"); + if (IS_ERR(st->mclk)) + return dev_err_probe(dev, PTR_ERR(st->mclk), + "Failed to get mclk.\n"); + + return 0; +} + +static int ad7191_setup(struct iio_dev *indio_dev) +{ + struct ad7191_state *st = iio_priv(indio_dev); + int ret; + + ret = ad7191_init_regulators(indio_dev); + if (ret) + return ret; + + ret = ad7191_config_setup(indio_dev); + if (ret) + return ret; + + return ad7191_clock_setup(st); +} + +static int ad7191_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long m) +{ + struct ad7191_state *st = iio_priv(indio_dev); + + switch (m) { + case IIO_CHAN_INFO_RAW: + return ad_sigma_delta_single_conversion(indio_dev, chan, val); + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_VOLTAGE: { + guard(mutex)(&st->lock); + *val = st->scale_avail[st->scale_index][0]; + *val2 = st->scale_avail[st->scale_index][1]; + return IIO_VAL_INT_PLUS_NANO; + } + case IIO_TEMP: + *val = 0; + *val2 = NANO / AD7191_TEMP_CODES_PER_DEGREE; + return IIO_VAL_INT_PLUS_NANO; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_OFFSET: + *val = -(1 << (chan->scan_type.realbits - 1)); + switch (chan->type) { + case IIO_VOLTAGE: + return IIO_VAL_INT; + case IIO_TEMP: + *val -= 273 * AD7191_TEMP_CODES_PER_DEGREE; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_SAMP_FREQ: + *val = st->samp_freq_avail[st->samp_freq_index]; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad7191_set_gain(struct ad7191_state *st, int gain_index) +{ + DECLARE_BITMAP(bitmap, 2) = { }; + + st->scale_index = gain_index; + + bitmap_write(bitmap, gain_index, 0, 2); + + return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); +} + +static int ad7191_set_samp_freq(struct ad7191_state *st, int samp_freq_index) +{ + DECLARE_BITMAP(bitmap, 2) = {}; + + st->samp_freq_index = samp_freq_index; + + bitmap_write(bitmap, samp_freq_index, 0, 2); + + return gpiod_multi_set_value_cansleep(st->odr_gpios, bitmap); +} + +static int __ad7191_write_raw(struct ad7191_state *st, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + int i; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: { + if (!st->pga_gpios) + return -EPERM; + guard(mutex)(&st->lock); + for (i = 0; i < st->scale_avail_size; i++) { + if (val2 == st->scale_avail[i][1]) + return ad7191_set_gain(st, i); + } + return -EINVAL; + } + case IIO_CHAN_INFO_SAMP_FREQ: { + if (!st->odr_gpios) + return -EPERM; + guard(mutex)(&st->lock); + for (i = 0; i < st->samp_freq_avail_size; i++) { + if (val == st->samp_freq_avail[i]) + return ad7191_set_samp_freq(st, i); + } + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int ad7191_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, int val2, + long mask) +{ + struct ad7191_state *st = iio_priv(indio_dev); + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret = __ad7191_write_raw(st, chan, val, val2, mask); + + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7191_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + case IIO_CHAN_INFO_SAMP_FREQ: + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad7191_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, const int **vals, + int *type, int *length, long mask) +{ + struct ad7191_state *st = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + *vals = (int *)st->scale_avail; + *type = IIO_VAL_INT_PLUS_NANO; + *length = st->scale_avail_size * 2; + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_SAMP_FREQ: + *vals = (int *)st->samp_freq_avail; + *type = IIO_VAL_INT; + *length = st->samp_freq_avail_size; + return IIO_AVAIL_LIST; + } + + return -EINVAL; +} + +static const struct iio_info ad7191_info = { + .read_raw = ad7191_read_raw, + .write_raw = ad7191_write_raw, + .write_raw_get_fmt = ad7191_write_raw_get_fmt, + .read_avail = ad7191_read_avail, + .validate_trigger = ad_sd_validate_trigger, +}; + +static const struct iio_chan_spec ad7191_channels[] = { + { + .type = IIO_TEMP, + .address = AD7191_CH_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_OFFSET) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), + .scan_type = { + .sign = 'u', + .realbits = 24, + .storagebits = 32, + .endianness = IIO_BE, + }, + }, + { + .type = IIO_VOLTAGE, + .differential = 1, + .indexed = 1, + .channel = 1, + .channel2 = 2, + .address = AD7191_CH_AIN1_AIN2, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_OFFSET) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), + .scan_index = 1, + .scan_type = { + .sign = 'u', + .realbits = 24, + .storagebits = 32, + .endianness = IIO_BE, + }, + }, + { + .type = IIO_VOLTAGE, + .differential = 1, + .indexed = 1, + .channel = 3, + .channel2 = 4, + .address = AD7191_CH_AIN3_AIN4, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_OFFSET) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), + .scan_index = 2, + .scan_type = { + .sign = 'u', + .realbits = 24, + .storagebits = 32, + .endianness = IIO_BE, + }, + }, + IIO_CHAN_SOFT_TIMESTAMP(3), +}; + +static int ad7191_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct ad7191_state *st; + struct iio_dev *indio_dev; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + + ret = devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + indio_dev->name = "ad7191"; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = ad7191_channels; + indio_dev->num_channels = ARRAY_SIZE(ad7191_channels); + indio_dev->info = &ad7191_info; + + ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7191_sigma_delta_info); + if (ret) + return ret; + + ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); + if (ret) + return ret; + + ret = ad7191_setup(indio_dev); + if (ret) + return ret; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id ad7191_of_match[] = { + { .compatible = "adi,ad7191", }, + { } +}; +MODULE_DEVICE_TABLE(of, ad7191_of_match); + +static const struct spi_device_id ad7191_id_table[] = { + { "ad7191" }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad7191_id_table); + +static struct spi_driver ad7191_driver = { + .driver = { + .name = "ad7191", + .of_match_table = ad7191_of_match, + }, + .probe = ad7191_probe, + .id_table = ad7191_id_table, +}; +module_spi_driver(ad7191_driver); + +MODULE_AUTHOR("Alisa-Dariana Roman "); +MODULE_DESCRIPTION("Analog Devices AD7191 ADC"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); From patchwork Fri Feb 28 14:06:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13996475 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B954D26FD9F; Fri, 28 Feb 2025 14:13:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740752039; cv=none; b=d7+wbW/rogmSon4E3dvOciooBovD5htiryVC8nuZf+Qf8oDJOzp/WEDeCnbmOra/xiL0UM+ax7LIFm7bDqAT3BwYztqA5yuzgUAouFxaWvfP59oEGL+EO1q8ZkJ5EaZGxeCFdiWge7ANXXALKYiyqX76OsrbyRdTIrARc0qZsiQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740752039; c=relaxed/simple; bh=+kMhd2o3Td9CwUSXlj1HJCe+jb1gtnNx4+5+2K79dys=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DwTmIXPbCDCC186IkW4HbT971Y+SGrY4DMxhbn9DQEgljRLThBT9Y6bjP5CopjnlEUXApEKob2MZ7NLJezCQ+2M7wSgKrl6ikJSi7kphsUFo7ogcWzBPMyP5H62NXZWUVz8GavKEgLhGzODGbPXtNJkmBi0+e2h6srUtYFl6Tes= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YmNIxWAS; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YmNIxWAS" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4394345e4d5so15418315e9.0; Fri, 28 Feb 2025 06:13:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740752036; x=1741356836; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LQn3Jl5aIqEmUh59R7uxT0+LWMvUZhWqaT8DyQNXmoA=; b=YmNIxWASHlg7ZfToYrmOArVy012zg2RcUzu/dd2TRNj5zJI5A6CmdEnJQTytuSbFq8 LAP5+XVsJLal+CzvgshnSRF096dAUtS2M8qnDlBx5CwnNaGr6sFN9RquWmYp8xmexXQk 3o5myvIMR3XkCloxNaYKA1cywExPqiTxVEzH27sBtR27diCeFL3inFGEwuWnc3L1W+gW cTrBvPMyo2H1QHuweQwYmBNUC1Oyq0tpstxNYgnP6Qdw0NNfbzLakzvN7JOWR3aE0B7x oTvCo6y4coFkKBWdTAUyNSFtCsHApjTq5bze40U+N0MWPWcRv2wIU2mjlD0emmXttpou 4oSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740752036; x=1741356836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LQn3Jl5aIqEmUh59R7uxT0+LWMvUZhWqaT8DyQNXmoA=; b=u1Be59arxSJ+pm/Ej/QalXOvlWbyJZ3VYiwnrB4CEw/Iosbn0dwPL6fbVfHa2qGEB7 2OhvHIvXAnL3q6H/rL6QlbGad2BfECnEfw90ZwCwlW2+dCOnDd4Yfc+vstlgSnjU4S2f oI1OL7LB3mBqUcBdaqYSnupJbxfkuz69Mosg0+XzNS+AYY5SSgQyMoMTp+w1ZI1NmfFQ +Xg5Sb2SX/X3N5oY8YtHjixUXyxs1iannikfcewdbVPaDXtp7n2sTSGjnaAMqbvuC3h0 SUl+FRBp5iUxLXbpyo4VAEmNvIL8fmQW/98qt9m+gLt10xzDJ4XA0rBm+PMyVhXMlP0t piVQ== X-Forwarded-Encrypted: i=1; AJvYcCUFt4dCS/G/V+QM+7lA4a97iHTdhMtR7noFD1txYa2W4pMTyRJM4HDYozc1V+frxngxN+NRZfzGS/lq@vger.kernel.org, AJvYcCWjUdHK1NvElbL2A+MZ6D7zPFkY2rfKSTsk8ISURurDkJNGeVJjQKGBJDyesCYVwyXeffEd8MbdQNDJ@vger.kernel.org, AJvYcCX0Lxfqak/3n9IjDAQHqGI5MnJKxAek7AwPNU56HnTgV9hbrnVf/ypBP9WlwLBoibRsyoSop5T8lJLh@vger.kernel.org, AJvYcCXnUxfi2R76oj4f+zvhTqUqFHQRzlsk/t1S+WocJ4F5kY8vajbSTUdrzaUIrtpmjkxP1rU8aEdXTixVAx7z@vger.kernel.org X-Gm-Message-State: AOJu0YyAyXke4QTdlFDd74scBwn8Q3+U2+2zchyOe/Q0/VtUoo/qahAM BAMtcvdm/uCLkfh39tGtOxXNZhuZo9gs3+bT7i727KIWaex2ild8 X-Gm-Gg: ASbGncu0spVkIeBuyTngCntuzT26F6QPl/z49x17rg6UYgcW21glN8ShBVv5+A/Ba5l lM2uR63qpfNQr6nRrMwhffhecHqoQky5bYkn2BTqmgCaUwDFgPvqqrkkmmrsObZEPbE5HhI5h4p LqWTrF6F8SaVDe3qFJfvAV2YQz+9KGeIxfclqRzXP4n3Y33sSLTPNqvYAZO3nNIW0LI5v9wY3LO 0bxZ8Cqcb7pdpLZTmufHssYcr7Tptoj6d8Cnn/xnhBtFuTf3QuX2tk7lj29RuxY7mo1QFZk6H0b 9f5rMPztRWGU/lmNfkaLkA== X-Google-Smtp-Source: AGHT+IH6auimIyZBLMP16QM5jf72aIFJrYIzux01LERo0tlUCqJVVoHCKyq6NkhMvXsL3mkYczf2yw== X-Received: by 2002:a05:600c:4ecf:b0:439:9a40:aa03 with SMTP id 5b1f17b1804b1-43ba66da2b9mr28808475e9.2.1740752035757; Fri, 28 Feb 2025 06:13:55 -0800 (PST) Received: from spiri.. ([82.77.155.83]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43b736f75c6sm58221645e9.1.2025.02.28.06.13.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 06:13:55 -0800 (PST) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , "Rob Herring (Arm)" , Jonathan Cameron , Ramona Gradinariu , David Lechner , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Subject: [PATCH v6 3/3] docs: iio: add AD7191 Date: Fri, 28 Feb 2025 16:06:02 +0200 Message-ID: <20250228141327.262488-4-alisa.roman@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250228141327.262488-1-alisa.roman@analog.com> References: <20250228141327.262488-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add documentation for AD7191 driver. Signed-off-by: Alisa-Dariana Roman --- Documentation/iio/ad7191.rst | 119 +++++++++++++++++++++++++++++++++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 121 insertions(+) create mode 100644 Documentation/iio/ad7191.rst diff --git a/Documentation/iio/ad7191.rst b/Documentation/iio/ad7191.rst new file mode 100644 index 000000000000..977d4fea14b0 --- /dev/null +++ b/Documentation/iio/ad7191.rst @@ -0,0 +1,119 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +============= +AD7191 driver +============= + +Device driver for Analog Devices AD7191 ADC. + +Supported devices +================= + +* `AD7191 `_ + +The AD7191 is a high precision, low noise, 24-bit Σ-Δ ADC with integrated PGA. +It features two differential input channels, an internal temperature sensor, and +configurable sampling rates. + +Devicetree +========== + +Pin Configuration +----------------- + +The driver supports both pin-strapped and GPIO-controlled configurations for ODR +(Output Data Rate) and PGA (Programmable Gain Amplifier) settings. These +configurations are mutually exclusive - you must use either pin-strapped or GPIO +control for each setting, not both. + +ODR Configuration +^^^^^^^^^^^^^^^^^ + +The ODR can be configured either through GPIO control or pin-strapping: + +- When using GPIO control, specify the "odr-gpios" property in the device tree +- For pin-strapped configuration, specify the "adi,odr-value" property in the + device tree + +Available ODR settings: + + - 120 Hz (ODR1=0, ODR2=0) + - 60 Hz (ODR1=0, ODR2=1) + - 50 Hz (ODR1=1, ODR2=0) + - 10 Hz (ODR1=1, ODR2=1) + +PGA Configuration +^^^^^^^^^^^^^^^^^ + +The PGA can be configured either through GPIO control or pin-strapping: + +- When using GPIO control, specify the "pga-gpios" property in the device tree +- For pin-strapped configuration, specify the "adi,pga-value" property in the + device tree + +Available PGA gain settings: + + - 1x (PGA1=0, PGA2=0) + - 8x (PGA1=0, PGA2=1) + - 64x (PGA1=1, PGA2=0) + - 128x (PGA1=1, PGA2=1) + +Clock Configuration +------------------- + +The AD7191 supports both internal and external clock sources: + +- When CLKSEL pin is tied LOW: Uses internal 4.92MHz clock (no clock property + needed) +- When CLKSEL pin is tied HIGH: Requires external clock source + - Can be a crystal between MCLK1 and MCLK2 pins + - Or a CMOS-compatible clock driving MCLK2 pin + - Must specify the "clocks" property in device tree when using external clock + +SPI Interface Requirements +-------------------------- + +The AD7191 has specific SPI interface requirements: + +- The DOUT/RDY output is dual-purpose and requires SPI bus locking +- DOUT/RDY must be connected to an interrupt-capable GPIO +- The SPI controller's chip select must be connected to the PDOWN pin of the ADC +- When CS (PDOWN) is high, the device powers down and resets internal circuitry +- SPI mode 3 operation (CPOL=1, CPHA=1) is required + +Power Supply Requirements +------------------------- + +The device requires the following power supplies: + +- AVdd: Analog power supply +- DVdd: Digital power supply +- Vref: Reference voltage supply (external) + +All power supplies must be specified in the device tree. + +Channel Configuration +===================== + +The device provides three channels: + +1. Temperature Sensor + - 24-bit unsigned + - Internal temperature measurement + - Temperature in millidegrees Celsius + +2. Differential Input (AIN1-AIN2) + - 24-bit unsigned + - Differential voltage measurement + - Configurable gain via PGA + +3. Differential Input (AIN3-AIN4) + - 24-bit unsigned + - Differential voltage measurement + - Configurable gain via PGA + +Buffer Support +============== + +This driver supports IIO triggered buffers. See Documentation/iio/iio_devbuf.rst +for more information about IIO triggered buffers. diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index 2d334be2b7f2..edc984a38b3b 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -21,6 +21,7 @@ Industrial I/O Kernel Drivers ad4000 ad4030 ad4695 + ad7191 ad7380 ad7606 ad7625 diff --git a/MAINTAINERS b/MAINTAINERS index 87c491975ced..0547a3bb528c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1352,6 +1352,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml +F: Documentation/iio/ad7191.rst F: drivers/iio/adc/ad7191.c ANALOG DEVICES INC AD7192 DRIVER