From patchwork Fri Feb 28 20:04:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13997033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7414C282C6 for ; Fri, 28 Feb 2025 20:05:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1to6bu-0005Ku-Ut; Fri, 28 Feb 2025 15:05:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <36xbCZwgKCmYaLIRHVMOKSSKPI.GSQUIQY-HIZIPRSRKRY.SVK@flex--whendrik.bounces.google.com>) id 1to6ba-0004on-17 for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:06 -0500 Received: from mail-wm1-x349.google.com ([2a00:1450:4864:20::349]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <36xbCZwgKCmYaLIRHVMOKSSKPI.GSQUIQY-HIZIPRSRKRY.SVK@flex--whendrik.bounces.google.com>) id 1to6bX-0000xm-1r for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:05 -0500 Received: by mail-wm1-x349.google.com with SMTP id 5b1f17b1804b1-43ab5baf62cso18737895e9.0 for ; Fri, 28 Feb 2025 12:05:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740773099; x=1741377899; darn=nongnu.org; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=DolmQsqndmFLMXgbOTcrfWM8vLPEPuQ/PPLa+E6wyHc=; b=38XuES/Vm+B7W999d7fnJHBYIJogfFuPE6Q/Wfc2Fs4M8VWilQEbHcI1wxdlPdnqoU lpcddH9I0dsoqCkbg/GtrSPfqG4mgRS03OoJC1yJA1VJAz3PPDzEegx10DqEi4Aa6kPr sx0hLMx2uGpCQEJEvzdmEGHEzmXy5bgJSImA8rAHYzYsQmApUUFZ4yVWGg7YAS8T7H5N GcIeAzN+WXO1LAdzxNWkwYRox1z75iueAZVfIBEDGGzlGD44mn9hkIOmTl6T1jCwzrfY 3yqbRMXN4jneWiq5Jscf5EYKNrd7cu8OmACAglx+8keiV2jah6q/Mi7vz4OgBih5PwY1 PPrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773099; x=1741377899; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=DolmQsqndmFLMXgbOTcrfWM8vLPEPuQ/PPLa+E6wyHc=; b=r34bj4Gk6INk7IrIR7jTuJe7Y/2YGgxIUTGfvnomtKorfZIFShww4hYkwO/j0RLZjd Sf3iaYjsrKYYGoiQjKOh3lfE+8dKp8ajIsvbek+EBMC8ctikhyIQenCo8DyyofbzaRvM SKIEhUXX3ax4Qri8IkPC3b7kXS1S8kKP0mD4rm05Pm6uPO26Scn7Rvu5dTDmaUHsQhxW 3OVw+G9TmkEmeVhQihGhXqfXhK+sh3cOug1S8uy/1dR6kp4tAYWzz/0oTgbFrxsoMriG Ci6LgCq76kcwxwcXIxlhkX0xFUsq9efndG2hfbhG4a9ovz2N7vyOP0kYgaRVNWlwqutB YeOA== X-Gm-Message-State: AOJu0Yw4LDWuJM/ZJFzBKnJTUoQFOdxo8hN7D0A/lmW4DIYHMVXlgHqh wySsKPClGm09db48flUY0GMPP9tWuebtXMGZtQw6edKRvIjgePbSGo3slfHzT+GYtUW+LI2bCrJ wFoCNgp0wI0uJj1ZdBWW/4LL+EWCoGwqb5JOTMF5PzDh0l4XWd2DdQ1C6e1RRTT/O+Veb/H5jvJ 5zb6YwTg8EhcU3+QxvP6J8Qt1adWsvoTBZ4oBYDBMgmQ== X-Google-Smtp-Source: AGHT+IG7w9KVqYnW/iUiH6FcHTHOtUoSFA69ouOf77jdVo8p2tdo6oeabuuM+uwA+AwZflT0lU2vSd3u9LmTbQ== X-Received: from wmbhc26.prod.google.com ([2002:a05:600c:871a:b0:439:916e:3c57]) (user=whendrik job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:3c93:b0:439:8bc3:a697 with SMTP id 5b1f17b1804b1-43ba66cfe5dmr41066515e9.4.1740773099324; Fri, 28 Feb 2025 12:04:59 -0800 (PST) Date: Fri, 28 Feb 2025 20:04:46 +0000 Mime-Version: 1.0 X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250228200453.45173-1-whendrik@google.com> Subject: [PATCH v6 1/8] i386: Add Intel RDT device and State to config. From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, zhao1.liu@intel.com, xiaoyao.li@intel.com, Jonathan.Cameron@huawei.com, v6-0000-cover-letter.patch@google.com Cc: peternewman@google.com, Hendrik Wuethrich Received-SPF: pass client-ip=2a00:1450:4864:20::349; envelope-from=36xbCZwgKCmYaLIRHVMOKSSKPI.GSQUIQY-HIZIPRSRKRY.SVK@flex--whendrik.bounces.google.com; helo=mail-wm1-x349.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Change config to show RDT, add minimal code to the rdt.c module to make sure things still compile. Signed-off-by: Hendrik Wuethrich --- hw/i386/Kconfig | 4 ++ hw/i386/meson.build | 1 + hw/i386/rdt.c | 97 +++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/rdt.h | 35 ++++++++++++++++ target/i386/cpu.h | 4 ++ 5 files changed, 141 insertions(+) create mode 100644 hw/i386/rdt.c create mode 100644 include/hw/i386/rdt.h diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d34ce07b21..a3a6b2259c 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -10,6 +10,9 @@ config SGX bool depends on KVM +config RDT + bool + config PC bool imply APPLESMC @@ -26,6 +29,7 @@ config PC imply QXL imply SEV imply SGX + imply RDT imply TEST_DEVICES imply TPM_CRB imply TPM_TIS_ISA diff --git a/hw/i386/meson.build b/hw/i386/meson.build index 10bdfde27c..3a697dcc03 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -22,6 +22,7 @@ i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport.c')) i386_ss.add(when: 'CONFIG_VTD', if_true: files('intel_iommu.c')) i386_ss.add(when: 'CONFIG_SGX', if_true: files('sgx-epc.c','sgx.c'), if_false: files('sgx-stub.c')) +i386_ss.add(when: 'CONFIG_RDT', if_true: files('rdt.c')) i386_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-common.c')) i386_ss.add(when: 'CONFIG_PC', if_true: files( diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c new file mode 100644 index 0000000000..76a253902b --- /dev/null +++ b/hw/i386/rdt.c @@ -0,0 +1,97 @@ +/* + * Intel Resource Director Technology (RDT). + * + * Copyright 2025 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "hw/i386/rdt.h" +#include "qemu/osdep.h" /* Needs to be included before isa.h */ +#include "hw/isa/isa.h" +#include "hw/qdev-properties.h" +#include "qom/object.h" + +#define TYPE_RDT "rdt" +#define RDT_NUM_RMID_PROP "rmids" + +OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); + +struct RDTMonitor { + uint64_t count_local; + uint64_t count_remote; + uint64_t count_l3; +}; + +struct RDTAllocation { + QemuMutex lock; + uint32_t active_cos; +}; + +struct RDTStatePerCore { + QemuMutex lock; + uint32_t active_rmid; +}; + +struct RDTStatePerL3Cache { + QemuMutex lock; + + RDTMonitor *monitors; + + /* RDT Allocation bitmask MSRs */ + uint32_t msr_L3_ia32_mask_n[RDT_MAX_L3_MASK_COUNT]; + uint32_t msr_L2_ia32_mask_n[RDT_MAX_L2_MASK_COUNT]; + uint32_t ia32_L2_qos_ext_bw_thrtl_n[RDT_MAX_MBA_THRTL_COUNT]; + + /* Parent RDTState */ + RDTState *rdtstate; +}; + +/* One instance of RDT-internal state to be shared by all cores */ +struct RDTState { + ISADevice parent; + + /* Max amount of RMIDs */ + uint32_t rmids; + + uint16_t l3_caches; + + RDTStatePerL3Cache *rdtInstances; + RDTAllocation *allocations; +}; + +struct RDTStateClass { +}; + +OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); + +static Property rdt_properties[] = { + DEFINE_PROP_UINT32(RDT_NUM_RMID_PROP, RDTState, rmids, 256), +}; + +static void rdt_init(Object *obj) +{ +} + +static void rdt_finalize(Object *obj) +{ +} + +static void rdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->hotpluggable = false; + dc->desc = "RDT"; + dc->user_creatable = true; + + device_class_set_props(dc, rdt_properties); +} diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h new file mode 100644 index 0000000000..1f99f98f7f --- /dev/null +++ b/include/hw/i386/rdt.h @@ -0,0 +1,35 @@ +/* + * Intel Resource Director Technology (RDT). + * + * Copyright 2025 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef HW_RDT_H +#define HW_RDT_H + +/* Max counts for allocation masks or CBMs. In other words, the size of + * respective MSRs. + * L3_MASK and L3_mask are architectural limitations. THRTL_COUNT is just + * the space left until the next MSR. + * */ +#define RDT_MAX_L3_MASK_COUNT 127 +#define RDT_MAX_L2_MASK_COUNT 63 +#define RDT_MAX_MBA_THRTL_COUNT 63 + +typedef struct RDTState RDTState; +typedef struct RDTStatePerL3Cache RDTStatePerL3Cache; +typedef struct RDTStatePerCore RDTStatePerCore; +typedef struct RDTMonitor RDTMonitor; +typedef struct RDTAllocation RDTAllocation; + +#endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c67b42d34f..2cbcc8fe4e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2253,6 +2253,10 @@ struct ArchCPU { struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; Notifier machine_done; + /* Help the RDT MSRs find the RDT device state */ + struct RDTStatePerL3Cache *rdtStatePerL3Cache; + struct RDTStatePerCore *rdtPerCore; + struct kvm_msrs *kvm_msr_buf; int32_t node_id; /* NUMA node this CPU belongs to */ From patchwork Fri Feb 28 20:04:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13997032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0613FC282D1 for ; Fri, 28 Feb 2025 20:05:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1to6bf-0004xV-JO; Fri, 28 Feb 2025 15:05:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <37RbCZwgKCmgcNKTJXOQMUUMRK.IUSWKSa-JKbKRTUTMTa.UXM@flex--whendrik.bounces.google.com>) id 1to6ba-0004pv-4N for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:06 -0500 Received: from mail-wm1-x34a.google.com ([2a00:1450:4864:20::34a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <37RbCZwgKCmgcNKTJXOQMUUMRK.IUSWKSa-JKbKRTUTMTa.UXM@flex--whendrik.bounces.google.com>) id 1to6bY-0000yA-51 for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:05 -0500 Received: by mail-wm1-x34a.google.com with SMTP id 5b1f17b1804b1-4393e89e910so14582635e9.0 for ; Fri, 28 Feb 2025 12:05:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740773101; x=1741377901; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=hyuNddXB12O2QD6cZesmxd3qfxmTAioxmOYCYIQvpfA=; b=pc9MA2vkg2yUqo/AwICBPuYwEI6qJCFRoFCjdXlcZlSc+wnlqlP/LCCiScXQ/bLoen bkdL/GKN6xMqiaRlE+5wCqGo3iht4ImEYc8eE02uNsquRZcBHADR7CkFfsG3MiFK2135 PwvOUBE9O6mVcC5NQXsFpltOj5ywnDX49++aYt6Ay8GMwEk8B8oIlqoY2Nel8If3qAOz i3Z5m233TR/A4W30JKCzQfYMUIbuDxUAMmat06mOKrTB2Xty1u3TbuoQcjK0EO06Mgm4 wTr+ayPcxLkz0DM0coltL8FD5/F5C1inH9LfReRG6tzrJFgy9/PVVzoveTJSwlO95DM1 EROQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773101; x=1741377901; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=hyuNddXB12O2QD6cZesmxd3qfxmTAioxmOYCYIQvpfA=; b=D3SFCZj6jYpb5E1Nu3RDm3+3u2GzcePG5v9LjsbpQpfgJnyfkEmrSJARp6B5EUHEMb a/QaELte4xYVZQdSnjgcuzgBBdzYqG4Btp+zI71U1AFSiB3Vg1Totw2RR9mg88NJORB7 esoda/8INcn3FZi/LiW1BZmoG2a1VdxC1IVlgUNaGgToANvmbszcSIa5PN7mXUkaIhJj Gm2Vxm5DZ41WzeIV8kq6k8U56P8tu6misfoiSzd075jDX5V6olOmRdHGzfciAkw6nYJQ 6WeY0PDl4uBvybZ72DTGFWbqFRvdfJ+ONmyPPHrLE2CSl5fL6cAUsAtUx5tQowI3KKsA acjg== X-Gm-Message-State: AOJu0YxHMKjZq39AvGyMsPeNp3+s3P3D0FTXuYjRFOBIPao/hkvLM2Qn 5bV7tl8KLA1WRILr+yRcDzUtHqsIWXEisYM/7pZwrBL4F7XqKJXNGcOUejZNpD/Qq6ReF2/25Qz jhdPpjSlsXbsTl94NlzAlTIr7P5/BtQjrbVTh+97t5pH/Htgn63wQvaJiN4fo5APuOz866s/baJ amwBpYWjgk9lKxO6uPJ/Bzq9zw4eJE+qqWP0C0UZwCvg== X-Google-Smtp-Source: AGHT+IH7eqTRgkrTYJGBVWCG5bG9DuB2zgUa5d87oGQsD5gCmuDsq0cj8zDiAzS38QAOou2q+XChM9iZs5+gsQ== X-Received: from wmbgx23.prod.google.com ([2002:a05:600c:8597:b0:439:8b09:7257]) (user=whendrik job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:46c6:b0:439:9c3a:bba7 with SMTP id 5b1f17b1804b1-43ba67749d3mr34611515e9.28.1740773101304; Fri, 28 Feb 2025 12:05:01 -0800 (PST) Date: Fri, 28 Feb 2025 20:04:47 +0000 In-Reply-To: <20250228200453.45173-1-whendrik@google.com> Mime-Version: 1.0 References: <20250228200453.45173-1-whendrik@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250228200453.45173-2-whendrik@google.com> Subject: [PATCH v6 2/8] i386: Add init and realize functionality for RDT device. From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, zhao1.liu@intel.com, xiaoyao.li@intel.com, Jonathan.Cameron@huawei.com, v6-0000-cover-letter.patch@google.com Cc: peternewman@google.com, Hendrik Wuethrich Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=37RbCZwgKCmgcNKTJXOQMUUMRK.IUSWKSa-JKbKRTUTMTa.UXM@flex--whendrik.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add code to initialize all necessary state for the RDT device. Signed-off-by: Hendrik Wuethrich --- hw/i386/rdt.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index 76a253902b..498c7b70ad 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -18,7 +18,9 @@ #include "qemu/osdep.h" /* Needs to be included before isa.h */ #include "hw/isa/isa.h" #include "hw/qdev-properties.h" +#include "include/hw/boards.h" #include "qom/object.h" +#include "target/i386/cpu.h" #define TYPE_RDT "rdt" #define RDT_NUM_RMID_PROP "rmids" @@ -71,6 +73,16 @@ struct RDTState { struct RDTStateClass { }; +static inline int16_t cache_ids_contain(uint32_t current_ids[], + uint16_t size, uint32_t id) { + for (int i = 0; i < size; i++) { + if (current_ids[i] == id) { + return i; + } + } + return -1; +} + OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); static Property rdt_properties[] = { @@ -81,8 +93,75 @@ static void rdt_init(Object *obj) { } +static void rdt_realize(DeviceState *dev, Error **errp) { + RDTState *rdtDev = RDT(dev); + MachineState *ms = MACHINE(qdev_get_machine()); + rdtDev->rdtInstances = NULL; + rdtDev->l3_caches = 0; + uint32_t *cache_ids_found = g_malloc(sizeof(uint32_t) * 256); + uint32_t cache_ids_size = 0; + + /* Iterate over all CPUs and set RDT state */ + for (int i = 0; i < ms->possible_cpus->len; i++) { + X86CPU *x86_cpu = X86_CPU(ms->possible_cpus->cpus[i].cpu); + X86CPUTopoInfo topo_info = x86_cpu->env.topo_info; + + uint32_t num_threads_sharing = apicid_pkg_offset(&topo_info); + uint32_t index_msb = 32 - clz32(num_threads_sharing); + uint32_t l3_id = x86_cpu->apic_id & ~((1 << index_msb) - 1); + + int16_t pos = cache_ids_contain(cache_ids_found, + cache_ids_size, l3_id); + /* + * If we find a core that shares a new L3 cache, + * initialize the relevant per-L3 state. + * */ + if (pos == -1) { + cache_ids_size++; + pos = cache_ids_size - 1; + cache_ids_found[pos] = l3_id; + + rdtDev->rdtInstances = g_realloc(rdtDev->rdtInstances, + sizeof(RDTStatePerL3Cache) * + cache_ids_size); + rdtDev->l3_caches++; + RDTStatePerL3Cache *rdt = &rdtDev->rdtInstances[pos]; + rdt->rdtstate = rdtDev; + rdt->monitors = g_malloc(sizeof(RDTMonitor) * rdtDev->rmids); + rdt->rdtstate->allocations = g_malloc(sizeof(RDTAllocation) * + rdtDev->rmids); + rdt->monitors->count_local = 0; + rdt->monitors->count_remote = 0; + rdt->monitors->count_l3 = 0; + memset(rdt->msr_L2_ia32_mask_n, 0xF, + sizeof(rdt->msr_L2_ia32_mask_n)); + memset(rdt->msr_L3_ia32_mask_n, 0xF, + sizeof(rdt->msr_L3_ia32_mask_n)); + memset(rdt->ia32_L2_qos_ext_bw_thrtl_n, 0xF, + sizeof(rdt->ia32_L2_qos_ext_bw_thrtl_n)); + qemu_mutex_init(&rdt->rdtstate->allocations->lock); + qemu_mutex_init(&rdt->lock); + } + + x86_cpu->rdtStatePerL3Cache = &rdtDev->rdtInstances[pos]; + x86_cpu->rdtPerCore = g_malloc(sizeof(RDTStatePerCore)); + + qemu_mutex_init(&x86_cpu->rdtPerCore->lock); + } +} + static void rdt_finalize(Object *obj) { + RDTState *rdt = RDT(obj); + MachineState *ms = MACHINE(qdev_get_machine()); + + for (int i = 0; i < ms->possible_cpus->len; i++) { + RDTStatePerL3Cache *rdtInstance = &rdt->rdtInstances[i]; + g_free(rdtInstance->monitors); + g_free(rdtInstance->rdtstate->allocations); + } + + g_free(rdt->rdtInstances); } static void rdt_class_init(ObjectClass *klass, void *data) @@ -92,6 +171,7 @@ static void rdt_class_init(ObjectClass *klass, void *data) dc->hotpluggable = false; dc->desc = "RDT"; dc->user_creatable = true; + dc->realize = rdt_realize; device_class_set_props(dc, rdt_properties); } From patchwork Fri Feb 28 20:04:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13997038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7371C282D0 for ; Fri, 28 Feb 2025 20:07:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1to6bx-0005Lp-Qu; Fri, 28 Feb 2025 15:05:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <37xbCZwgKCmoePMVLZQSOWWOTM.KWUYMUc-LMdMTVWVOVc.WZO@flex--whendrik.bounces.google.com>) id 1to6bc-0004wG-TB for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:10 -0500 Received: from mail-wm1-x34a.google.com ([2a00:1450:4864:20::34a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <37xbCZwgKCmoePMVLZQSOWWOTM.KWUYMUc-LMdMTVWVOVc.WZO@flex--whendrik.bounces.google.com>) id 1to6ba-00016H-Bk for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:08 -0500 Received: by mail-wm1-x34a.google.com with SMTP id 5b1f17b1804b1-4399a5afc72so12993005e9.3 for ; Fri, 28 Feb 2025 12:05:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740773103; x=1741377903; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=BwTgJJO2SlsGl4rYeVMdy42gc14Aj/IPZZveRoI2VoA=; b=Mzfcu1aSfIlaNkrYe/oxWRJxFxl8UASYJQKSjCeUBcN4oTRUDrIhn3u16u6YsTx/us M4NoSKhukFTs5fEAESlu4evIDQp5bN8XRMLhLkMde+pyoaYqqh1XjhgifTCcgZ74zSrY 7lFsiGmNKAu0TakvopYvBzF0K2nflq3UpP6mTIKt1t6ZdkxiE1Y/IWdUf2+YGvwlJ2wD 9GSoNzBbBYeUwsxuzFUZpts3qDzPxPL5ZTXtbN2YeRi/kdQEiGDsbNulCE5qZcY12tRp b7VgD3zb+COgVYVQXrfVQ5QfsUIeMvdOzYCCiQpO5OXoGIt9aovQZGSseUjLm7w+jHAY ileQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773103; x=1741377903; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=BwTgJJO2SlsGl4rYeVMdy42gc14Aj/IPZZveRoI2VoA=; b=Xtt2dWyfhydja16XjexPHyedhNtJVwc5QNEYVa90UtpIj1UWirLlyp3Bs6QWoQtiVx 2DkgwXtYWvzmjYDSuZ67IZ/KepTMuoVs1dnFopFlK7wd0NCdAaAb628Pur1PT+6TkRQC 3RQBh4RYWzo7qd/4eOubemQ7m5KwT/d4Y0SCVXBsaWbTln/S6Atimra4jgrvERPk3UvT srWAdCVbPFT/VqJgexnHrrCpDN1EHa5JG6/HeQjVjbPoua704oycVzmirxJXyrYBmPkA Od/dBvbCQEsoBYoWTwQoAXxMBYBWgGMi6nRo9i7WWDhsS3m+e16Aj9JMmGNvj5OTrJd6 c3YA== X-Gm-Message-State: AOJu0YwSVb9lSdBqEy0n8UrDh0pbZQVrcqVJrKTUETMISGAbAzTDpI6r 8aBB2uUmlJjCP8A01A3sbQ6UME3muXoLhH1vHehbUjkmLNPhXlIYNfq59Zdbs7g4vF2VRvh6XhG tLmxzjzc9kh6nC8+AAYIiAbBboMdGRrG00x+5Q0uRa6b2QQfHZH5dfzsSub0OAOp/qN3IU3v6IQ Xo3UeoIkCoIg/v/c96SXexGEtlsZLZXaVfIOL2f/W+lA== X-Google-Smtp-Source: AGHT+IEtdtVOtWqGgDtExekSulp7Zlq4K94heqhVYF+st1QF5a4L2jdS6zQypslzGA1NEYQSWcLQuj635k4zng== X-Received: from wmdd18.prod.google.com ([2002:a05:600c:a212:b0:439:96eb:cfa0]) (user=whendrik job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:5106:b0:439:9496:181c with SMTP id 5b1f17b1804b1-43ba67745d4mr43309435e9.29.1740773103477; Fri, 28 Feb 2025 12:05:03 -0800 (PST) Date: Fri, 28 Feb 2025 20:04:48 +0000 In-Reply-To: <20250228200453.45173-1-whendrik@google.com> Mime-Version: 1.0 References: <20250228200453.45173-1-whendrik@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250228200453.45173-3-whendrik@google.com> Subject: [PATCH v6 3/8] i386: Add RDT functionality From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, zhao1.liu@intel.com, xiaoyao.li@intel.com, Jonathan.Cameron@huawei.com, v6-0000-cover-letter.patch@google.com Cc: peternewman@google.com, Hendrik Wuethrich Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=37xbCZwgKCmoePMVLZQSOWWOTM.KWUYMUc-LMdMTVWVOVc.WZO@flex--whendrik.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add RDT code to Associate CLOSID with RMID / set RMID for monitoring, write COS, and read monitoring data. This patch does not add code for the guest to interact through these things with MSRs, only the actual ability for the RDT device to do them. Signed-off-by: Hendrik Wuethrich --- hw/i386/rdt.c | 145 ++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/rdt.h | 16 +++++ 2 files changed, 161 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index 498c7b70ad..32ef1ee124 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -22,9 +22,17 @@ #include "qom/object.h" #include "target/i386/cpu.h" +/* RDT Monitoring Event Codes */ +#define RDT_EVENT_L3_OCCUPANCY 1 +#define RDT_EVENT_L3_REMOTE_BW 2 +#define RDT_EVENT_L3_LOCAL_BW 3 + #define TYPE_RDT "rdt" #define RDT_NUM_RMID_PROP "rmids" +#define QM_CTR_ERROR (1ULL << 63) +#define QM_CTR_UNAVAILABLE (1ULL << 62) + OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); struct RDTMonitor { @@ -73,6 +81,143 @@ struct RDTState { struct RDTStateClass { }; +bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerL3Cache *rdtStatePerL3Cache = cpu->rdtStatePerL3Cache; + RDTStatePerCore *rdtPerCore = cpu->rdtPerCore; + RDTAllocation *alloc; + + uint32_t cos_id = (msr_ia32_pqr_assoc & 0xffff0000) >> 16; + uint32_t rmid = msr_ia32_pqr_assoc & 0xffff; + + if (cos_id > RDT_MAX_L3_MASK_COUNT || cos_id > RDT_MAX_L2_MASK_COUNT || + cos_id > RDT_MAX_MBA_THRTL_COUNT || rmid > rdt_max_rmid(rdtStatePerL3Cache)) { + return false; + } + + qemu_mutex_lock(&rdtPerCore->lock); + qemu_mutex_lock(&rdtStatePerL3Cache->lock); + + rdtPerCore->active_rmid = rmid; + + alloc = &rdtStatePerL3Cache->rdtstate->allocations[rmid]; + + alloc->active_cos = cos_id; + + qemu_mutex_unlock(&rdtStatePerL3Cache->lock); + qemu_mutex_unlock(&rdtPerCore->lock); + + return true; +} + +uint32_t rdt_read_l3_mask(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerL3Cache *rdt = cpu->rdtStatePerL3Cache; + + qemu_mutex_lock(&rdt->lock); + return rdt->msr_L3_ia32_mask_n[pos]; + qemu_mutex_unlock(&rdt->lock); +} + +uint32_t rdt_read_l2_mask(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerL3Cache *rdt = cpu->rdtStatePerL3Cache; + + qemu_mutex_lock(&rdt->lock); + return rdt->msr_L2_ia32_mask_n[pos]; + qemu_mutex_unlock(&rdt->lock); +} + +uint32_t rdt_read_mba_thrtl(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerL3Cache *rdt = cpu->rdtStatePerL3Cache; + + qemu_mutex_lock(&rdt->lock); + return rdt->ia32_L2_qos_ext_bw_thrtl_n[pos]; + qemu_mutex_unlock(&rdt->lock); +} + +void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerL3Cache *rdt = cpu->rdtStatePerL3Cache; + + qemu_mutex_lock(&rdt->lock); + rdt->msr_L3_ia32_mask_n[pos] = val; + qemu_mutex_unlock(&rdt->lock); +} + +void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerL3Cache *rdt = cpu->rdtStatePerL3Cache; + + qemu_mutex_lock(&rdt->lock); + rdt->msr_L2_ia32_mask_n[pos] = val; + qemu_mutex_unlock(&rdt->lock); +} + +void rdt_write_mba_thrtl(uint32_t pos, uint32_t val) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerL3Cache *rdt = cpu->rdtStatePerL3Cache; + + qemu_mutex_lock(&rdt->lock); + rdt->ia32_L2_qos_ext_bw_thrtl_n[pos] = val; + qemu_mutex_unlock(&rdt->lock); +} + +uint32_t rdt_max_rmid(RDTStatePerL3Cache *rdt) +{ + RDTState *rdtdev = rdt->rdtstate; + return rdtdev->rmids - 1; +} + +uint64_t rdt_read_event_count(RDTStatePerL3Cache *rdtInstance, + uint32_t rmid, uint32_t event_id) +{ + RDTMonitor *mon; + RDTState *rdt = rdtInstance->rdtstate; + + uint32_t count_l3 = 0; + uint32_t count_local = 0; + uint32_t count_remote = 0; + + if (!rdt) { + return 0; + } + + qemu_mutex_lock(&rdtInstance->lock); + + for (int i = 0; i < rdt->l3_caches; i++) { + rdtInstance = &rdt->rdtInstances[i]; + if (rmid >= rdtInstance->rdtstate->rmids) { + return QM_CTR_ERROR; + } + mon = &rdtInstance->monitors[rmid]; + count_l3 += mon->count_l3; + count_local += mon->count_local; + count_remote += mon->count_remote; + } + + qemu_mutex_unlock(&rdtInstance->lock); + + switch (event_id) { + case RDT_EVENT_L3_OCCUPANCY: + return count_l3 == 0 ? QM_CTR_UNAVAILABLE : count_l3; + case RDT_EVENT_L3_REMOTE_BW: + return count_remote == 0 ? QM_CTR_UNAVAILABLE : count_remote; + case RDT_EVENT_L3_LOCAL_BW: + return count_local == 0 ? QM_CTR_UNAVAILABLE : count_local; + default: + return QM_CTR_ERROR; + } +} + static inline int16_t cache_ids_contain(uint32_t current_ids[], uint16_t size, uint32_t id) { for (int i = 0; i < size; i++) { diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index 1f99f98f7f..d087627499 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -17,6 +17,9 @@ #ifndef HW_RDT_H #define HW_RDT_H +#include +#include + /* Max counts for allocation masks or CBMs. In other words, the size of * respective MSRs. * L3_MASK and L3_mask are architectural limitations. THRTL_COUNT is just @@ -32,4 +35,17 @@ typedef struct RDTStatePerCore RDTStatePerCore; typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; +bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); + +void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val); +void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val); +void rdt_write_mba_thrtl(uint32_t pos, uint32_t val); + +uint32_t rdt_read_l3_mask(uint32_t pos); +uint32_t rdt_read_l2_mask(uint32_t pos); +uint32_t rdt_read_mba_thrtl(uint32_t pos); + +uint64_t rdt_read_event_count(RDTStatePerL3Cache *rdt, uint32_t rmid, uint32_t event_id); +uint32_t rdt_max_rmid(RDTStatePerL3Cache *rdt); + #endif From patchwork Fri Feb 28 20:04:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13997036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CB93C282C6 for ; Fri, 28 Feb 2025 20:06:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1to6c3-0005WZ-C4; Fri, 28 Feb 2025 15:05:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <38RbCZwgKCmwgROXNbSUQYYQVO.MYWaOWe-NOfOVXYXQXe.YbQ@flex--whendrik.bounces.google.com>) id 1to6bk-00059m-R8 for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:19 -0500 Received: from mail-wm1-x34a.google.com ([2a00:1450:4864:20::34a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <38RbCZwgKCmwgROXNbSUQYYQVO.MYWaOWe-NOfOVXYXQXe.YbQ@flex--whendrik.bounces.google.com>) id 1to6bd-00019a-7N for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:15 -0500 Received: by mail-wm1-x34a.google.com with SMTP id 5b1f17b1804b1-439a5c4dfb2so12425955e9.1 for ; Fri, 28 Feb 2025 12:05:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740773105; x=1741377905; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=f+N70W1h/Xmy4CplrtdSn+OiQuPC9AQ4ibAdCjh6RWE=; b=oaa8E2C3OytYVvsHm+SBwwTIoqBjnsETdhVk8j5/qVhv2At9NfgT6nI03r43Lx+PWZ yeoCYfR+U4a65NQOL4elpB6Dyt//Y0auXdbF40iu3gl3QMp/kenX+cPmLjqlcvcOVF+L gKQ3O05iKIUKSg3qEQyEL8+ELuTsIvQydnz6IPROm6Tla6kUug4Zfe8TE6SkXWkkujp9 aYxc1M+fT3c6DmIt5LkRSWvgcthd8KnyUeMjKxlFDSIwmqT22xaJ5exHxCTPjmdPWNKP hIrX3kJapg34OxIZ1KEokZuz55jdGvymMjSMD99V62T8gZEW0agcwwsEb7bYJBAZ52HL PFjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773105; x=1741377905; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=f+N70W1h/Xmy4CplrtdSn+OiQuPC9AQ4ibAdCjh6RWE=; b=PXov8hDPLyjWLqrPe8PP3Om8ShOYtAxN8nX9gIYaXgt+3dM5mXt4k1fF4a8otqah+M FJfRyqnNh1EeX5humHhB8ty/tMWwqulgETUpdchAJiEGrlIxUHXvaHdXrSy3yz/qD5AY cqDboMqjKoxzo0Qx3YSsaPfZ7Egf0NOInsGp3qVHtIXVIlLMvKs0kQNBd/DOsHwd23yh ug60rgbVduX0nLjesrtU/rkFGNPejkIP1Ozt5CjScozu8isE2wyzwmr1Q4xezshOLviz VcLmUa1HFW8m8HrPm/dZIYrC4FLrR7uC4a1mazmQzYeSo5vbCNmg634r9pOKiMQ8kPsR BWjQ== X-Gm-Message-State: AOJu0Yza1TW6C/7u5dzcnavM+cl++I53gl1LDfV5vIvxj2pvdJVxQ5sJ FwlWwcteAmFLs/yErojNMwCKdU5M1I189FrSCLajEetCIyFxaFoXgqkrY24DydDqFOdlsAcxIjP 6gqhSwCaOg8V7MFuaBBr0EzbRiXekimKYcGmLimUTGjsSuyaq/zEaTjDiXp1R28CJDC8AZrHrRf FNSArRjqr/+uWrh9+CGgQmSt6mcX86mH3WkcqrH+AiXA== X-Google-Smtp-Source: AGHT+IEURBPBL9vfA5d4yzQspkEy1o3DNgfzPWOPavDLy+TO2pL5ibEL3KoF00/JlrhhwpKv+5lhTYI5jlJ/Dw== X-Received: from wmbfk6.prod.google.com ([2002:a05:600c:cc6:b0:439:94f1:365e]) (user=whendrik job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:511e:b0:439:6017:6689 with SMTP id 5b1f17b1804b1-43ba66e0bf5mr40423805e9.9.1740773105262; Fri, 28 Feb 2025 12:05:05 -0800 (PST) Date: Fri, 28 Feb 2025 20:04:49 +0000 In-Reply-To: <20250228200453.45173-1-whendrik@google.com> Mime-Version: 1.0 References: <20250228200453.45173-1-whendrik@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250228200453.45173-4-whendrik@google.com> Subject: [PATCH v6 4/8] i386: Add RDT device interface through MSRs From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, zhao1.liu@intel.com, xiaoyao.li@intel.com, Jonathan.Cameron@huawei.com, v6-0000-cover-letter.patch@google.com Cc: peternewman@google.com, Hendrik Wuethrich Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=38RbCZwgKCmwgROXNbSUQYYQVO.MYWaOWe-NOfOVXYXQXe.YbQ@flex--whendrik.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Implement rdmsr and wrmsr for the following MSRs: * MSR_IA32_PQR_ASSOC * MSR_IA32_QM_EVTSEL * MSR_IA32_QM_CTR * IA32_L3_QOS_Mask_n * IA32_L2_QOS_Mask_n * IA32_L2_QoS_Ext_BW_Thrtl_n This allows for the guest to call RDT-internal functions to associate an RMID with a CLOSID / set an active RMID for monitoring, read monitoring data, and set classes of service. Signed-off-by: Hendrik Wuethrich --- include/hw/i386/rdt.h | 4 ++ target/i386/cpu.h | 14 +++++ target/i386/tcg/system/misc_helper.c | 85 ++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+) diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index d087627499..b63b433eef 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -29,6 +29,10 @@ #define RDT_MAX_L2_MASK_COUNT 63 #define RDT_MAX_MBA_THRTL_COUNT 63 +#define CPUID_10_1_EDX_COS_MAX RDT_MAX_L3_MASK_COUNT +#define CPUID_10_2_EDX_COS_MAX RDT_MAX_L2_MASK_COUNT +#define CPUID_10_3_EDX_COS_MAX RDT_MAX_MBA_THRTL_COUNT + typedef struct RDTState RDTState; typedef struct RDTStatePerL3Cache RDTStatePerL3Cache; typedef struct RDTStatePerCore RDTStatePerCore; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2cbcc8fe4e..08089ce6c2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -577,6 +577,17 @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 +#define MSR_IA32_QM_EVTSEL 0x0c8d +#define MSR_IA32_QM_CTR 0x0c8e +#define MSR_IA32_PQR_ASSOC 0x0c8f + +#define MSR_IA32_L3_CBM_BASE 0x0c90 +#define MSR_IA32_L3_MASKS_END 0x0d0f +#define MSR_IA32_L2_CBM_BASE 0x0d10 +#define MSR_IA32_L2_CBM_END 0x0d4f +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE 0xd50 +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_END 0xd8f + #define MSR_APIC_START 0x00000800 #define MSR_APIC_END 0x000008ff @@ -1883,6 +1894,9 @@ typedef struct CPUArchState { uint64_t msr_ia32_feature_control; uint64_t msr_ia32_sgxlepubkeyhash[4]; + uint64_t msr_ia32_qm_evtsel; + uint64_t msr_ia32_pqr_assoc; + uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/misc_helper.c index c9c4d42f84..7027f7228c 100644 --- a/target/i386/tcg/system/misc_helper.c +++ b/target/i386/tcg/system/misc_helper.c @@ -25,6 +25,7 @@ #include "exec/address-spaces.h" #include "exec/exec-all.h" #include "tcg/helper-tcg.h" +#include "hw/i386/rdt.h" #include "hw/i386/apic.h" void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) @@ -293,6 +294,47 @@ void helper_wrmsr(CPUX86State *env) env->msr_bndcfgs = val; cpu_sync_bndcs_hflags(env); break; +#ifdef CONFIG_RDT + case MSR_IA32_QM_EVTSEL: + env->msr_ia32_qm_evtsel = val; + break; + case MSR_IA32_PQR_ASSOC: + env->msr_ia32_pqr_assoc = val; + + if (!rdt_associate_rmid_cos(val)) + goto error; + break; + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE; + + if (pos > CPUID_10_1_EDX_COS_MAX) { + goto error; + } + rdt_write_msr_l3_mask(pos, val); + break; + } + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE; + + if (pos > CPUID_10_2_EDX_COS_MAX) { + goto error; + } + rdt_write_msr_l2_mask(pos, val); + break; + } + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrtl_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE; + + if (pos > CPUID_10_3_EDX_COS_MAX) { + goto error; + } + rdt_write_mba_thrtl(pos, val); + break; + } +#endif case MSR_APIC_START ... MSR_APIC_END: { int ret; int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; @@ -471,6 +513,49 @@ void helper_rdmsr(CPUX86State *env) val = cpu_x86_get_msr_core_thread_count(x86_cpu); break; } +#ifdef CONFIG_RDT + case MSR_IA32_QM_CTR: + val = rdt_read_event_count(x86_cpu->rdtPerNode, + (env->msr_ia32_qm_evtsel >> 32) & 0xff, + env->msr_ia32_qm_evtsel & 0xff); + break; + case MSR_IA32_QM_EVTSEL: + val = env->msr_ia32_qm_evtsel; + break; + case MSR_IA32_PQR_ASSOC: + val = env->msr_ia32_pqr_assoc; + break; + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE; + + if (pos >= CPUID_10_1_EDX_COS_MAX) { + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); + } + val = rdt_read_l3_mask(pos); + break; + } + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE; + + if (pos >= CPUID_10_2_EDX_COS_MAX) { + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); + } + val = rdt_read_l2_mask(pos); + break; + } + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrtl_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE; + + if (pos >= CPUID_10_3_EDX_COS_MAX) { + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); + } + val = rdt_read_mba_thrtl(pos); + break; + } +#endif case MSR_APIC_START ... MSR_APIC_END: { int ret; int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; From patchwork Fri Feb 28 20:04:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13997039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF215C282D2 for ; Fri, 28 Feb 2025 20:07:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1to6c2-0005Td-Dq; Fri, 28 Feb 2025 15:05:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <38xbCZwgKCm4iTQZPdUWSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--whendrik.bounces.google.com>) id 1to6bf-0004xh-HF for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:15 -0500 Received: from mail-wr1-x449.google.com ([2a00:1450:4864:20::449]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <38xbCZwgKCm4iTQZPdUWSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--whendrik.bounces.google.com>) id 1to6bd-00019r-5M for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:10 -0500 Received: by mail-wr1-x449.google.com with SMTP id ffacd0b85a97d-38f39352f1dso1126431f8f.0 for ; Fri, 28 Feb 2025 12:05:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740773107; x=1741377907; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=f5nUlFdo6zTGVeedUX76LpqnWI9Z721CKkwnHkSKwH0=; b=1SW4aDSFz6KYmi29H7tzRqJpJvvCkM6X2zBNw6PufowcQ1BW/2yLzDGOwD5ZqKeAtD dxxqN3tjprcrPfEj6uAHnbpzlhY6idpo0+tQJwUDpBy+/qkH7/ADjXlzwtlvCp6pyMnr OsWHlOnEVHkvIjq/DIvEmF3aZ0nYMaThxpiICW7DR18H845+3EAv61JPnT68y8kQLVGL Pr96cHenIcewnLNmePFPJkxAJlJwdD9AVNHPY9kdndMEeic2wtBPGfZSIBXW5sNC0aYo SeZnyCxx5iKPcJWx8O7C/G0U1fnG9Ta+duH9SCU6gvZaJ3TAnxWxVxj4v7Yvxe86cZXR nZdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773107; x=1741377907; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=f5nUlFdo6zTGVeedUX76LpqnWI9Z721CKkwnHkSKwH0=; b=vf7GZ9TtPO2i57wml5hAlDDEQraHDXz7XWZj2+Q9YfTT0KWnSxh4v2fMxQZ2UibcU6 2eLaKjWEPH49BtJUH+G0eRbGQ7dfbZLw/u8hFUf7m0+CBHtNzOf3qy7O3+VP0GffR4dJ zobPV8aqmyQ31FDqhjzSAKDQWyrpOOzQ/vZaeOCS2ec0QaefJWCfVwHS2QMmVyga4ZQB hzdL4uIfFQe1Ty1wKsKP3H1CHHr8QDhimwmSnvvieBJolAwyZA15tOjVxHLFOUMxNM86 ao7IuvG+fsRNw6sDX4WKU7W+lclwsGGDzXUmfn9TTbwgXRxFUI4HUosD2eGifzhVOlaO XDvA== X-Gm-Message-State: AOJu0YysyJUqnTfQvLp8yKj/x5Pw6AVkaajduC5nbGjYa5N6Zg00gYAz 5O6TZQ7SADBD+RUAJlFP+AhfyL2eTOtHmKRjXmDLBv5sGkqNnvYR2QfwQKqlrd64e7qd6BbD3p1 qUJ7nmd1+0eXqRaEpo5g0/An8Ka7tae6tc+gRN7kEkz/oP7qBcnePHF1kCmAC2vCwG+2czPngcZ WTRPjVP9KQz0ejP1nDrp0SjCal8zjCrzzAHDaWdOVLkA== X-Google-Smtp-Source: AGHT+IFoScdELt4ZkGKuM3Hubf3ZyhyYmMXataSvwKxnYp/L4zc4epF8Q0VereIOZs7Rm6sQwDf8vHAKG17lFQ== X-Received: from wrbgx23.prod.google.com ([2002:a05:6000:4717:b0:38f:59c8:7f19]) (user=whendrik job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6000:1866:b0:390:e9ea:588 with SMTP id ffacd0b85a97d-390eca3bd17mr4657127f8f.55.1740773107123; Fri, 28 Feb 2025 12:05:07 -0800 (PST) Date: Fri, 28 Feb 2025 20:04:50 +0000 In-Reply-To: <20250228200453.45173-1-whendrik@google.com> Mime-Version: 1.0 References: <20250228200453.45173-1-whendrik@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250228200453.45173-5-whendrik@google.com> Subject: [PATCH v6 5/8] i386: Add CPUID enumeration for RDT From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, zhao1.liu@intel.com, xiaoyao.li@intel.com, Jonathan.Cameron@huawei.com, v6-0000-cover-letter.patch@google.com Cc: peternewman@google.com, Hendrik Wuethrich Received-SPF: pass client-ip=2a00:1450:4864:20::449; envelope-from=38xbCZwgKCm4iTQZPdUWSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--whendrik.bounces.google.com; helo=mail-wr1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add CPUID enumeration for intel RDT monitoring and allocation, as well as the flags used in the enumeration code. Signed-off-by: Hendrik Wuethrich --- include/hw/i386/rdt.h | 23 +++++++++++++ target/i386/cpu.c | 75 +++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 5 +++ 3 files changed, 103 insertions(+) diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index b63b433eef..a21bf804a6 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -29,8 +29,31 @@ #define RDT_MAX_L2_MASK_COUNT 63 #define RDT_MAX_MBA_THRTL_COUNT 63 +/* RDT L3 Cache Monitoring Technology */ +#define CPUID_F_0_EDX_L3 (1U << 1) +#define CPUID_F_1_EDX_L3_OCCUPANCY (1U << 0) +#define CPUID_F_1_EDX_L3_TOTAL_BW (1U << 1) +#define CPUID_F_1_EDX_L3_LOCAL_BW (1U << 2) + +/* RDT Cache Allocation Technology */ +#define CPUID_10_0_EBX_L3_CAT (1U << 1) +#define CPUID_10_0_EBX_L2_CAT (1U << 2) +#define CPUID_10_0_EBX_MBA (1U << 3) + +/* RDT L3 Allocation features */ +#define CPUID_10_1_EAX_CBM_LENGTH 0xf +#define CPUID_10_1_EBX_CBM 0x0 +#define CPUID_10_1_ECX_CDP 0x0 /* to enable, it would be (1U << 2) */ #define CPUID_10_1_EDX_COS_MAX RDT_MAX_L3_MASK_COUNT + +/* RDT L2 Allocation features*/ +#define CPUID_10_2_EAX_CBM_LENGTH 0xf +#define CPUID_10_2_EBX_CBM 0x0 #define CPUID_10_2_EDX_COS_MAX RDT_MAX_L2_MASK_COUNT + +/* RDT MBA features */ +#define CPUID_10_3_EAX_THRTL_MAX 89 +#define CPUID_10_3_ECX_LINEAR_RESPONSE (1U << 2) #define CPUID_10_3_EDX_COS_MAX RDT_MAX_MBA_THRTL_COUNT typedef struct RDTState RDTState; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 72ab147e85..cd06744451 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -42,6 +42,7 @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "hw/i386/rdt.h" #include "disas/capstone.h" #include "cpu-internal.h" @@ -6869,6 +6870,80 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, assert(!(*eax & ~0x1f)); *ebx &= 0xffff; /* The count doesn't need to be reliable. */ break; +#ifndef CONFIG_USER_ONLY + case 0xF: + /* Shared Resource Monitoring Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; +#ifdef CONFIG_RDT + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM)) + break; + if (!(cpu->rdtStatePerL3Cache)) { + warn_report("Intel RDT features enabled in commandline, " + "but rdt device not used"); + break; + } + /* Non-zero count is ResId */ + switch (count) { + /* Monitoring Resource Type Enumeration */ + case 0: + *edx = env->features[FEAT_RDT_F_0_EDX]; + *ebx = rdt_max_rmid(cpu->rdtStatePerL3Cache); + break; + case 1: + *ebx = 1; + *ecx = rdt_max_rmid(cpu->rdtStatePerL3Cache); + *edx = CPUID_F_1_EDX_L3_OCCUPANCY | + CPUID_F_1_EDX_L3_TOTAL_BW | + CPUID_F_1_EDX_L3_LOCAL_BW; + break; + } +#endif + break; + case 0x10: + /* Shared Resource Director Technology Allocation Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; +#ifdef CONFIG_RDT + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE)) + break; + if (!(cpu->rdtPerCore)) { + warn_report("Intel RDT features enabled in commandline, " + "but rdt device not used"); + break; + } + /* Non-zero count is ResId */ + switch (count) { + /* Cache Allocation Technology Available Resource Types */ + case 0: + *ebx = CPUID_10_0_EBX_L3_CAT | + CPUID_10_0_EBX_L2_CAT | + CPUID_10_0_EBX_MBA; + break; + case 1: + *eax = CPUID_10_1_EAX_CBM_LENGTH; + *ebx = CPUID_10_1_EBX_CBM; + *ecx = CPUID_10_1_ECX_CDP; + *edx = CPUID_10_1_EDX_COS_MAX; + break; + case 2: + *eax = CPUID_10_2_EAX_CBM_LENGTH; + *ebx = CPUID_10_2_EBX_CBM; + *edx = CPUID_10_2_EDX_COS_MAX; + break; + case 3: + *eax = CPUID_10_3_EAX_THRTL_MAX; + *ecx = CPUID_10_3_ECX_LINEAR_RESPONSE; + *edx = CPUID_10_3_EDX_COS_MAX; + break; + } +#endif + break; +#endif case 0x1C: if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 08089ce6c2..6f5a3ecbd4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -679,6 +679,7 @@ typedef enum FeatureWord { FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */ + FEAT_RDT_F_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ FEATURE_WORDS, } FeatureWord; @@ -853,8 +854,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_0_EBX_RTM (1U << 11) /* Zero out FPU CS and FPU DS */ #define CPUID_7_0_EBX_ZERO_FCS_FDS (1U << 13) +/* Resource Director Technology Monitoring */ +#define CPUID_7_0_EBX_PQM (1U << 12) /* Memory Protection Extension */ #define CPUID_7_0_EBX_MPX (1U << 14) +/* Resource Director Technology Allocation */ +#define CPUID_7_0_EBX_PQE (1U << 15) /* AVX-512 Foundation */ #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Doubleword & Quadword Instruction */ From patchwork Fri Feb 28 20:04:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13997037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80F64C282C6 for ; Fri, 28 Feb 2025 20:07:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1to6bz-0005NK-DF; Fri, 28 Feb 2025 15:05:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <39BbCZwgKCm8jURaQeVXTbbTYR.PbZdRZh-QRiRYabaTah.beT@flex--whendrik.bounces.google.com>) id 1to6bi-000580-Tg for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:19 -0500 Received: from mail-wm1-x349.google.com ([2a00:1450:4864:20::349]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <39BbCZwgKCm8jURaQeVXTbbTYR.PbZdRZh-QRiRYabaTah.beT@flex--whendrik.bounces.google.com>) id 1to6bh-0001AC-7d for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:14 -0500 Received: by mail-wm1-x349.google.com with SMTP id 5b1f17b1804b1-43ab5baf62cso18738865e9.0 for ; Fri, 28 Feb 2025 12:05:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740773109; x=1741377909; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=kmLVEYOHqmSuKqtrlHj7xi68jyrF2grY357sctURLPY=; b=n79mVFztausugPlMC8wNXlE61uyMOuNv3nAb96W0doBJj+OTBIJmSStnpzjiTEqIjW pTmHiP4V7G7864vEcHhDn1JOW0yTKosMbIZPqqNdU8+mG7XAkNwFSSe1w2h+HaO/jIku 6gqUYMQJg/oPSwNZq0mRJZt+yTlhxmpm3Q7vRo1eUn1ieR+flTy7NtOHb1VXyTvOmT9d QeExA0FUd6R9I7hbbXxKg6H2DpMuoA0ttlQJ0bocHqs6qDGbjf+tJ2EBY18W/g3XZB3O 6RDnMskDzzR4Gy+niWN+uAcv0ZWRHIFsMTEnAvs9UoDU4B2TlGSJO3IaBPiowa55WOdc E6gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773109; x=1741377909; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=kmLVEYOHqmSuKqtrlHj7xi68jyrF2grY357sctURLPY=; b=RgdDhsvUpZEDk/ADkgnQojEmelj5dnE0jST+2/GC4I3WerdEyXhO60RDrbTk6YHPbq yvcpTDHFHNsmiQ9kZTx1xVQNs5mha+Q4N7eINgWMgHwtTonOmdWX9vpdAE88El2lgCMi RsFlmI+TtUGCkNVRXVKP8WrmkzPOKKKl5NcistpesxBsZF0LW0VTQTKLijnxnULmAq3t V7Q5ZQc9OtBpsSJYIbAmTEoX1pfVZ+/ztDVawAwsz0LZRQMiXLecuDM/vXECEAHnO2uD LSFO05UUm319GSNSClTfKvsLp/pRwjbK2AeswMTILGI4cWz6icVtwWNu9FRDeIM7Y9ir ovRg== X-Gm-Message-State: AOJu0YzEtwXAYIb7RzRucwMlSLjTip5Rx9G6fChoClrJeZG3DpSndJrb nsqoU3sGo3aJ4FDs7Y2IoevMVQnE/EVydEzEO9Pb123xyejemgyUI+TgQ+XM+91V0KTaTFE7x7K a5zrHd5Lj3ogAX1Jq2fLILgmVej0rlDAlpFcQdpR5olMAF3du/mqTk8ZtMM5JVD+aDgKqkxD9gR CObDbG0SUUNCOw1GaHFC2xAjX8Cb8VUeiprUpXv3O68w== X-Google-Smtp-Source: AGHT+IEXDnmtHdvCU6FYxqx7SwZPQUpPbr18UkYC5JLrNcO3k2UfFjffj812/9T2Ik/o7OjQ3e5tDnnKh17anA== X-Received: from wmbfm10.prod.google.com ([2002:a05:600c:c0a:b0:439:81e4:9ca6]) (user=whendrik job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:1392:b0:439:6ab6:5d45 with SMTP id 5b1f17b1804b1-43ba6747775mr34648115e9.28.1740773108969; Fri, 28 Feb 2025 12:05:08 -0800 (PST) Date: Fri, 28 Feb 2025 20:04:51 +0000 In-Reply-To: <20250228200453.45173-1-whendrik@google.com> Mime-Version: 1.0 References: <20250228200453.45173-1-whendrik@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250228200453.45173-6-whendrik@google.com> Subject: [PATCH v6 6/8] i386: Add RDT feature flags. From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, zhao1.liu@intel.com, xiaoyao.li@intel.com, Jonathan.Cameron@huawei.com, v6-0000-cover-letter.patch@google.com Cc: peternewman@google.com, Hendrik Wuethrich Received-SPF: pass client-ip=2a00:1450:4864:20::349; envelope-from=39BbCZwgKCm8jURaQeVXTbbTYR.PbZdRZh-QRiRYabaTah.beT@flex--whendrik.bounces.google.com; helo=mail-wm1-x349.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add RDT features to feature word / TCG. Signed-off-by: Hendrik Wuethrich --- target/i386/cpu.c | 33 +++++++++++++++++++++++++++++++-- target/i386/cpu.h | 2 ++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cd06744451..6262665294 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -868,7 +868,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, CPUID_7_0_EBX_CLFLUSHOPT | \ CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ - CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES | \ + CPUID_7_0_EBX_PQM | CPUID_7_0_EBX_PQE) /* missing: CPUID_7_0_EBX_HLE CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ @@ -905,6 +906,9 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, #define TCG_SGX_12_0_EBX_FEATURES 0 #define TCG_SGX_12_1_EAX_FEATURES 0 #define TCG_24_0_EBX_FEATURES 0 +#define TCG_RDT_F_0_EDX_FEATURES CPUID_F_0_EDX_L3 +#define TCG_RDT_10_0_EDX_FEATURES (CPUID_10_0_EBX_L3_CAT | \ + CPUID_10_0_EBX_L2_CAT | CPUID_10_0_EBX_MBA) #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1062,7 +1066,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "fsgsbase", "tsc-adjust", "sgx", "bmi1", "hle", "avx2", "fdp-excptn-only", "smep", "bmi2", "erms", "invpcid", "rtm", - NULL, "zero-fcs-fds", "mpx", NULL, + "rdt-m", "zero-fcs-fds", "mpx", "rdt-a", "avx512f", "avx512dq", "rdseed", "adx", "smap", "avx512ifma", "pcommit", "clflushopt", "clwb", "intel-pt", "avx512pf", "avx512er", @@ -1650,6 +1654,31 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .tcg_features = TCG_SGX_12_1_EAX_FEATURES, }, + + [FEAT_RDT_10_0_EBX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + NULL, "l3-cat", "l2-cat", "mba" + }, + .cpuid = { + .eax = 0x10, + .needs_ecx = true, .ecx = 0, + .reg = R_EBX, + }, + .tcg_features = TCG_RDT_10_0_EDX_FEATURES, + }, + [FEAT_RDT_F_0_EDX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [1] = "l3-cmt" + }, + .cpuid = { + .eax = 0xf, + .needs_ecx = true, .ecx = 0, + .reg = R_EDX, + }, + .tcg_features = TCG_RDT_F_0_EDX_FEATURES, + }, }; typedef struct FeatureMask { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6f5a3ecbd4..488126378d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -679,7 +679,9 @@ typedef enum FeatureWord { FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */ + FEAT_RDT_F_0_EBX, /* CPUID[EAX=0xf,ECX=0].EBX (RDT CMT/MBM) */ FEAT_RDT_F_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ + FEAT_RDT_10_0_EBX, /* CPUID[EAX=0x10,ECX=0].EBX (RDT CAT/MBA) */ FEATURE_WORDS, } FeatureWord; From patchwork Fri Feb 28 20:04:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13997034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 007B0C282D0 for ; Fri, 28 Feb 2025 20:05:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1to6bv-0005L2-2x; Fri, 28 Feb 2025 15:05:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <39xbCZwgKCnImXUdThYaWeeWbU.SecgUck-TUlUbdedWdk.ehW@flex--whendrik.bounces.google.com>) id 1to6bl-00059o-2R for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:19 -0500 Received: from mail-wr1-x44a.google.com ([2a00:1450:4864:20::44a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <39xbCZwgKCnImXUdThYaWeeWbU.SecgUck-TUlUbdedWdk.ehW@flex--whendrik.bounces.google.com>) id 1to6bh-0001Ae-JU for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:15 -0500 Received: by mail-wr1-x44a.google.com with SMTP id ffacd0b85a97d-390f6aa50c5so200077f8f.2 for ; Fri, 28 Feb 2025 12:05:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740773111; x=1741377911; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=uGSGCt2jpgGQiVQiPTcoL8q2cRRPXF5PbYpq3+oes4A=; b=VfVd3we6lN1YPw16oa3mZuDhefLdIHWLDUZDjyAs4WtVoihzAI9mQS8iZF3gHrGVOW 5CD4BywXJqBu9YSn0/Dp84bXZ79JTGYOTm7q1C1zhSyroCTNO+UkcczhtbBSC0m/6QHJ yuJniBS/oU0fsdnUNY/Kx+vnP+nJcsy8OqZG4EY2ws8z8J+wGyh/AnicKqndleCgW0vQ 2CqJPeHvtk18MWNu526QGyGVfGyyQEi+/9xmAri7oh4zjvT+9A1FkAjd1n3Xovk6A7Nh emP6tYBDWieqyc2p5fPRb428hyEW9UDPYJws4BWIR6NXoFB3AsysYXdYP7FpqD9p4Muk H5KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773111; x=1741377911; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=uGSGCt2jpgGQiVQiPTcoL8q2cRRPXF5PbYpq3+oes4A=; b=CuFolIJ91skYw1dukzhGCW53uhuXrPRv49kEWps+crjA1F1nTnvtAjUpDYSFwuew31 bVW+7i6SdKqSKz29xR8PiXM8/FmgH3P7CUL0wIxg6p4pe8mB55yytit2PecgZn4Wb6DZ ARPsirAecTtdMw7JRs0sQ/Xb8oeIZO/KEhp8y1BgS5NjcLihTSVMRk9mo1Arb+mLlcg6 501r1iGrLqWdUwmqFaSGi0kyYUY5F2KMs6Vqs+TsMeiF82mKK9T/zSV6BwExWOMHX8yQ yppxcwboclv2/wBRtXA21eIOAMN0fnkn1inKP8ll29oEV8/VGXlNx/tYJkkZ9zGZW4wA mbsw== X-Gm-Message-State: AOJu0YyXJLWk4Ar/yEHorQgLQ2uhsY1R2pqn9YYOgQxOTRrkzajYVTNj f7MNng+UFlHvl+m0n7k246GYRK/q1qY0YkMepwvKZvWyZtzqfG/vCR9nnTlHc0pXKuyzahCJshC oAj/faicf/p2wb4sTnUuPK2GK9DHv2k5VdjlcelolHw2xJjAkmMBTXbU3q9iS9OLj0dVdtL+IA8 5yUTNT2ol3cnOzdQ4O9iWH5dpM1QuH5vLHTOVTYPz8jg== X-Google-Smtp-Source: AGHT+IFbZpM9s5UNjjeyIN6pD3JSGrNta9nwfz2pM99RKn4uczzIqfi9Nqb+BaigbskYx/PsDCW8yoqC2eMmuA== X-Received: from wmbg8.prod.google.com ([2002:a05:600c:a408:b0:439:846f:f9c8]) (user=whendrik job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6000:1faa:b0:38d:e6b6:508b with SMTP id ffacd0b85a97d-390ec7cd37fmr3818354f8f.9.1740773111082; Fri, 28 Feb 2025 12:05:11 -0800 (PST) Date: Fri, 28 Feb 2025 20:04:52 +0000 In-Reply-To: <20250228200453.45173-1-whendrik@google.com> Mime-Version: 1.0 References: <20250228200453.45173-1-whendrik@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250228200453.45173-7-whendrik@google.com> Subject: [PATCH v6 7/8] i386/cpu: Adjust CPUID level for RDT features From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, zhao1.liu@intel.com, xiaoyao.li@intel.com, Jonathan.Cameron@huawei.com, v6-0000-cover-letter.patch@google.com Cc: peternewman@google.com, Hendrik Wuethrich Received-SPF: pass client-ip=2a00:1450:4864:20::44a; envelope-from=39xbCZwgKCnImXUdThYaWeeWbU.SecgUck-TUlUbdedWdk.ehW@flex--whendrik.bounces.google.com; helo=mail-wr1-x44a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Adjust minimum CPUID level if RDT monitoring or allocation features are enabled to ensure that CPUID will return them. Signed-off-by: Hendrik Wuethrich --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6262665294..1ec3d88a65 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7872,6 +7872,16 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); } + + /* RDT monitoring requires CPUID[0xF] */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0xF); + } + + /* RDT allocation requires CPUID[0x10] */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x10); + } } /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ From patchwork Fri Feb 28 20:04:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hendrik Wuethrich X-Patchwork-Id: 13997035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED433C282C6 for ; Fri, 28 Feb 2025 20:06:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1to6bx-0005MC-S7; Fri, 28 Feb 2025 15:05:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3-BbCZwgKCnMnYVeUiZbXffXcV.TfdhVdl-UVmVcefeXel.fiX@flex--whendrik.bounces.google.com>) id 1to6bm-00059q-Aq for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:19 -0500 Received: from mail-wr1-x44a.google.com ([2a00:1450:4864:20::44a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3-BbCZwgKCnMnYVeUiZbXffXcV.TfdhVdl-UVmVcefeXel.fiX@flex--whendrik.bounces.google.com>) id 1to6bk-0001Al-Bz for qemu-devel@nongnu.org; Fri, 28 Feb 2025 15:05:18 -0500 Received: by mail-wr1-x44a.google.com with SMTP id ffacd0b85a97d-38f4c0c1738so2107118f8f.1 for ; Fri, 28 Feb 2025 12:05:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740773113; x=1741377913; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=T6l8npdxC324roaIdrme3w/FcKx3sGvjwIH9lVt7u+8=; b=CerSCiGw+ung4PEbdtyhmlBE313UoEAqhuVVwS4dQZA228PmElW9ZaR3HZ5QXC2dI5 p4scgA1YDJp1PaZrndlne5N3P5FAX8fvQTD+hz5vYLorI3UwgodUxw+s2qTXu3VlTA3f u+dqbAmPfTG8Rdav/72kDvZHiGjZiJg/uk+IGoh9L9LBSSXuNyd9luGwRgVIio4V0d7W ARedrRnVmfxVaA+IxJ/m35HrxuNSVcleQEEvor80X9naStS0JbOEvzNgreJA0mgrUwTE uhzAyQlj4WPeE5nWths/7PDlzmmLnRffSeF31Bx1ujPHwZ44qEo+REU9LXR2uMRufuFH eS5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773113; x=1741377913; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=T6l8npdxC324roaIdrme3w/FcKx3sGvjwIH9lVt7u+8=; b=ADMbrzyZp1IhYATU18XsV7Wt4NREdIdB0aEszHLSeN8oj69iWErecgIbGNYtS3dEFs HW1UYYmvH14RSWaxnGvqnifpOlSsYNcbFaWlxdAI/CJQJMM/lrnaVVX7D1eMU8JF4xvs kzFHmCcWqNKWjSQhP+qbblyedm3azJr0qVOLexeWH3RcsOQHg/eoEN0sdIR/YeaLsj8o HgZsY9eEqvbS++dlMWq7S8gQKpz+5bj9yOSWKBtvRmQI58f3EAJRpDRaKDfWmZhmKkf5 ifz7G9QhWCMoBQd5IulgKWoAMnS2DeANxJL1v+/Ro8um+bKQ9wreJLK3a7GG844UIH6m hmpw== X-Gm-Message-State: AOJu0YykSzTp9+dNRuV0athXHaGEJMqkZbRiZcWaclnTcBu06oA0ZM4K YKym5Cpj52/NvYM87Wj8LAiZk7OsDYxORKfxt8pTMs+OpSkLEUYAkctz7ALZcaPduhy6JS+MbcF ZPm1GUfudYwldpdrlhMSDhNAJ9HIBNjktokLJ67f48XkK+qGtftTVYPZPTED948LkBrRb6zKPBW IiehghgzqQDdN3g7Th6Gv9gJYBWrKqiMw/N3XQ5TzQRA== X-Google-Smtp-Source: AGHT+IGXOpJDqUEYXVp0Y50O72GYiqFNXjrYusgeUKsSM773D6PSE4XAHz4u4s7Woov0xziW0t8RI2r0vyjZFA== X-Received: from wrbee9.prod.google.com ([2002:a05:6000:2109:b0:38f:3f49:99e9]) (user=whendrik job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6000:18a6:b0:38a:8ace:85e8 with SMTP id ffacd0b85a97d-390eca5b4c5mr5511269f8f.44.1740773112991; Fri, 28 Feb 2025 12:05:12 -0800 (PST) Date: Fri, 28 Feb 2025 20:04:53 +0000 In-Reply-To: <20250228200453.45173-1-whendrik@google.com> Mime-Version: 1.0 References: <20250228200453.45173-1-whendrik@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250228200453.45173-8-whendrik@google.com> Subject: [PATCH v6 8/8] i386/cpu: Adjust level for RDT on full_cpuid_auto_level From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, zhao1.liu@intel.com, xiaoyao.li@intel.com, Jonathan.Cameron@huawei.com, v6-0000-cover-letter.patch@google.com Cc: peternewman@google.com, Hendrik Wuethrich Received-SPF: pass client-ip=2a00:1450:4864:20::44a; envelope-from=3-BbCZwgKCnMnYVeUiZbXffXcV.TfdhVdl-UVmVcefeXel.fiX@flex--whendrik.bounces.google.com; helo=mail-wr1-x44a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Make sure that RDT monitoring and allocation features are included in in full_cpuid_auto_level. Signed-off-by: Hendrik Wuethrich --- target/i386/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1ec3d88a65..55003760a6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7825,6 +7825,8 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_SVM); x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); + x86_cpu_adjust_feat_level(cpu, FEAT_RDT_F_0_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_RDT_10_0_EBX); /* Intel Processor Trace requires CPUID[0x14] */ if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {