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Tsirkin" , Marcel Apfelbaum , Jason Chien Subject: [PATCH 1/3] include/hw/pci: Attach BDF to Memory Attributes Date: Sun, 2 Mar 2025 17:12:07 +0800 Message-ID: <20250302091209.20063-2-jason.chien@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20250302091209.20063-1-jason.chien@sifive.com> References: <20250302091209.20063-1-jason.chien@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=jason.chien@sifive.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This commit adds the BDF to the memory attributes for DMA operations. Signed-off-by: Jason Chien --- include/hw/pci/pci_device.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index add208edfa..968f1ba3e9 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -244,6 +244,8 @@ static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr, void *buf, dma_addr_t len, DMADirection dir, MemTxAttrs attrs) { + attrs.unspecified = 0; + attrs.requester_id = pci_requester_id(dev); return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir, attrs); } @@ -292,6 +294,8 @@ static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, uint##_bits##_t *val, \ MemTxAttrs attrs) \ { \ + attrs.unspecified = 0; \ + attrs.requester_id = pci_requester_id(dev); \ return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \ } \ static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ @@ -299,6 +303,8 @@ static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, uint##_bits##_t val, \ MemTxAttrs attrs) \ { \ + attrs.unspecified = 0; \ + attrs.requester_id = pci_requester_id(dev); \ return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ } @@ -327,8 +333,8 @@ PCI_DMA_DEFINE_LDST(q_be, q_be, 64); static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t *plen, DMADirection dir) { - return dma_memory_map(pci_get_address_space(dev), addr, plen, dir, - MEMTXATTRS_UNSPECIFIED); + MemTxAttrs attrs = {.requester_id = pci_requester_id(dev)}; + return dma_memory_map(pci_get_address_space(dev), addr, plen, dir, attrs); } static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, From patchwork Sun Mar 2 09:12:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Chien X-Patchwork-Id: 13997784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC0A9C282D0 for ; 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Sun, 02 Mar 2025 01:12:24 -0800 (PST) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736310abc8csm2952616b3a.77.2025.03.02.01.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Mar 2025 01:12:23 -0800 (PST) From: Jason Chien To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Michael S. Tsirkin" , Marcel Apfelbaum , Jason Chien Subject: [PATCH 2/3] hw/riscv/riscv-iommu: Obtain Device IDs from Memory Attributes Date: Sun, 2 Mar 2025 17:12:08 +0800 Message-ID: <20250302091209.20063-3-jason.chien@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20250302091209.20063-1-jason.chien@sifive.com> References: <20250302091209.20063-1-jason.chien@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=jason.chien@sifive.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The bus number of a PCIe endpoint may change after PCIe re-enumeration, potentially causing the device ID stored in RISCVIOMMUSpace to become outdated. This can lead to an incorrect Device Directory Table walk. This commit ensures that the IOMMU dynamically retrieves the latest device IDs from the memory attributes of the requester devices, ensuring accuracy. Signed-off-by: Jason Chien --- hw/riscv/riscv-iommu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index d46beb2d64..b72ce8e6d0 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2644,7 +2644,13 @@ void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus, static int riscv_iommu_memory_region_index(IOMMUMemoryRegion *iommu_mr, MemTxAttrs attrs) { - return attrs.unspecified ? RISCV_IOMMU_NOPROCID : (int)attrs.pid; + RISCVIOMMUSpace *as = container_of(iommu_mr, RISCVIOMMUSpace, iova_mr); + + /* Requesters must attach its device ID. */ + g_assert(attrs.unspecified == 0); + + as->devid = attrs.requester_id; + return attrs.pid; } static int riscv_iommu_memory_region_index_len(IOMMUMemoryRegion *iommu_mr) From patchwork Sun Mar 2 09:12:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Chien X-Patchwork-Id: 13997785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02242C19F32 for ; Sun, 2 Mar 2025 09:13:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tofNF-0001FK-2V; Sun, 02 Mar 2025 04:12:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tofN9-0001D5-I5 for qemu-devel@nongnu.org; Sun, 02 Mar 2025 04:12:32 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tofN8-0003K0-28 for qemu-devel@nongnu.org; Sun, 02 Mar 2025 04:12:31 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-22349bb8605so67782305ad.0 for ; Sun, 02 Mar 2025 01:12:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1740906747; x=1741511547; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tjc4iz+I/x7TI5oB+jbfsG6hWaQKtW3nc06vJhmSDRc=; b=cgKXtxLAGPtWZykUgQigYVA+fbI1iskvdstBp5q3MRz6uuMw3L3Tg1OsFcScUpvfRP b/hEXQJfxQ8EH1dIwPjQNUHDhyFjrXa5Ye54SKoEwINqb2Qf3wHTRw8h/RkL7kg/PHFr EfimJOdC3uTzAApsmNrPHHarNkBAyIrjhxRD2OwGMbFrtZ/I8l4FECQ0JnbX6u7kkrD1 mLHG3DdA8VfOfaNZMBBXcUvFPY84y1oHK8FFq4/DhUlOr1baXq2n2dUg4+eBq60jacN3 bOJoViMkFW6agGC7EoD9/cXfuvIqTbfIOa+qBI0vtQPtd9yPIAchfagoDnroswlFpbvC SLsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740906747; x=1741511547; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tjc4iz+I/x7TI5oB+jbfsG6hWaQKtW3nc06vJhmSDRc=; b=q4Ye5iKVlxaPlvQlDWNMklHun5CtjOeWxkwdmFmnNbmGWgOtHUi8Y5MY4RmFJR6Tko QqVjZX8Gfc3WgUijmNaAk86lp56KpIN9U/6GQmuxNOkK5ezyv/ugNEgiW83vQooPAxCr /75km9+zbGa29lkJoQiz8D4yVoypbWptvyYMOfHPEzaiaJiS5KKygJxrG8flyVEJsgI5 lMWiHrSsoVQ65p02jZnqJ0iJa5TlP9PKKdekbget4JBtI4zt2HL+FLj24vb8mm3AkNB2 rTDtqwrrXE3c7OMKVT4NrH/UagzrqmJCZrTxlp9fajnSwtkVKbyomg6gYQl/UP/cBaj8 18/A== X-Gm-Message-State: AOJu0YyZZvgok3RLJ/h3Ep6NzdUqKREpGuiNPG15uNK1uEDx0Iis6P0T 6vQtiLWRzBpqcuX3UtvxW+uWUR10cW7ckbNiPMh0/PTULvL4P86PPvgqgRS/wSdN5MPn9Jhdjj1 pxTeYa68zNro61d20tT6PTyW9iiUy4fX3azPlr457FpJ09MVKlmcE8J50EJ+4M5orPl4QyfCi/m RgzRIaw+5XzFzmdzMPKDxpAyJZ1LJv1o1QaPAFMd4= X-Gm-Gg: ASbGnctO6ZlR+Wxyy6JSj+hIARdoJRILmY5ydeSmfPlhpcG2GVYile4gw079BwiIye9 TBuLgngI2h0f2eX9adhFO0y7K468FM3kghayvwE4rAatDIeQZ4pQDiL3f6jVPa8Kujo4YuMlNZp ntmfYdpED3qqH9Gb8ryGVVpQBwedpDlXDD+B06VhvBbdQ7UYlMgm7NddYQdZLjWLclBx0tRdM2t aJCViS7ZfuHMRpxuNd8XKmA4xWBIGmoKY8SsBXanroyrYIwNkPakEvT5Uy96zTxnAePVPMECGef A4cVP76UnKNuDbPBgphySPK55f4yKLVcmf/MiBdV35iUCbW0oT6nXakmFvZ+OB3en36Y4jx9 X-Google-Smtp-Source: AGHT+IEgEAPhg+7yznp98FSyzHyqEh+Zc7k3dE/DfQs8W+cbNG7D5sHOEZnJv59fcGFH7dmD3MCxzA== X-Received: by 2002:a05:6300:8095:b0:1f3:1eb8:7597 with SMTP id adf61e73a8af0-1f31eb88d4amr1172840637.35.1740906747350; Sun, 02 Mar 2025 01:12:27 -0800 (PST) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736310abc8csm2952616b3a.77.2025.03.02.01.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Mar 2025 01:12:26 -0800 (PST) From: Jason Chien To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Michael S. Tsirkin" , Marcel Apfelbaum , Jason Chien Subject: [PATCH 3/3] hw/riscv/riscv_iommu: Remove the "bus" property Date: Sun, 2 Mar 2025 17:12:09 +0800 Message-ID: <20250302091209.20063-4-jason.chien@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20250302091209.20063-1-jason.chien@sifive.com> References: <20250302091209.20063-1-jason.chien@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=jason.chien@sifive.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This property was originally intended to set the bus number for non-root endpoints. However, since the PCIe bus number is assigned and modified at runtime, setting this property before software execution is incorrect. Additionally, the property incorrectly assumes that all endpoints share the same bus, whereas no such restriction exists. With the IOMMU now retrieving the latest device IDs from memory attributes, there is no longer a need to set or update device IDs. Signed-off-by: Jason Chien --- hw/riscv/riscv-iommu.c | 7 ------- hw/riscv/riscv-iommu.h | 1 - 2 files changed, 8 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index b72ce8e6d0..1ca85b95ac 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -1197,9 +1197,6 @@ static AddressSpace *riscv_iommu_space(RISCVIOMMUState *s, uint32_t devid) { RISCVIOMMUSpace *as; - /* FIXME: PCIe bus remapping for attached endpoints. */ - devid |= s->bus << 8; - QLIST_FOREACH(as, &s->spaces, list) { if (as->devid == devid) { break; @@ -2261,9 +2258,6 @@ static MemTxResult riscv_iommu_trap_write(void *opaque, hwaddr addr, return MEMTX_ACCESS_ERROR; } - /* FIXME: PCIe bus remapping for attached endpoints. */ - devid |= s->bus << 8; - ctx = riscv_iommu_ctx(s, devid, 0, &ref); if (ctx == NULL) { res = MEMTX_ACCESS_ERROR; @@ -2498,7 +2492,6 @@ void riscv_iommu_reset(RISCVIOMMUState *s) static const Property riscv_iommu_properties[] = { DEFINE_PROP_UINT32("version", RISCVIOMMUState, version, RISCV_IOMMU_SPEC_DOT_VER), - DEFINE_PROP_UINT32("bus", RISCVIOMMUState, bus, 0x0), DEFINE_PROP_UINT32("ioatc-limit", RISCVIOMMUState, iot_limit, LIMIT_CACHE_IOT), DEFINE_PROP_BOOL("intremap", RISCVIOMMUState, enable_msi, TRUE), diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index a31aa62144..655c0e71a8 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -34,7 +34,6 @@ struct RISCVIOMMUState { /*< public >*/ uint32_t version; /* Reported interface version number */ uint32_t pid_bits; /* process identifier width */ - uint32_t bus; /* PCI bus mapping for non-root endpoints */ uint64_t cap; /* IOMMU supported capabilities */ uint64_t fctl; /* IOMMU enabled features */