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Mon, 3 Mar 2025 14:36:35 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250303143635eusmtrp2e1abc780f3982bbe24c4887ec03d920c~pUbshPPtu1887518875eusmtrp2o; Mon, 3 Mar 2025 14:36:35 +0000 (GMT) X-AuditID: cbfec7f4-c0df970000004fb9-9f-67c5be738c5d Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 8F.B0.19920.27EB5C76; Mon, 3 Mar 2025 14:36:34 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250303143634eusmtip26cc4ad15e7f62616c4f3ed35c439d379~pUbrjH7532028620286eusmtip2U; Mon, 3 Mar 2025 14:36:34 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Michal Wilczynski Subject: [PATCH v1 1/4] dt-bindings: clock: thead: Add TH1520 VO clock controller Date: Mon, 3 Mar 2025 15:36:26 +0100 Message-Id: <20250303143629.400583-2-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303143629.400583-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPKsWRmVeSWpSXmKPExsWy7djPc7rF+46mGyxZKW/x7M5XVoutv2ex W6zZe47JYv6Rc6wW9y5tYbJ4sbeRxaL52Ho2i5ez7rFZfOy5x2pxedccNottn1vYLNYeuctu sf7rfCaLi6dcLe7eO8Fi8fJyD7NF2yx+i/97drBb/Lu2kcWiZf8UFgcRj/c3Wtk93rx8yeJx uOMLu8e9E9NYPTat6mTz2Lyk3qNl7TEmj/6/Bh7v911l8+jbsorR41LzdXaPz5vkAniiuGxS UnMyy1KL9O0SuDJ2dnxlKliqUtG1bgFbA+M3mS5GTg4JAROJ1SdnM3YxcnEICaxglNhz+Qor hPOFUeLy6fXsEM5nRon7v26ywLRM+jcLzBYSWM4o8fSpD0TRG0aJ6R/OMoIk2ASMJB4snw82 SkRgD5PE9+8/mUEcZoFVjBJPvn0EmsvBISwQLPGmPQvEZBFQleg9UgzSyytgJ/H39Q5GiGXy EvsPnmUGsTkF7CUOXW9ggagRlDg58wmYzQxU07x1Nth4CYFLnBIXD8xlBZkpIeAi8WpZBcQc YYlXx7ewQ9gyEv93zmeCsPMlHmz9xAxh10js7DkOZVtL3Dn3iw1kDLOApsT6XfoQYUeJvacn MUFM55O48VYQ4gI+iUnbpjNDhHklOtqEIKrVJKb29MItPbdiG9RSD4mpi3YwT2BUnIXkl1lI fpmFsHcBI/MqRvHU0uLc9NRio7zUcr3ixNzi0rx0veT83E2MwDR5+t/xLzsYl7/6qHeIkYmD 8RCjBAezkgjvrfaj6UK8KYmVValF+fFFpTmpxYcYpTlYlMR5F+1vTRcSSE8sSc1OTS1ILYLJ MnFwSjUwRTHNEdl/4aKp34PUT1P8jPZeu3H+G5cUn/7vR4c+HIlWO5AvO/mr9MpGCX+HFitG rYKysqQPyj6/7x40m9T/rW5CS/D7TVP4rq3Zefldo1Dm5tvLCp/8NeZUC3/Cee6Ho8u/p+yy Fvyeq93/7ymM+/FmwuPVUyaz1xVVFFfv/ip+K3nrdRZGbosHm01cxVa9eH1Oqp5Nd03c46vR ef6+5Qs/fFs1syS8gmn67MKnH3skPPPUWXIOztma3CuRlj3119uHIcLLFBR2K1fPWeJ0zcAk IHR98u1LhzxrK4Tlzyl0PPibs65BpnzapMajn+Ya7N0aWJXXM23OMXWh6Ukr1Nfc3vNx5hLD 5K+N5torw5RYijMSDbWYi4oTAU3733YCBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrAIsWRmVeSWpSXmKPExsVy+t/xe7pF+46mGzw4ZGPx7M5XVoutv2ex W6zZe47JYv6Rc6wW9y5tYbJ4sbeRxaL52Ho2i5ez7rFZfOy5x2pxedccNottn1vYLNYeuctu sf7rfCaLi6dcLe7eO8Fi8fJyD7NF2yx+i/97drBb/Lu2kcWiZf8UFgcRj/c3Wtk93rx8yeJx uOMLu8e9E9NYPTat6mTz2Lyk3qNl7TEmj/6/Bh7v911l8+jbsorR41LzdXaPz5vkAnii9GyK 8ktLUhUy8otLbJWiDS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DJ2dnxlKliq UtG1bgFbA+M3mS5GTg4JAROJSf9msXQxcnEICSxllLhwfBYbREJG4lr3SxYIW1jiz7UusLiQ wCtGid5XwiA2m4CRxIPl81lBmkUELjBJ7Fq3mgnEYRZYxygxZfsOJpAqYYFAiUt9c9i7GDk4 WARUJXqPFIOEeQXsJP6+3sEIsUBeYv/Bs8wgNqeAvcSh6w0sEMvsJPas3ckOUS8ocXLmE7A4 M1B989bZzBMYBWYhSc1CklrAyLSKUSS1tDg3PbfYUK84Mbe4NC9dLzk/dxMjMKq3Hfu5eQfj vFcf9Q4xMnEwHmKU4GBWEuG91X40XYg3JbGyKrUoP76oNCe1+BCjKdDZE5mlRJPzgWklryTe 0MzA1NDEzNLA1NLMWEmc1+3y+TQhgfTEktTs1NSC1CKYPiYOTqkGJrlJFlVfA7ZK71XpVBRf u32rwkfFSZ4mr2ZfeDlB8t8j8+/6v2N8m+pXM+eu2jM1M7wmTX3G5In3U5c/iQu94vXqXNbV dcpxp9Jt8iXY/pYdefX2d5iw2oc+tW1fnCs+8grUhyh4KC66NzXCbVp0mVj3mmmPN05dpyF4 7bMx65o1c1gW2MmLrS8x1D5q7HDdhOs3b2hqcfK/nY0XTi5mzxfvWL/+5uonrBKTrCOyZi9a dUBCXaj58dV41qA9rHqGG71v2+f7VV1b9nKX8zfjiKRJbA7xlSvuN58+vKnnsUncHe+dy07c feZ9c/vluFMHGXIi3/Xtrel6ExO4U+yx2dbdwtvX1vAGNKjabbqm8UCJpTgj0VCLuag4EQDL IBdUcwMAAA== X-CMS-MailID: 20250303143635eucas1p1dbcd26d4906b962e07cbde7f5ef704bf X-Msg-Generator: CA X-RootMTR: 20250303143635eucas1p1dbcd26d4906b962e07cbde7f5ef704bf X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250303143635eucas1p1dbcd26d4906b962e07cbde7f5ef704bf References: <20250303143629.400583-1-m.wilczynski@samsung.com> Add device tree bindings for the TH1520 Video Output (VO) subsystem clock controller. The VO sub-system manages clock gates for multimedia components including HDMI, MIPI, and GPU. Document the VIDEO_PLL requirements for the VO clock controller, which receives its input from the AP clock controller. The VIDEO_PLL is a Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz with maximum FOUTVCO of 2376 MHz. Add a mandatory reset property for the TH1520 VO clock controller that handles the GPU clocks. This reset line controls the GPU CLKGEN reset, which is required for proper GPU clock operation. The reset property is only required for the "thead,th1520-clk-vo" compatible, as it specifically handles the GPU-related clocks. This binding complements the existing AP sub-system clock controller which manages CPU, DPU, GMAC and TEE PLLs. Signed-off-by: Michal Wilczynski Acked-by: Conor Dooley --- .../bindings/clock/thead,th1520-clk-ap.yaml | 33 ++++++++++++++++-- .../dt-bindings/clock/thead,th1520-clk-ap.h | 34 +++++++++++++++++++ 2 files changed, 64 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml index 0129bd0ba4b3..6ea8202718d0 100644 --- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller description: | The T-HEAD TH1520 AP sub-system clock controller configures the - CPU, DPU, GMAC and TEE PLLs. + CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures + the clock gates for the HDMI, MIPI and the GPU. SoC reference manual https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf @@ -20,14 +21,30 @@ maintainers: properties: compatible: - const: thead,th1520-clk-ap + enum: + - thead,th1520-clk-ap + - thead,th1520-clk-vo reg: maxItems: 1 clocks: items: - - description: main oscillator (24MHz) + - description: | + One input clock: + - For "thead,th1520-clk-ap": the clock input must be the 24 MHz + main oscillator. + - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, + which is configured by the AP clock controller. According to the + TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL + (integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with + a maximum FOUTVCO of 2376 MHz. + + resets: + maxItems: 1 + description: + Required for "thead,th1520-clk-vo". This reset line controls the + GPU CLKGEN reset which is required for proper GPU clock operation. "#clock-cells": const: 1 @@ -40,6 +57,16 @@ required: - clocks - "#clock-cells" +allOf: + - if: + properties: + compatible: + contains: + const: thead,th1520-clk-vo + then: + required: + - resets + additionalProperties: false examples: diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h index a199784b3512..09a9aa7b3ab1 100644 --- a/include/dt-bindings/clock/thead,th1520-clk-ap.h +++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h @@ -93,4 +93,38 @@ #define CLK_SRAM3 83 #define CLK_PLL_GMAC_100M 84 #define CLK_UART_SCLK 85 + +/* VO clocks */ +#define CLK_AXI4_VO_ACLK 0 +#define CLK_GPU_MEM 1 +#define CLK_GPU_CORE 2 +#define CLK_GPU_CFG_ACLK 3 +#define CLK_DPU_PIXELCLK0 4 +#define CLK_DPU_PIXELCLK1 5 +#define CLK_DPU_HCLK 6 +#define CLK_DPU_ACLK 7 +#define CLK_DPU_CCLK 8 +#define CLK_HDMI_SFR 9 +#define CLK_HDMI_PCLK 10 +#define CLK_HDMI_CEC 11 +#define CLK_MIPI_DSI0_PCLK 12 +#define CLK_MIPI_DSI1_PCLK 13 +#define CLK_MIPI_DSI0_CFG 14 +#define CLK_MIPI_DSI1_CFG 15 +#define CLK_MIPI_DSI0_REFCLK 16 +#define CLK_MIPI_DSI1_REFCLK 17 +#define CLK_HDMI_I2S 18 +#define CLK_X2H_DPU1_ACLK 19 +#define CLK_X2H_DPU_ACLK 20 +#define CLK_AXI4_VO_PCLK 21 +#define CLK_IOPMP_VOSYS_DPU_PCLK 22 +#define CLK_IOPMP_VOSYS_DPU1_PCLK 23 +#define CLK_IOPMP_VOSYS_GPU_PCLK 24 +#define CLK_IOPMP_DPU1_ACLK 25 +#define CLK_IOPMP_DPU_ACLK 26 +#define CLK_IOPMP_GPU_ACLK 27 +#define CLK_MIPIDSI0_PIXCLK 28 +#define CLK_MIPIDSI1_PIXCLK 29 +#define CLK_HDMI_PIXCLK 30 + #endif From patchwork Mon Mar 3 14:36:27 2025 Content-Type: text/plain; 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Mon, 3 Mar 2025 14:36:36 +0000 (GMT) X-AuditID: cbfec7f2-b09c370000005155-55-67c5be74b179 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 31.C0.19920.37EB5C76; Mon, 3 Mar 2025 14:36:35 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250303143635eusmtip26eaa624a46e587c544e1e90cca63e7d2~pUbsa-KwB2168421684eusmtip2I; Mon, 3 Mar 2025 14:36:34 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Michal Wilczynski Subject: [PATCH v1 2/4] clk: thead: Add clock support for VO subsystem in T-Head TH1520 SoC Date: Mon, 3 Mar 2025 15:36:27 +0100 Message-Id: <20250303143629.400583-3-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303143629.400583-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrIKsWRmVeSWpSXmKPExsWy7djPc7ol+46mGzxZLGPx7M5XVoutv2ex W6zZe47JYv6Rc6wW9y5tYbJ4sbeRxaL52Ho2i5ez7rFZfOy5x2pxedccNottn1vYLNYeuctu sf7rfCaLi6dcLe7eO8Fi8fJyD7NF2yx+i/97drBb/Lu2kcWiZf8UFgcRj/c3Wtk93rx8yeJx uOMLu8e9E9NYPTat6mTz2Lyk3qNl7TEmj/6/Bh7v911l8+jbsorR41LzdXaPz5vkAniiuGxS UnMyy1KL9O0SuDL+TGtlLXgXUbHly2bGBsYr3l2MnBwSAiYSr+dtZu5i5OIQEljBKPFp/nF2 COcLo8TXdbtYIZzPjBKd5y6zwbR8XfMCqmo5o8TxhyeYIJw3jBJH9/5kAqliEzCSeLB8Pli7 iMAeJonv33+CbWEWWMUo8eTbR3aQKmGBWIld8zewgNgsAqoSB459ANvBK2AncWHDQyaIffIS +w+eZQaxOQXsJQ5db2CBqBGUODnzCZjNDFTTvHU2M0T9OU6JdSdNIGwXibPbzrFA2MISr45v YYewZST+75wPNT9f4sHWT1C9NRI7e45D2dYSd879ArqHA2i+psT6XfoQYUeJaxvWM4KEJQT4 JG68FYS4gE9i0rbpzBBhXomONiGIajWJqT29cEvPrdjGBFHiIfFnesEERsVZSF6ZheSVWQhr FzAyr2IUTy0tzk1PLTbMSy3XK07MLS7NS9dLzs/dxAhMlaf/Hf+0g3Huq496hxiZOBgPMUpw MCuJ8N5qP5ouxJuSWFmVWpQfX1Sak1p8iFGag0VJnHfR/tZ0IYH0xJLU7NTUgtQimCwTB6dU A1N/usD0zoCXZ2Qfiq69Zx7HwhtlyyzBtfjVnp2lZes9ryW5BDxufKKU6sTDtOIrZzFLXnvl 2QfLXhiKy6zSUHygdHKKSv3Hr/3u6mFbt6WKr1Vhnp7j4CV4c+OK1xePn5BMnjQzOENAY7+u yU1f4S2tE8x1vr/n/6Xm8qF97qOVtjG+a1kObzGx1Dc6cvz34zP7ixtLF1qqiu14pH0jbeMS SWG7tP+L7ng/M5lwXoItsqRn6ZnIddu5buwV/Lpx5bPAvzoF9iY5349HBgnsEPyQ77dt+ek9 VwP2MHI/Xqew6+EC2TAF4SIdyyVtEx+L8Gzd/ORuYUW0huqaqScZOKPl7PcmHFRK1eZ5tDG7 OEKJpTgj0VCLuag4EQB5q6w9BAQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrIIsWRmVeSWpSXmKPExsVy+t/xe7rF+46mGzTPMrd4ducrq8XW37PY LdbsPcdkMf/IOVaLe5e2MFm82NvIYtF8bD2bxctZ99gsPvbcY7W4vGsOm8W2zy1sFmuP3GW3 WP91PpPFxVOuFnfvnWCxeHm5h9mibRa/xf89O9gt/l3byGLRsn8Ki4OIx/sbreweb16+ZPE4 3PGF3ePeiWmsHptWdbJ5bF5S79Gy9hiTR/9fA4/3+66yefRtWcXocan5OrvH501yATxRejZF +aUlqQoZ+cUltkrRhhZGeoaWFnpGJpZ6hsbmsVZGpkr6djYpqTmZZalF+nYJehl/prWyFryL qNjyZTNjA+MV7y5GTg4JAROJr2tesHcxcnEICSxllDi6bi8bREJG4lr3SxYIW1jiz7UuNoii V4wSi9/PBitiEzCSeLB8PitIQkTgApPErnWrmUAcZoF1jBJTtu8Acjg4hAWiJeb+lwRpYBFQ lThw7ANYM6+AncSFDQ+ZIDbIS+w/eJYZxOYUsJc4dL0BbLMQUM2etTvZIeoFJU7OfAIWZwaq b946m3kCo8AsJKlZSFILGJlWMYqklhbnpucWG+oVJ+YWl+al6yXn525iBMb1tmM/N+9gnPfq o94hRiYOxkOMEhzMSiK8t9qPpgvxpiRWVqUW5ccXleakFh9iNAW6eyKzlGhyPjCx5JXEG5oZ mBqamFkamFqaGSuJ87pdPp8mJJCeWJKanZpakFoE08fEwSnVwDTp2sV7U5RPq/wsc7xguESj YI14fOvZsOvl1RMOLkyb9Nzedv0KpomrvAwnv97C8jflyrTzPfZTNzW0c/YY1jjWHVbTuOjy 3meJq9xuvqe7BTeLT7R0fGea6LjM2TPJyaeawe+27rJpuy+LG++WmTNN/V+JTdErw09auXo5 4WwvNy5JedHFMTPvjrP989a1X5qT8rhsc5XjpQQt/lyTVN0rtvuChF5X7j7m4GN//dsPaHR9 nbba12BH/5QjM6c43Jz+JGb5nezJs6c+X92sF5SvvTg62H62c4rh5IM6X8/xdDn5ThFQ7RF4 3L5hz0zlCWwMEexZlTt3vXq7M9fag3mzkMaqtoPfV/3//CFt60QlluKMREMt5qLiRAA/aTQp dAMAAA== X-CMS-MailID: 20250303143636eucas1p2c8cb95fd5e8c36a114fd4b4c75ea4123 X-Msg-Generator: CA X-RootMTR: 20250303143636eucas1p2c8cb95fd5e8c36a114fd4b4c75ea4123 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250303143636eucas1p2c8cb95fd5e8c36a114fd4b4c75ea4123 References: <20250303143629.400583-1-m.wilczynski@samsung.com> The T-Head TH1520 SoC integrates a variety of clocks for its subsystems, including the Application Processor (AP) and the Video Output (VO) [1]. Up until now, the T-Head clock driver only supported AP clocks. This commit extends the driver to provide clock functionality for the VO subsystem. At this stage, the focus is on implementing the VO clock gates, as these are currently the most relevant and required components for enabling and disabling the VO subsystem functionality. Future enhancements may introduce additional VO-related clocks as necessary. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- drivers/clk/thead/clk-th1520-ap.c | 197 +++++++++++++++++++++++++----- 1 file changed, 169 insertions(+), 28 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index 4c9555fc6184..57972589f120 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -847,6 +847,67 @@ static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0); static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0); +static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", + video_pll_clk_pd, 0x0, BIT(0), 0); +static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, + 0x0, BIT(3), 0); +static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", + video_pll_clk_pd, 0x0, BIT(4), 0); +static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", + video_pll_clk_pd, 0x0, BIT(5), 0); +static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", + video_pll_clk_pd, 0x0, BIT(6), 0); +static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0, + BIT(7), 0); +static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0, + BIT(8), 0); +static CCU_GATE(CLK_DPU_CCLK, dpu_cclk, "dpu-cclk", video_pll_clk_pd, 0x0, + BIT(9), 0); +static CCU_GATE(CLK_HDMI_SFR, hdmi_sfr_clk, "hdmi-sfr-clk", video_pll_clk_pd, + 0x0, BIT(10), 0); +static CCU_GATE(CLK_HDMI_PCLK, hdmi_pclk, "hdmi-pclk", video_pll_clk_pd, 0x0, + BIT(11), 0); +static CCU_GATE(CLK_HDMI_CEC, hdmi_cec_clk, "hdmi-cec-clk", video_pll_clk_pd, + 0x0, BIT(12), 0); +static CCU_GATE(CLK_MIPI_DSI0_PCLK, mipi_dsi0_pclk, "mipi-dsi0-pclk", + video_pll_clk_pd, 0x0, BIT(13), 0); +static CCU_GATE(CLK_MIPI_DSI1_PCLK, mipi_dsi1_pclk, "mipi-dsi1-pclk", + video_pll_clk_pd, 0x0, BIT(14), 0); +static CCU_GATE(CLK_MIPI_DSI0_CFG, mipi_dsi0_cfg_clk, "mipi-dsi0-cfg-clk", + video_pll_clk_pd, 0x0, BIT(15), 0); +static CCU_GATE(CLK_MIPI_DSI1_CFG, mipi_dsi1_cfg_clk, "mipi-dsi1-cfg-clk", + video_pll_clk_pd, 0x0, BIT(16), 0); +static CCU_GATE(CLK_MIPI_DSI0_REFCLK, mipi_dsi0_refclk, "mipi-dsi0-refclk", + video_pll_clk_pd, 0x0, BIT(17), 0); +static CCU_GATE(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk, "mipi-dsi1-refclk", + video_pll_clk_pd, 0x0, BIT(18), 0); +static CCU_GATE(CLK_HDMI_I2S, hdmi_i2s_clk, "hdmi-i2s-clk", video_pll_clk_pd, + 0x0, BIT(19), 0); +static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk", + video_pll_clk_pd, 0x0, BIT(20), 0); +static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk", + video_pll_clk_pd, 0x0, BIT(21), 0); +static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk", + video_pll_clk_pd, 0x0, BIT(22), 0); +static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk, + "iopmp-vosys-dpu-pclk", video_pll_clk_pd, 0x0, BIT(23), 0); +static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vosys_dpu1_pclk, + "iopmp-vosys-dpu1-pclk", video_pll_clk_pd, 0x0, BIT(24), 0); +static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk, + "iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, BIT(25), 0); +static CCU_GATE(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-aclk", + video_pll_clk_pd, 0x0, BIT(27), 0); +static CCU_GATE(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-aclk", + video_pll_clk_pd, 0x0, BIT(28), 0); +static CCU_GATE(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-aclk", + video_pll_clk_pd, 0x0, BIT(29), 0); +static CCU_GATE(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, "mipi-dsi0-pixclk", + video_pll_clk_pd, 0x0, BIT(30), 0); +static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", + video_pll_clk_pd, 0x0, BIT(31), 0); +static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd, + 0x4, BIT(0), 0); + static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", &gmac_pll_clk.common.hw, 10, 1, 0); @@ -963,7 +1024,38 @@ static struct ccu_common *th1520_gate_clks[] = { &sram3_clk.common, }; -#define NR_CLKS (CLK_UART_SCLK + 1) +static struct ccu_common *th1520_vo_gate_clks[] = { + &axi4_vo_aclk.common, + &gpu_core_clk.common, + &gpu_cfg_aclk.common, + &dpu0_pixelclk.common, + &dpu1_pixelclk.common, + &dpu_hclk.common, + &dpu_aclk.common, + &dpu_cclk.common, + &hdmi_sfr_clk.common, + &hdmi_pclk.common, + &hdmi_cec_clk.common, + &mipi_dsi0_pclk.common, + &mipi_dsi1_pclk.common, + &mipi_dsi0_cfg_clk.common, + &mipi_dsi1_cfg_clk.common, + &mipi_dsi0_refclk.common, + &mipi_dsi1_refclk.common, + &hdmi_i2s_clk.common, + &x2h_dpu1_aclk.common, + &x2h_dpu_aclk.common, + &axi4_vo_pclk.common, + &iopmp_vosys_dpu_pclk.common, + &iopmp_vosys_dpu1_pclk.common, + &iopmp_vosys_gpu_pclk.common, + &iopmp_dpu1_aclk.common, + &iopmp_dpu_aclk.common, + &iopmp_gpu_aclk.common, + &mipi_dsi0_pixclk.common, + &mipi_dsi1_pixclk.common, + &hdmi_pixclk.common +}; static const struct regmap_config th1520_clk_regmap_config = { .reg_bits = 32, @@ -972,8 +1064,44 @@ static const struct regmap_config th1520_clk_regmap_config = { .fast_io = true, }; +struct th1520_plat_data { + struct ccu_common **th1520_pll_clks; + struct ccu_common **th1520_div_clks; + struct ccu_common **th1520_mux_clks; + struct ccu_common **th1520_gate_clks; + + int nr_clks; + int nr_pll_clks; + int nr_div_clks; + int nr_mux_clks; + int nr_gate_clks; +}; + +static const struct th1520_plat_data th1520_ap_platdata = { + .th1520_pll_clks = th1520_pll_clks, + .th1520_div_clks = th1520_div_clks, + .th1520_mux_clks = th1520_mux_clks, + .th1520_gate_clks = th1520_gate_clks, + + .nr_clks = CLK_UART_SCLK + 1, + + .nr_pll_clks = ARRAY_SIZE(th1520_pll_clks), + .nr_div_clks = ARRAY_SIZE(th1520_div_clks), + .nr_mux_clks = ARRAY_SIZE(th1520_mux_clks), + .nr_gate_clks = ARRAY_SIZE(th1520_gate_clks), +}; + +static const struct th1520_plat_data th1520_vo_platdata = { + .th1520_gate_clks = th1520_vo_gate_clks, + + .nr_clks = CLK_HDMI_PIXCLK + 1, + + .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), +}; + static int th1520_clk_probe(struct platform_device *pdev) { + const struct th1520_plat_data *plat_data; struct device *dev = &pdev->dev; struct clk_hw_onecell_data *priv; @@ -982,11 +1110,17 @@ static int th1520_clk_probe(struct platform_device *pdev) struct clk_hw *hw; int ret, i; - priv = devm_kzalloc(dev, struct_size(priv, hws, NR_CLKS), GFP_KERNEL); + plat_data = device_get_match_data(&pdev->dev); + if (!plat_data) { + dev_err(&pdev->dev, "Error: No device match data found\n"); + return -ENODEV; + } + + priv = devm_kzalloc(dev, struct_size(priv, hws, plat_data->nr_clks), GFP_KERNEL); if (!priv) return -ENOMEM; - priv->num = NR_CLKS; + priv->num = plat_data->nr_clks; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -996,35 +1130,35 @@ static int th1520_clk_probe(struct platform_device *pdev) if (IS_ERR(map)) return PTR_ERR(map); - for (i = 0; i < ARRAY_SIZE(th1520_pll_clks); i++) { - struct ccu_pll *cp = hw_to_ccu_pll(&th1520_pll_clks[i]->hw); + for (i = 0; i < plat_data->nr_pll_clks; i++) { + struct ccu_pll *cp = hw_to_ccu_pll(&plat_data->th1520_pll_clks[i]->hw); - th1520_pll_clks[i]->map = map; + plat_data->th1520_pll_clks[i]->map = map; - ret = devm_clk_hw_register(dev, &th1520_pll_clks[i]->hw); + ret = devm_clk_hw_register(dev, &plat_data->th1520_pll_clks[i]->hw); if (ret) return ret; priv->hws[cp->common.clkid] = &cp->common.hw; } - for (i = 0; i < ARRAY_SIZE(th1520_div_clks); i++) { - struct ccu_div *cd = hw_to_ccu_div(&th1520_div_clks[i]->hw); + for (i = 0; i < plat_data->nr_div_clks; i++) { + struct ccu_div *cd = hw_to_ccu_div(&plat_data->th1520_div_clks[i]->hw); - th1520_div_clks[i]->map = map; + plat_data->th1520_div_clks[i]->map = map; - ret = devm_clk_hw_register(dev, &th1520_div_clks[i]->hw); + ret = devm_clk_hw_register(dev, &plat_data->th1520_div_clks[i]->hw); if (ret) return ret; priv->hws[cd->common.clkid] = &cd->common.hw; } - for (i = 0; i < ARRAY_SIZE(th1520_mux_clks); i++) { - struct ccu_mux *cm = hw_to_ccu_mux(&th1520_mux_clks[i]->hw); + for (i = 0; i < plat_data->nr_mux_clks; i++) { + struct ccu_mux *cm = hw_to_ccu_mux(&plat_data->th1520_mux_clks[i]->hw); const struct clk_init_data *init = cm->common.hw.init; - th1520_mux_clks[i]->map = map; + plat_data->th1520_mux_clks[i]->map = map; hw = devm_clk_hw_register_mux_parent_data_table(dev, init->name, init->parent_data, @@ -1040,10 +1174,10 @@ static int th1520_clk_probe(struct platform_device *pdev) priv->hws[cm->common.clkid] = hw; } - for (i = 0; i < ARRAY_SIZE(th1520_gate_clks); i++) { - struct ccu_gate *cg = hw_to_ccu_gate(&th1520_gate_clks[i]->hw); + for (i = 0; i < plat_data->nr_gate_clks; i++) { + struct ccu_gate *cg = hw_to_ccu_gate(&plat_data->th1520_gate_clks[i]->hw); - th1520_gate_clks[i]->map = map; + plat_data->th1520_gate_clks[i]->map = map; hw = devm_clk_hw_register_gate_parent_data(dev, cg->common.hw.init->name, @@ -1057,19 +1191,21 @@ static int th1520_clk_probe(struct platform_device *pdev) priv->hws[cg->common.clkid] = hw; } - ret = devm_clk_hw_register(dev, &osc12m_clk.hw); - if (ret) - return ret; - priv->hws[CLK_OSC12M] = &osc12m_clk.hw; + if (plat_data == &th1520_ap_platdata) { + ret = devm_clk_hw_register(dev, &osc12m_clk.hw); + if (ret) + return ret; + priv->hws[CLK_OSC12M] = &osc12m_clk.hw; - ret = devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw); - if (ret) - return ret; - priv->hws[CLK_PLL_GMAC_100M] = &gmac_pll_clk_100m.hw; + ret = devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw); + if (ret) + return ret; + priv->hws[CLK_PLL_GMAC_100M] = &gmac_pll_clk_100m.hw; - ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); - if (ret) - return ret; + ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); + if (ret) + return ret; + } ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); if (ret) @@ -1081,6 +1217,11 @@ static int th1520_clk_probe(struct platform_device *pdev) static const struct of_device_id th1520_clk_match[] = { { .compatible = "thead,th1520-clk-ap", + .data = &th1520_ap_platdata, + }, + { + .compatible = "thead,th1520-clk-vo", + .data = &th1520_vo_platdata, }, { /* sentinel */ }, }; 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Mon, 3 Mar 2025 14:36:36 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250303143636eusmtrp140dd095e5b9115ee1e760911e56b4c0a~pUbuOFROt0893008930eusmtrp1c; Mon, 3 Mar 2025 14:36:36 +0000 (GMT) X-AuditID: cbfec7f4-c0df970000004fb9-a7-67c5be75bd0c Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 77.89.19654.47EB5C76; Mon, 3 Mar 2025 14:36:36 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250303143635eusmtip2111d49015de186ff013ab1487cc7515c~pUbtRgu4p2137621376eusmtip2U; Mon, 3 Mar 2025 14:36:35 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Michal Wilczynski Subject: [PATCH v1 3/4] clk: thead: Add support for custom ops in CCU_GATE_CLK_OPS macro Date: Mon, 3 Mar 2025 15:36:28 +0100 Message-Id: <20250303143629.400583-4-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303143629.400583-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrIKsWRmVeSWpSXmKPExsWy7djPc7ql+46mG/ycJGvx7M5XVoutv2ex W6zZe47JYv6Rc6wW9y5tYbJ4sbeRxaL52Ho2i5ez7rFZfOy5x2pxedccNottn1vYLNYeuctu sf7rfCaLi6dcLe7eO8Fi8fJyD7NF2yx+i/97drBb/Lu2kcWiZf8UFgcRj/c3Wtk93rx8yeJx uOMLu8e9E9NYPTat6mTz2Lyk3qNl7TEmj/6/Bh7v911l8+jbsorR41LzdXaPz5vkAniiuGxS UnMyy1KL9O0SuDIOnlnNXLBCtGLZtUUsDYzrBbsYOTkkBEwkHr1fzNbFyMUhJLCCUaL9ajuU 84VR4kVTBxNIlZDAZ0aJlS+TYDruPf3FAlG0nFFi77M5TBDOG0aJGYfvgnWwCRhJPFg+nxUk ISKwh0ni+/efzCAOs8AqRokn3z6yg1QJC0RJvP9/HcxmEVCVWLTvDFg3r4CdxLLGt4wQ++Ql 9h88ywxicwrYSxy63sACUSMocXLmEzCbGaimeetssAUSAuc4JU4s+MEG0ewicXnjbSYIW1ji 1fEt7BC2jMTpyT0sEHa+xIOtn5gh7BqJnT3HoWxriTvnfgHN4QBaoCmxfpc+RNhRomnJaVaQ sIQAn8SNt4IQJ/BJTNo2nRkizCvR0SYEUa0mMbWnF27puRXbmCBKPCR2dupMYFScheSXWUh+ mYWwdgEj8ypG8dTS4tz01GKjvNRyveLE3OLSvHS95PzcTYzAVHn63/EvOxiXv/qod4iRiYPx EKMEB7OSCO+t9qPpQrwpiZVVqUX58UWlOanFhxilOViUxHkX7W9NFxJITyxJzU5NLUgtgsky cXBKNTDN3cM960P0FskZaWrVjjFbfhy5f+KW4d4Ji8qWZu13r6lJ/xUotOhm9d1Fa/YLbUns 7AmIMr23kLU59mYEh+ni15uf6dQ/1Zv3/ufvlZvuGy/dEXOXN+HnMull366uNVsam2Btse/S z9CMHc8n/wptVnfZqaMUc/ZOzLLVJac5L2xTkVqwKsopp/ZDx2Kf4w/OffF2+OjFP0Hl9dkZ 05s3r+OY8157/85PTZXrhQ6XGF+4tuuW368VdkFH92SVMVkvWHy0rO6b+1nPLUfLFOzvN69T ZlLMsKi7qNO447TtOftn7VvEH982MmJ/NsVde5PVfbED98RUuj79ZNG0Lb/w9MYibj2JvIfS p5/lLg5KPqXEUpyRaKjFXFScCACvHrjQBAQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEIsWRmVeSWpSXmKPExsVy+t/xe7ol+46mGxxbY2Lx7M5XVoutv2ex W6zZe47JYv6Rc6wW9y5tYbJ4sbeRxaL52Ho2i5ez7rFZfOy5x2pxedccNottn1vYLNYeuctu sf7rfCaLi6dcLe7eO8Fi8fJyD7NF2yx+i/97drBb/Lu2kcWiZf8UFgcRj/c3Wtk93rx8yeJx uOMLu8e9E9NYPTat6mTz2Lyk3qNl7TEmj/6/Bh7v911l8+jbsorR41LzdXaPz5vkAnii9GyK 8ktLUhUy8otLbJWiDS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DIOnlnNXLBC tGLZtUUsDYzrBbsYOTkkBEwk7j39xdLFyMUhJLCUUeLEipNMEAkZiWvdL1kgbGGJP9e62CCK XjFKdC5YwAiSYBMwkniwfD4rSEJE4AKTxK51q5lAHGaBdYwSU7bvABslLBAh0Xf8EDOIzSKg KrFo3xmwOK+AncSyxreMECvkJfYfPAtWwylgL3HoegPYaiGgmj1rd7JD1AtKnJz5BCzODFTf vHU28wRGgVlIUrOQpBYwMq1iFEktLc5Nzy020itOzC0uzUvXS87P3cQIjOxtx35u2cG48tVH vUOMTByMhxglOJiVRHhvtR9NF+JNSaysSi3Kjy8qzUktPsRoCnT3RGYp0eR8YGrJK4k3NDMw NTQxszQwtTQzVhLnZbtyPk1IID2xJDU7NbUgtQimj4mDU6qBaeoOhpUbK+88vV/OuUBAcN/f BI9j+xoPC0uEx3vqWZ3nyirumjDt6co2NvbtZUeXZcd3G1t8Dm/da7d0N2+CT6nky0d71y/4 HS0pUHn++b3F7tm7HntfXiy99Ma/BI0/L86eCEk+e+vCsa3bojdfsjyZFxOSMXOTyXupIywh Bx9IF/9cum/OzL8bIid/7N0SfPtCqOaZqAqj2MmPPvyU1Du2JdngWOCn/y951UO/BBnecmnm b736TevA1blGsx99UPLS8pn6bcGsg9PCTH/leMwJ2mc36fHLSex5Umd5Nn0Qi2MrvXe4xnvR ycY5E1c9F+KK3ir6KrW712dt2u23t7XbEszjZ0yJbRA99beLLYFbiaU4I9FQi7moOBEAbWgs dnUDAAA= X-CMS-MailID: 20250303143636eucas1p1c3ca1df44b86efff959c1d5ec016c8ae X-Msg-Generator: CA X-RootMTR: 20250303143636eucas1p1c3ca1df44b86efff959c1d5ec016c8ae X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250303143636eucas1p1c3ca1df44b86efff959c1d5ec016c8ae References: <20250303143629.400583-1-m.wilczynski@samsung.com> The IMG Rogue GPU requires three clocks: core, sys, and mem [1]. On the T-HEAD TH1520 SoC, the mem clock gate is marked as "Reserved" in the hardware manual (section 4.4.2.6.1) [2] and cannot be configured. Add a new CCU_GATE_CLK_OPS macro that allows specifying custom clock operations. This enables us to use nop operations for the mem clock, preventing the driver from attempting to enable/disable this reserved clock gate. Link: https://lore.kernel.org/all/2fe3d93f-62ac-4439-ac17-d81137f6410a@imgtec.com [1] Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [2] Signed-off-by: Michal Wilczynski --- drivers/clk/thead/clk-th1520-ap.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index 57972589f120..ea96d007aecd 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -89,6 +89,21 @@ struct ccu_pll { } \ } +#define CCU_GATE_CLK_OPS(_clkid, _struct, _name, _parent, _reg, _gate, _flags, \ + _clk_ops) \ + struct ccu_gate _struct = { \ + .enable = _gate, \ + .common = { \ + .clkid = _clkid, \ + .cfg0 = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA( \ + _name, \ + _parent, \ + &_clk_ops, \ + _flags), \ + } \ + } + static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) { return container_of(hw, struct ccu_common, hw); @@ -847,6 +862,11 @@ static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0); static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0); +static const struct clk_ops clk_nop_ops = {}; + +static CCU_GATE_CLK_OPS(CLK_GPU_MEM, gpu_mem_clk, "gpu-mem-clk", + video_pll_clk_pd, 0x0, BIT(2), 0, clk_nop_ops); + static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", video_pll_clk_pd, 0x0, BIT(0), 0); static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, @@ -1205,6 +1225,12 @@ static int th1520_clk_probe(struct platform_device *pdev) ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); if (ret) return ret; + } else if (plat_data == &th1520_vo_platdata) { + ret = devm_clk_hw_register(dev, &gpu_mem_clk.common.hw); + if (ret) + return ret; + gpu_mem_clk.common.map = map; + priv->hws[CLK_GPU_MEM] = &gpu_mem_clk.common.hw; } ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); 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Mon, 3 Mar 2025 14:36:37 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250303143637eusmtrp2a9001e7e4370175b5446fad2aa8949e6~pUbvCc2Y01887518875eusmtrp2r; Mon, 3 Mar 2025 14:36:37 +0000 (GMT) X-AuditID: cbfec7f2-b11c470000005155-60-67c5be769d64 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 03.C0.19920.57EB5C76; Mon, 3 Mar 2025 14:36:37 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250303143636eusmtip26d8b366318502581e33c26828353764e~pUbuKTvar2028620286eusmtip2V; Mon, 3 Mar 2025 14:36:36 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Michal Wilczynski Subject: [PATCH v1 4/4] clk: thead: Add GPU clock gate control with CLKGEN reset support Date: Mon, 3 Mar 2025 15:36:29 +0100 Message-Id: <20250303143629.400583-5-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303143629.400583-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf0wTZxjHfe+ud1ek7qwsvEPjpMYSHaIYt7wZC2xjLDczE+f2F7pIJ5dC RgvrAcMfkXal2GnnFpmUVUyN02gqjNnRWgjSrZSWUSyROiEEOpgyBHEMEZ1jwGgPN//7PN/n +zzf90leGpdOiRLofHUxp1ErCmRkDOH0PQluLm1tV26t+0eMfh+YESHHrIVCddeCGLJ6gyIU 7mnE0N1rOgLpfQ0kGrOESTRlCotQqLmWRM7pChLVewcp1DBjxdCNziw0GO4g0FjIhKNKy3No ocVFoflbVwhU4f6aeD2OnewzUOzE2BjBthkfUmy4o1rE2m2fk+wP58vZinofxn45t5WdbP2F ZE802gDbo++l2Gn72l2x2TGv5XIF+aWcZkt6TkxeW1e9qGh2c9m8cQZoQYf8GBDTkNkOx8+Y qWMghpYylwD0VJ0gheIhgFVtrbhQTAN4y+sSPR1x+S4TEZYyFwEcdEkF0wSA3lFftEEy2+DQ Raso0ohjWjD4+PGT6CqcsQF459EUFXGtYrLhpO776ATBbIBzxqGoLmHS4W/6m6QQ9yJ0/3Qd j7CYyYCeXi0heFbCn7+5E2V80aN3nI4GQKZTDKs7+5eG34ILwz2UwKvguL9xidfAhSYrJnAh HHI8wAU+DJtM/iVOgwPBvxf30IsBG2FD8xZBfgPevucGERkyK2Df/ZXCE1bAk04zLsgSaKyU Cm45PGX64r/Q4CUnJlhYaJ/48CuQaHnmFsszt1j+jz0LcBuI50p4lZLjU9Xcpym8QsWXqJUp +wtVdrD4KwPz/gcucGZ8KsUDMBp4AKRxWZyk/2i7UirJVRw4yGkK92lKCjjeA1bThCxecs5t UEoZpaKY+5jjijjN0y5GixO0mNmUVZd8dPl78eeTdeWOP9fXjNhUf2R0WZN0Ly/LD2mP/AUN V+RXd3y27Mi5rsoRS/zBV/O/myUPyZyxLWeTZkX7c606fy2oURef1L4Dwi+lkbsKuwZv+mJP 9fWPZhdX/bop8Ahfe2+HynDBpwmllZV2H17Y9rwxIfCBu7v3dirzyh5jDtcsKUNXzc3l9fI1 iQFvQlZB4gtv80UjmddzRq3rku9Cazqao93mH9O19/u3v79OPlztP+6afxPb03PakalXZNqS Wx0f9Y7M7ZW7WtprvlXxNxRJjbtrNzje1a8OHBqQXN7pY9uXj5qP7zVaTd0hxtBkV+TVGYcP ZHzCygg+T5G6Cdfwin8B+GQTcgQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEIsWRmVeSWpSXmKPExsVy+t/xe7ql+46mG2z8p2Px7M5XVoutv2ex W6zZe47JYv6Rc6wW9y5tYbJ4sbeRxaL52Ho2i5ez7rFZfOy5x2pxedccNottn1vYLNYeuctu sf7rfCaLi6dcLe7eO8Fi8fJyD7NF2yx+i/97drBb/Lu2kcWiZf8UFgcRj/c3Wtk93rx8yeJx uOMLu8e9E9NYPTat6mTz2Lyk3qNl7TEmj/6/Bh7v911l8+jbsorR41LzdXaPz5vkAnii9GyK 8ktLUhUy8otLbJWiDS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DIOn1nLWvBb t+Jfx1fGBsYTal2MnBwSAiYSO46tZuli5OIQEljKKHFr5w1miISMxLXulywQtrDEn2tdbBBF rxgl5j74wgiSYBMwkniwfD4rSEJE4AKTxK51q5lAHGaBdYwSU7bvYAKpEhaIkHi3oA1sLIuA qsTfjgfsIDavgJ3Eo+YrbBAr5CX2HzwLVsMpYC9x6HoD2GohoJo9a3dC1QtKnJz5BCzODFTf vHU28wRGgVlIUrOQpBYwMq1iFEktLc5Nzy021CtOzC0uzUvXS87P3cQIjOxtx35u3sE479VH vUOMTByMhxglOJiVRHhvtR9NF+JNSaysSi3Kjy8qzUktPsRoCnT3RGYp0eR8YGrJK4k3NDMw NTQxszQwtTQzVhLndbt8Pk1IID2xJDU7NbUgtQimj4mDU6qBiXlJysKLziEzG2MenlIKElzq OOXAX8bJp20+JXKf4VbcspfvZ4HafwaravVFfY8uBdv3KlwLPGKy5VdeEmtD0NKSc3sSLuZw 1uQffzrpzTW/zllzZyXolyz+/DNvV9qWzZaOJ+f+N4r0SlR5ZjWTbeVWj2clNx2ChdTKq2ov tP90Y/34oJKp9rn67Jq8RYkhJ5dZPC/k+7nlIOuKn7p7ts5YINf37uneWa5HI68+CAv0n/R0 p3x/KlON44knX34ni1zxe6lyWSJDN2NCc0yCaaSHe3h+fB3vdocrR1g6s46mdFrYyP/c++Pg q7ri779vvjLNqnxVqxMfbPpCPIf3qH6d0DObaxVNZfX7/oQYKrEUZyQaajEXFScCACXhFKN1 AwAA X-CMS-MailID: 20250303143637eucas1p1a3abdea520ab88688de1263a5f07bba0 X-Msg-Generator: CA X-RootMTR: 20250303143637eucas1p1a3abdea520ab88688de1263a5f07bba0 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250303143637eucas1p1a3abdea520ab88688de1263a5f07bba0 References: <20250303143629.400583-1-m.wilczynski@samsung.com> The T-HEAD TH1520 has three GPU clocks: core, cfg, and mem. The mem clock gate is marked as "Reserved" in hardware, while core and cfg are configurable. In order for these clock gates to work properly, the CLKGEN reset must be managed in a specific sequence. Move the CLKGEN reset handling to the clock driver since it's fundamentally a clock-related workaround [1]. This ensures that clk_enabled GPU clocks stay physically enabled without external interference from the reset driver. The reset is now deasserted only when both core and cfg clocks are enabled, and asserted when either of them is disabled. The mem clock is configured to use nop operations since it cannot be controlled. Link: https://lore.kernel.org/all/945fb7e913a9c3dcb40697328b7e9842b75fea5c.camel@pengutronix.de [1] Signed-off-by: Michal Wilczynski --- drivers/clk/thead/clk-th1520-ap.c | 87 ++++++++++++++++++++++++++++--- 1 file changed, 81 insertions(+), 6 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index ea96d007aecd..1dfcde867233 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -12,6 +12,7 @@ #include #include #include +#include #define TH1520_PLL_POSTDIV2 GENMASK(26, 24) #define TH1520_PLL_POSTDIV1 GENMASK(22, 20) @@ -862,17 +863,70 @@ static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0); static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0); +static struct reset_control *gpu_reset; +static DEFINE_SPINLOCK(gpu_reset_lock); /* protect GPU reset sequence */ + +static void ccu_gpu_clk_disable(struct clk_hw *hw); +static int ccu_gpu_clk_enable(struct clk_hw *hw); + +static const struct clk_ops ccu_gate_gpu_ops = { + .disable = ccu_gpu_clk_disable, + .enable = ccu_gpu_clk_enable +}; + static const struct clk_ops clk_nop_ops = {}; static CCU_GATE_CLK_OPS(CLK_GPU_MEM, gpu_mem_clk, "gpu-mem-clk", video_pll_clk_pd, 0x0, BIT(2), 0, clk_nop_ops); +static CCU_GATE_CLK_OPS(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", + video_pll_clk_pd, 0x0, BIT(3), 0, ccu_gate_gpu_ops); +static CCU_GATE_CLK_OPS(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", + video_pll_clk_pd, 0x0, BIT(4), 0, ccu_gate_gpu_ops); + +static void ccu_gpu_clk_disable(struct clk_hw *hw) +{ + struct ccu_gate *cg = hw_to_ccu_gate(hw); + unsigned long flags; + + spin_lock_irqsave(&gpu_reset_lock, flags); + + ccu_disable_helper(&cg->common, cg->enable); + + if ((cg == &gpu_core_clk && + !clk_hw_is_enabled(&gpu_cfg_aclk.common.hw)) || + (cg == &gpu_cfg_aclk && + !clk_hw_is_enabled(&gpu_core_clk.common.hw))) + reset_control_assert(gpu_reset); + + spin_unlock_irqrestore(&gpu_reset_lock, flags); +} + +static int ccu_gpu_clk_enable(struct clk_hw *hw) +{ + struct ccu_gate *cg = hw_to_ccu_gate(hw); + unsigned long flags; + int ret; + + spin_lock_irqsave(&gpu_reset_lock, flags); + + ret = ccu_enable_helper(&cg->common, cg->enable); + if (ret) { + spin_unlock_irqrestore(&gpu_reset_lock, flags); + return ret; + } + + if ((cg == &gpu_core_clk && + clk_hw_is_enabled(&gpu_cfg_aclk.common.hw)) || + (cg == &gpu_cfg_aclk && clk_hw_is_enabled(&gpu_core_clk.common.hw))) + ret = reset_control_deassert(gpu_reset); + + spin_unlock_irqrestore(&gpu_reset_lock, flags); + + return ret; +} static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", video_pll_clk_pd, 0x0, BIT(0), 0); -static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, - 0x0, BIT(3), 0); -static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", - video_pll_clk_pd, 0x0, BIT(4), 0); static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", video_pll_clk_pd, 0x0, BIT(5), 0); static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", @@ -1046,8 +1100,6 @@ static struct ccu_common *th1520_gate_clks[] = { static struct ccu_common *th1520_vo_gate_clks[] = { &axi4_vo_aclk.common, - &gpu_core_clk.common, - &gpu_cfg_aclk.common, &dpu0_pixelclk.common, &dpu1_pixelclk.common, &dpu_hclk.common, @@ -1150,6 +1202,13 @@ static int th1520_clk_probe(struct platform_device *pdev) if (IS_ERR(map)) return PTR_ERR(map); + if (plat_data == &th1520_vo_platdata) { + gpu_reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(gpu_reset)) + return dev_err_probe(dev, PTR_ERR(gpu_reset), + "GPU reset is required for VO clock controller\n"); + } + for (i = 0; i < plat_data->nr_pll_clks; i++) { struct ccu_pll *cp = hw_to_ccu_pll(&plat_data->th1520_pll_clks[i]->hw); @@ -1226,11 +1285,27 @@ static int th1520_clk_probe(struct platform_device *pdev) if (ret) return ret; } else if (plat_data == &th1520_vo_platdata) { + /* GPU clocks need to be treated differently, as MEM clock + * is non-configurable, and the reset needs to be de-asserted + * after enabling CORE and CFG clocks. + */ ret = devm_clk_hw_register(dev, &gpu_mem_clk.common.hw); if (ret) return ret; gpu_mem_clk.common.map = map; priv->hws[CLK_GPU_MEM] = &gpu_mem_clk.common.hw; + + ret = devm_clk_hw_register(dev, &gpu_core_clk.common.hw); + if (ret) + return ret; + gpu_core_clk.common.map = map; + priv->hws[CLK_GPU_CORE] = &gpu_core_clk.common.hw; + + ret = devm_clk_hw_register(dev, &gpu_cfg_aclk.common.hw); + if (ret) + return ret; + gpu_cfg_aclk.common.map = map; + priv->hws[CLK_GPU_CFG_ACLK] = &gpu_cfg_aclk.common.hw; } ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv);