From patchwork Mon Mar 3 17:00:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues KAMBA MPIANA X-Patchwork-Id: 13999219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4FA5C282CD for ; Mon, 3 Mar 2025 17:02:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VrTLtcaZKqpt4oNPAsTWCDaLlzxxZriU22/qH3PS1xg=; b=nsifeJq3svqDtLAmVwUo6pAwvd TBNeYTr4q2Pq07trPRkdEgZEnA2a3ZnEBnoctjBbO2aXEK0PC97nOQZBmh5ZjrblD0Lf2LuIitiDr LIOvpdhrpZF425eAVobK8rIfvhmXKykuzUIEnw4uT/kDxI+aBdltG3aCqQJ9Dk1x+QoxcHm7feBi2 jg6daC+IbDVOchG5p80G+NL/A8Tv7h3ztcw9ua0WKmoEMacd7GoCmVX18sawiAMQZRb+HoVO7RtkN Zzpce/kuep9aS8bC4OEHd49m8xa+DEJBIaxD4nvHJOI19K6gHJOUhNuFaSEV922XaxyWkJgORO3+r MQNCQ1cw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tp9B3-00000001erU-2ioN; Mon, 03 Mar 2025 17:02:01 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tp99T-00000001ebv-2KBA for linux-arm-kernel@lists.infradead.org; Mon, 03 Mar 2025 17:00:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5DA57106F; Mon, 3 Mar 2025 09:00:35 -0800 (PST) Received: from e129527.arm.com (unknown [10.57.67.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 344C03F673; Mon, 3 Mar 2025 09:00:19 -0800 (PST) From: Hugues KAMBA MPIANA To: sudeep.holla@arm.com Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, hugues.kambampiana@arm.com, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, liviu.dudau@arm.com, lpieralisi@kernel.org, robh@kernel.org Subject: [PATCH v2] arm64: dts: corstone1000: Add definitions for secondary CPU cores Date: Mon, 3 Mar 2025 17:00:12 +0000 Message-Id: <20250303170012.469576-1-hugues.kambampiana@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250303_090023_633977_10E315A2 X-CRM114-Status: GOOD ( 10.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to enable support for secondary CPU cores. This update facilitates symmetric multiprocessing (SMP) support on the Corstone1000 Fixed Virtual Platform (FVP), allowing the secondary cores to be properly initialised and utilised. Only FVP platform will have SMP support and hence the secondary cpu definitions are not added to corstone1000.dtsi. Signed-off-by: Hugues KAMBA MPIANA --- arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 24 ++++++++++++++++++++ arch/arm64/boot/dts/arm/corstone1000.dtsi | 2 +- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts index abd013562995..df9700302b8d 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -49,3 +49,27 @@ sdmmc1: mmc@50000000 { clock-names = "smclk", "apb_pclk"; }; }; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index bb9b96fb5314..b4364c61901c 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -21,7 +21,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>;