From patchwork Mon Mar 3 22:53:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13999591 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA88223958C for ; Mon, 3 Mar 2025 22:53:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741042395; cv=none; b=OSF8kMjG9GePkmwpmaRkz5CgBkg+K/9GJNuFlZRfpvOgAP5QE4wl4wJbNpZJ8/42u4x5GhGGzwgKeaLbbix4DbqVtaKq/nvhidv81dTzhkykOYOG+zF5f3JhjmoI7P2xNfZBB+fldJhsaFVpApTHdWkYFBzCdoCW8Vt46wvQo6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741042395; c=relaxed/simple; bh=DxQuXHMlgc7H5Iz7LRmGc2M8YCqPk4tOjdxPmN2FNfI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ry0dQW4qkVxNDgAleRy3TcG11T+WgaNvl8up5Qauc5zTbvzYb1A19JKG6OikfHm5lE+NFEQ5yZpRMAs4NyhZFSlf93J4q/6FPasLag5mIJniXDf7cbDGMljI1HCQQdZxRcaTVMQv9BklX2/O6xgdDBUCXhuh0+9qPgF1qTMgq/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=WdJuMiIk; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="WdJuMiIk" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-2239aa5da08so32746355ad.3 for ; Mon, 03 Mar 2025 14:53:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741042393; x=1741647193; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mugBhowmjHeOZ8voD78niLPk8kFDSWBL6lZCl8cn1Qg=; b=WdJuMiIkIs3pUQXpxz7Z9HmUtPvCC79mJk/occ7KYGG/aZdiOmBHRmCNJhdTOf3/ef ovpBWaFkZU/v2DMGUw9V6pXveZmqaYiGBC56j7XIAZad2ocyzUG4D6T6+hEk5gaP94Fw VsXkGx+7uzLOu6QNKgxQZDi4HxBscik0se8xvAPweYri0I7hRmHEPx0d0wqW2CcqCN/h N4o+RyBR5xgif1GKI770sWlsnhnzzyufnWMaoEritGhZ29py8V5tvja0pu0oehAjlZy+ 7I/spmdEj4WD2ny8Xc1m55EZRBYIwT6a33H+8dc1T906V1Jmn7Qk8d7bPbSMbFd/dkTJ xihw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741042393; x=1741647193; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mugBhowmjHeOZ8voD78niLPk8kFDSWBL6lZCl8cn1Qg=; b=ZMgaZqf8fBVF6ltXpO/4GHIQYdf5V6pIZr1d51wGx4H2b/jpHWYuIRrYtBTVt7aKI8 tOfnHlIBIBbICjNSm0wapbrzVCB8E/6RacfhUbR9+cmlc+dllEA0njwbolh78ElytxWt iAd+fGKvnKBtYg1RDfMFozv+RYTXxSeGuWIUSZeocgB9VEyCcVhoAeTe3VJaPSOak8Xt GmZnzMc804+UsHBslkp7mKGNghiDRw+5SpHxKtKdFcW1b7JOvEXiOc81J9t1BEpDnqTv V0SWcOuStFuceWCKH8305QuwQCsu/YwRFgMQhHoI0/8eyH5GHm/VFT+LTOSZ8NA7poR+ oWIg== X-Gm-Message-State: AOJu0YwFtoIwkMpQCImCwLLkMSaiNKS+jJXeR4tYiOh8DdsoIJ2xRYLu HgxeRk2kUFO5DSkUgF/ZwMM6N3PV+8bhNv1aFGLxjG6NG+qAfiIKo8UCN5p5hMo= X-Gm-Gg: ASbGncsBeFAwwe2Kbg1afWl4NMAHcxj8zjod/GdXAcSrNSZsfbhB0oM6tIFSext4ok8 yJww+xvtBG8yi35A9lRCa3Btpoz/9Hs7k1r9+4PUcUL4xwZFzicdleeHuPJHWnxuBaFZ2I2cHFD 8rznOnNRfGGzmbhM5LJOq9mY0My3rAPvg7+crEXznWHCrdWDvnBIrDqxZ8s8jQvuhoe9TeY1wbE iM8MGyXsqQUYT7aov83eCJiHPVxO8RRJdNaWFZYg1reRDkdT+TsGaOcSXm3bcx5LKFly6QI7WfD LD3AZJXQQs+WWjoDT2QjPgD4BHKAvTMZu5xpu9FLk5clPY7wBdb5x1x1gA== X-Google-Smtp-Source: AGHT+IGcN7KmSzWUc3x2Q9hIKcCxmrhzor1ESo6ey42ZNpnLuX0uKU0+qCp3SXFy7hHj8nlBIEN6rA== X-Received: by 2002:a05:6a00:240c:b0:732:2170:b68b with SMTP id d2e1a72fcca58-734abee4a68mr22681643b3a.0.1741042393072; Mon, 03 Mar 2025 14:53:13 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-734a003eb4fsm9440601b3a.129.2025.03.03.14.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Mar 2025 14:53:12 -0800 (PST) From: Atish Patra Date: Mon, 03 Mar 2025 14:53:06 -0800 Subject: [PATCH v2 1/4] RISC-V: KVM: Disable the kernel perf counter during configure Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250303-kvm_pmu_improve-v2-1-41d177e45929@rivosinc.com> References: <20250303-kvm_pmu_improve-v2-0-41d177e45929@rivosinc.com> In-Reply-To: <20250303-kvm_pmu_improve-v2-0-41d177e45929@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 The perf event should be marked disabled during the creation as it is not ready to be scheduled until there is SBI PMU start call or config matching is called with auto start. Otherwise, event add/start gets called during perf_event_create_kernel_counter function. It will be enabled and scheduled to run via perf_event_enable during either the above mentioned scenario. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 2707a51b082c..78ac3216a54d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -666,6 +666,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba .type = etype, .size = sizeof(struct perf_event_attr), .pinned = true, + .disabled = true, /* * It should never reach here if the platform doesn't support the sscofpmf * extension as mode filtering won't work without it. From patchwork Mon Mar 3 22:53:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13999592 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE50023959A for ; Mon, 3 Mar 2025 22:53:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741042396; cv=none; b=oGVSOf6sQijvJN6Bn00CWXx99AVj9O9q8+dEIoXz6AssgY3nj+769+Pkwo0Ubt5LEFF1AxRUK63FdamI9QkUbAOoMxqAqNQikJCayRJdbrYd6UBLg9I1kaB1a21lRT0NUq/GY1wiuqD+z3a+uSm5bfsUZR2tTgKBtjXjBXUDKbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741042396; c=relaxed/simple; bh=gBJ6uGpDPU8VQvhfth2yUutlzUR6uu8KN/4t8mgGmWk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CtnEZ6yaqpdPSvel071eH7zvyb7qUvQIckGp3DEpvwRCFEiyk0FrAJUxfLXyaaCf8KeqVAGv/ZqX3Qye53G6G+jjWAdGeu2S4SqMFz3j+GcnOPXJ56zyVBEZFz/4d7Pm+Ns4HJG6cNu9vhVh/a+bQSLlU/ZFWnNGDlRPRKBcmYw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=rw2Ic0j3; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="rw2Ic0j3" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-223a7065ff8so44352905ad.0 for ; Mon, 03 Mar 2025 14:53:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741042394; x=1741647194; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=b5xoxucipI3r87CV5kbgeUb/z0QLUAJbC0b2XlScuLU=; b=rw2Ic0j3xtkPH5LOGEOzDrhI//tfDv7NUln4/ovKnCAWLlp2odyXKMBNCkL8tmQr1b BijZYi3maGEJae5FyLgl0p7zTT/VBS9tlibysY0nINZf1GjUlGQEyyEyI2VrffrghxUZ GofPyfjlVVQ4qC4i0R7VqLCPPX1Bs+k3MqU2aCLrZIjmvWkouO6OqlOzNVAz6wQHkwN1 Vqu6ZyAZscDwpOjgSrteRa7FMx5x0hWKPKXS8upLHgacv7qgCiD4HWMWtIEJ/yWBENSR g4gpcvrLIvL5ZRzP8QlyK1JnvIHPrvK9V2o/aws0n1uNK625KzRv+eUkKEJHyZudS2bK GOAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741042394; x=1741647194; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b5xoxucipI3r87CV5kbgeUb/z0QLUAJbC0b2XlScuLU=; b=ADfjPey3tRHF5HVfZ23Ssvm3XjJgxKtBYiqxUvjnHoaAK4exmcJfVsJJLmCouT0G+Z qwtFX/esnB13OlkplKas6ExLG8LqWlFf9I+HCtD/3uQHO1lmRhoU6/kCOz2OjBr45xgT sYK4V3MIfPZbwBztzAIT5PfEVmm2ltRwNV1fvfrt3SBYZ4aZKdTnEQZaeeZV+w3S/QMp FlqUo9icuHLjs/+G7VInIDaJmmyNVwUEuXvGMRcSVBi/VfKdjoGS7au+bX9ShsQtrX+E pp2vPsrREu8wJDCndXAYGmuPlTd7Jst9nAo63JK3UyX+D0+fNg3eWvka4Gn3bHu9axld w29w== X-Gm-Message-State: AOJu0Yw/hHf7mDwyv5Px56ivpdHLHm7JDxQVrUPyq1o3sH7zBJpCy/Xs lQVAJTDBVw56KXKwkE3J4AkUHbxryRTZI5NwLrendxC/XUFX97CBhJHOPkB2qfQ= X-Gm-Gg: ASbGncvd+GHJg0Zc0GS2KGWFaBkKosEMgoYPSKayYYRhkqlo7q2S4REe7J8ptHEIdRn PUUUGNrz+K1JWiYcOAu1YD1yIqxs4yv9Dl18Uq+nFZSVyQz839gypkcGpQU7MFBzVXha9w0jHbM FnuLQhYp5+0YWE7WK/+9KdtXzz94WIm1UYzgQMK6QK71LlhFCZNUiWKLWwvul5d+vpwKE4Miko8 ajkemjwUPXds3DeGOv7dvz9pTHbkp5uqMjVclKyUnTBdkk/61/01PWbDLh6gve+eXkT42kV/CfA hKPF8ns7qQiooArkyFBFk03ZzIOvWf/hYRtlxTe4JuqjB6uRIvdY73F1vA== X-Google-Smtp-Source: AGHT+IGy8hMH+W8RZy5SJOGyzi1MeiJvJku2zV+j7M0txVehkixRDHS/MmEvMDbU3gziq5b3wIbZEQ== X-Received: by 2002:a17:903:230c:b0:21f:78f:c178 with SMTP id d9443c01a7336-22368fa5425mr202955235ad.3.1741042394242; Mon, 03 Mar 2025 14:53:14 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-734a003eb4fsm9440601b3a.129.2025.03.03.14.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Mar 2025 14:53:13 -0800 (PST) From: Atish Patra Date: Mon, 03 Mar 2025 14:53:07 -0800 Subject: [PATCH v2 2/4] KVM: riscv: selftests: Do not start the counter in the overflow handler Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250303-kvm_pmu_improve-v2-2-41d177e45929@rivosinc.com> References: <20250303-kvm_pmu_improve-v2-0-41d177e45929@rivosinc.com> In-Reply-To: <20250303-kvm_pmu_improve-v2-0-41d177e45929@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 There is no need to start the counter in the overflow handler as we intend to trigger precise number of LCOFI interrupts through these tests. The overflow irq handler has already stopped the counter. As a result, the stop call from the test function may return already stopped error which is fine as well. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c index f45c0ecc902d..284bc80193bd 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -118,8 +118,8 @@ static void stop_counter(unsigned long counter, unsigned long stop_flags) ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, stop_flags, 0, 0, 0); - __GUEST_ASSERT(ret.error == 0, "Unable to stop counter %ld error %ld\n", - counter, ret.error); + __GUEST_ASSERT(ret.error == 0 || ret.error == SBI_ERR_ALREADY_STOPPED, + "Unable to stop counter %ld error %ld\n", counter, ret.error); } static void guest_illegal_exception_handler(struct ex_regs *regs) @@ -137,7 +137,6 @@ static void guest_irq_handler(struct ex_regs *regs) unsigned int irq_num = regs->cause & ~CAUSE_IRQ_FLAG; struct riscv_pmu_snapshot_data *snapshot_data = snapshot_gva; unsigned long overflown_mask; - unsigned long counter_val = 0; /* Validate that we are in the correct irq handler */ GUEST_ASSERT_EQ(irq_num, IRQ_PMU_OVF); @@ -151,10 +150,6 @@ static void guest_irq_handler(struct ex_regs *regs) GUEST_ASSERT(overflown_mask & 0x01); WRITE_ONCE(vcpu_shared_irq_count, vcpu_shared_irq_count+1); - - counter_val = READ_ONCE(snapshot_data->ctr_values[0]); - /* Now start the counter to mimick the real driver behavior */ - start_counter(counter_in_use, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_val); } static unsigned long get_counter_index(unsigned long cbase, unsigned long cmask, From patchwork Mon Mar 3 22:53:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13999593 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DE5F23F28D for ; Mon, 3 Mar 2025 22:53:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741042397; cv=none; b=d67Y6fzIN+a5w1celnh7CBu+BVMlwZdEEhbZSbV5lScjjtVlFV8un8u4XTjM+3MvYChMnU4aeQ/TwFq2XSwoTnFVwlBHD3cxubh2KtkOYhnzB5re4OnYAf+sM5hkbTEUrxzJT8aJUxNSG3emvRbIXUum4MCbEHlMSQfn0Cf+NwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741042397; c=relaxed/simple; bh=oMiBPDZwgZr5dhcoZQIs4/IJPi1MUwF4a7itoyTuCso=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NOfFOgVytHTDE2DJWEWMMDQajBTUja83X3nM7vSh5MBscqWfaYWrmk6ZBx1PKkNfzsDDKO/HBK9vdxZPVZfLyjVhf2klsB7NFVk1/kHlCL+ZVQEfB/uyH/jtqI+Ezm7VjvJFRahkc53tdrGCaO0374VUo2Oj6vyRF8F0XM9br0Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=CxnXxHYZ; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="CxnXxHYZ" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-22359001f1aso111368085ad.3 for ; Mon, 03 Mar 2025 14:53:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741042395; x=1741647195; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=SSJ9VliM2a+aTryqldG0CH+Q28sfdpKDs8cwc/DPQU0=; b=CxnXxHYZW+6+02UjXEd/W0U3wCrXSGBHe5FKWLIm7dbBruAZmKN6C9dcX/tu1NQY1q BprpyoGcQRYAEtF1KCEIJEt4EwqZ1Uyl06fgk03q1ZyLs4Jlyu4iwKwEwtlyjoHLFupM tr82bZmHNAJdXI2LQM+XN5S0pvMSJ9ALGN9YmyJr2nNjaC823i5J6eu3cWm4T6bNCy2q RVMEiEabtG4vcf/MjHC2zkscNo57KM0H47wL39B27hvQ2YJ2TUOfvx2SNXuNVT4W763J 2GsHMK4iZ04DL+69CXkaDHcGReLSyRKfeYGNplNSrSeG3u0GXR2vATY+w/GlDVFZ4I9Y BauQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741042395; x=1741647195; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SSJ9VliM2a+aTryqldG0CH+Q28sfdpKDs8cwc/DPQU0=; b=luSSMMbchsHHH98JfM/rwtHVXq3bjDsRSKxzyBmuYkH7uVc2GxDKpr8/j6GwTqHPVK YU5/DixepPiDog4PxiqTQijdnNnak4+tG99ws0ACbkmuHOMxYCbl6eAkX/8KeE1qAkcV m8q33otjyeWucHJWuC/RDF7TN8nZxD8dQBDoXliMMuoOxy+g/H+V464AHlz/09DsVI2O FzDjjtgctqpX3tg4ISFIYBCH4bn0RCECOltZifrkjExjPTf5f8tAixmLPtLP4k3CONnl OxkHrvt3k8frWbHhdQx6wJGktp52MAkeOVnnrHJV3pwyXQUB9/HLgyJzi4LImfmb2PVM b4iA== X-Gm-Message-State: AOJu0YzOQqzMl4GITRhtSDRL3TSFDpCJOhj8HqUYpeuvMdCvXSwMrwAm odBDtz/ryXvMwUzR68QARp0P8Cts7ie5s/G5mbst+U6zzbUoT19YlU3a5z2kfhA= X-Gm-Gg: ASbGnctns7a+ysJUBOPQ0flOJ9LpqvJ5JQFfK/8rFOfhNGbgbXeSz7g2d53jreP+e61 ogbu5Zs8HOti6sE3VQVi14X2WVz3u1N79sGqafXtUZTEndRkotvBblEx/oR35/b5KLisQq3rYVT S5aU38pYeMiHMeY9ZTIzb+EFKahdDcjmaJSMaa8X+uVATppl+7I9VWZF337+kZAVVIEss1pQ+oF LS12oi50NOmd/0eQ7MCEhauChy/3cV0Ypm3l4ZL/tvfZJIcd2LuJO2YCBkooojJk7iXOshMeXsN etzE1S1dfkIAlNB8NT1SkiZ+XCdpA5DAPy7oPxQkN+3bi9Sw8lVhVQUSNA== X-Google-Smtp-Source: AGHT+IFgJxk7LwSBEIbBrY7Dr1CLOJZk/TMcnbzG8visvcRF+/r9iXWzrvGMz6kqm+x+c1jOver7mQ== X-Received: by 2002:a05:6a00:244d:b0:736:5504:e8af with SMTP id d2e1a72fcca58-7365504e9edmr9350148b3a.24.1741042395376; Mon, 03 Mar 2025 14:53:15 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-734a003eb4fsm9440601b3a.129.2025.03.03.14.53.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Mar 2025 14:53:15 -0800 (PST) From: Atish Patra Date: Mon, 03 Mar 2025 14:53:08 -0800 Subject: [PATCH v2 3/4] KVM: riscv: selftests: Change command line option Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250303-kvm_pmu_improve-v2-3-41d177e45929@rivosinc.com> References: <20250303-kvm_pmu_improve-v2-0-41d177e45929@rivosinc.com> In-Reply-To: <20250303-kvm_pmu_improve-v2-0-41d177e45929@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 The PMU test commandline option takes an argument to disable a certain test. The initial assumption behind this was a common use case is just to run all the test most of the time. However, running a single test seems more useful instead. Especially, the overflow test has been helpful to validate PMU virtualizaiton interrupt changes. Switching the command line option to run a single test instead of disabling a single test also allows to provide additional test specific arguments to the test. The default without any options remains unchanged which continues to run all the tests. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 40 +++++++++++++++--------- 1 file changed, 26 insertions(+), 14 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c index 284bc80193bd..de66099235d9 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -39,7 +39,11 @@ static bool illegal_handler_invoked; #define SBI_PMU_TEST_SNAPSHOT BIT(2) #define SBI_PMU_TEST_OVERFLOW BIT(3) -static int disabled_tests; +struct test_args { + int disabled_tests; +}; + +static struct test_args targs; unsigned long pmu_csr_read_num(int csr_num) { @@ -604,7 +608,11 @@ static void test_vm_events_overflow(void *guest_code) vcpu_init_vector_tables(vcpu); /* Initialize guest timer frequency. */ timer_freq = vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency)); + + /* Export the shared variables to the guest */ sync_global_to_guest(vm, timer_freq); + sync_global_to_guest(vm, vcpu_shared_irq_count); + sync_global_to_guest(vm, targs); run_vcpu(vcpu); @@ -613,28 +621,30 @@ static void test_vm_events_overflow(void *guest_code) static void test_print_help(char *name) { - pr_info("Usage: %s [-h] [-d ]\n", name); - pr_info("\t-d: Test to disable. Available tests are 'basic', 'events', 'snapshot', 'overflow'\n"); + pr_info("Usage: %s [-h] [-t ]\n", name); + pr_info("\t-t: Test to run (default all). Available tests are 'basic', 'events', 'snapshot', 'overflow'\n"); pr_info("\t-h: print this help screen\n"); } static bool parse_args(int argc, char *argv[]) { int opt; - - while ((opt = getopt(argc, argv, "hd:")) != -1) { + int temp_disabled_tests = SBI_PMU_TEST_BASIC | SBI_PMU_TEST_EVENTS | SBI_PMU_TEST_SNAPSHOT | + SBI_PMU_TEST_OVERFLOW; + while ((opt = getopt(argc, argv, "ht:")) != -1) { switch (opt) { - case 'd': + case 't': if (!strncmp("basic", optarg, 5)) - disabled_tests |= SBI_PMU_TEST_BASIC; + temp_disabled_tests &= ~SBI_PMU_TEST_BASIC; else if (!strncmp("events", optarg, 6)) - disabled_tests |= SBI_PMU_TEST_EVENTS; + temp_disabled_tests &= ~SBI_PMU_TEST_EVENTS; else if (!strncmp("snapshot", optarg, 8)) - disabled_tests |= SBI_PMU_TEST_SNAPSHOT; + temp_disabled_tests &= ~SBI_PMU_TEST_SNAPSHOT; else if (!strncmp("overflow", optarg, 8)) - disabled_tests |= SBI_PMU_TEST_OVERFLOW; + temp_disabled_tests &= ~SBI_PMU_TEST_OVERFLOW; else goto done; + targs.disabled_tests = temp_disabled_tests; break; case 'h': default: @@ -650,25 +660,27 @@ static bool parse_args(int argc, char *argv[]) int main(int argc, char *argv[]) { + targs.disabled_tests = 0; + if (!parse_args(argc, argv)) exit(KSFT_SKIP); - if (!(disabled_tests & SBI_PMU_TEST_BASIC)) { + if (!(targs.disabled_tests & SBI_PMU_TEST_BASIC)) { test_vm_basic_test(test_pmu_basic_sanity); pr_info("SBI PMU basic test : PASS\n"); } - if (!(disabled_tests & SBI_PMU_TEST_EVENTS)) { + if (!(targs.disabled_tests & SBI_PMU_TEST_EVENTS)) { test_vm_events_test(test_pmu_events); pr_info("SBI PMU event verification test : PASS\n"); } - if (!(disabled_tests & SBI_PMU_TEST_SNAPSHOT)) { + if (!(targs.disabled_tests & SBI_PMU_TEST_SNAPSHOT)) { test_vm_events_snapshot_test(test_pmu_events_snaphost); pr_info("SBI PMU event verification with snapshot test : PASS\n"); } - if (!(disabled_tests & SBI_PMU_TEST_OVERFLOW)) { + if (!(targs.disabled_tests & SBI_PMU_TEST_OVERFLOW)) { test_vm_events_overflow(test_pmu_events_overflow); pr_info("SBI PMU event verification with overflow test : PASS\n"); } From patchwork Mon Mar 3 22:53:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13999594 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C65A23FC52 for ; Mon, 3 Mar 2025 22:53:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741042399; cv=none; b=PGtrMPh+cUQIKGqTonRUwB8ZSLL8rr7MAMpAb3lmxAMWf3lvBZKizAl7eY+cBemNSPHUlyvNmXGrrpFOHF+IiOTe43ZpO5tA9V4AmR4us2NPzP7mTwFeoCJQQbhcS19WzOEahZfXINW7nPyRuGpxRD3oWJokbN9DryJqGyZJBt4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741042399; c=relaxed/simple; bh=nT1SZDmhRpluE6T0UXqXL8ivt7r+ikBYyrkgQ9kcFWM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GpsWWENarWYXeuVqb5VC6b1YXNq7FBZUZ2jElXQnIFoc+afSdqWs+F3YR8Jsv2rcYEiIIXP5Txs1TfKMZl+euYLzw3bOX8YHPw9IWkeDMuGjSl0YSPjJi33/YJVmRm7uVGGhYdfYRvPOI+3/T4Xp/eS+APCpPtz1c7SY7zbInrI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=jifWr2nx; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="jifWr2nx" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-22337bc9ac3so94790685ad.1 for ; Mon, 03 Mar 2025 14:53:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741042396; x=1741647196; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZCtM/lSFNLHVQ6KX2EDg2QNHrviALMnTGfDgB4f3TXM=; b=jifWr2nx4e35qYZjqR6eXb8khK+zuhylyXa25mW3z0ZH4ij1JG0qWGVhxOdHF+Sgy9 wukzH02Bb5J1DpS8p0esZEhFF/Kh9//vKDoMhAO1MfgK2/DtIR9i/ThlSo5XDiwtDTG1 TsPpTZW9Y2+ZbjzJrLNHni7BhU+lxelqzeJD8kOO6uTCksLY8Iatmnvj+0bPUbrtvmmf yx9+JEMt4jOF7DJ2KLnZKbEeheVPsLMlvFYSdLb5yANVm2x1+ry2hEGgCtSJqUmzxMpc mbnZubhuU57YEdRdIIGVBLQ6d3SIi7Pt/k0Jpb/VR2YCLYtJ/ivNdeijVS8+qn8OWl6C vq1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741042396; x=1741647196; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZCtM/lSFNLHVQ6KX2EDg2QNHrviALMnTGfDgB4f3TXM=; b=RXVEtxskSD6eBYTAnaj9ug3lzO5RzG3kypQuseNQ4BN0ncnPLixBR/Y3bxXvdn/vKW XUZyRH70/Sy5gYurpT/EWrbWoyXgcGEuI4/rlfn6LOdXn/XHzai5OcaDYSKnvWnOiSxB ixrpCZgcc2COAk/H3mM5Fnb/mPiaX7DbAC52Y/eQQSvWzSjGjNGxUiiyn/Y6GeSH9O1G QSBZF+di3fR3YsrueeUYmmaxpt6l7bHKjiq47X7rT2EipRtruH3g2yv0g+ZaXCUlkiqW YX+gsIDWPYR3aspncfqGEK5qEge+AcYpGLTLdi85kQdsEQbA4vQWkoILyxmH6gt+16SM 2ZBg== X-Gm-Message-State: AOJu0Yx47QyjTQDTGb3N6UFPgPipljhcjFiSJZqkKRq67Pul5Lkbz+hw GzLOKGqO5if5tEqAaPa87eVjCxPy5PeKwy7Cll5VjQXxEdXC/vtHriREDfioOTc= X-Gm-Gg: ASbGncsIZyY0gfYJTkBPZ4csq/frbSMNySJ16Dweaq3Wk9rEnduvkboAGOYNAKIzV2J m4UO40h3wCHfB3Uk1/aWMfpvmNqK2CNey+WjjULTUBrSrRvvmcxSb3YhTHyztPzeCCiXZEqTLMs t1/Te1j3UrLvm+3xPWZ6iNVHBOu+8m3yd2uIoKh1aFivN3tNh30W8r8zs0TkfOaeHjDoORLjXtU JrauEmEV9Z5tjJc5YfnT+Z1dhAkHRoj0QIyjneW1wRznQXDm69myxu0NhwRIQesEqEYP6kxYYdo YvWAjt+opraEceAdtf4zMW67/u2xgDfsz8v1B31p4MER5tJpoFZFIh5Bdg== X-Google-Smtp-Source: AGHT+IGXirVkG7YmM+e3F/UoJqVCuA4YUPHtWRuh1VU5G5YFfQvPrt0/VrZAaOMzGSWX8Cr6YTAmAg== X-Received: by 2002:a05:6a00:92a1:b0:736:3ed1:e842 with SMTP id d2e1a72fcca58-7363ed1ec20mr10954047b3a.20.1741042396365; Mon, 03 Mar 2025 14:53:16 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-734a003eb4fsm9440601b3a.129.2025.03.03.14.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Mar 2025 14:53:16 -0800 (PST) From: Atish Patra Date: Mon, 03 Mar 2025 14:53:09 -0800 Subject: [PATCH v2 4/4] KVM: riscv: selftests: Allow number of interrupts to be configurable Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250303-kvm_pmu_improve-v2-4-41d177e45929@rivosinc.com> References: <20250303-kvm_pmu_improve-v2-0-41d177e45929@rivosinc.com> In-Reply-To: <20250303-kvm_pmu_improve-v2-0-41d177e45929@rivosinc.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 It is helpful to vary the number of the LCOFI interrupts generated by the overflow test. Allow additional argument for overflow test to accommodate that. It can be easily cross-validated with /proc/interrupts output in the host. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 38 +++++++++++++++++++----- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c index de66099235d9..03406de4989d 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -39,8 +39,10 @@ static bool illegal_handler_invoked; #define SBI_PMU_TEST_SNAPSHOT BIT(2) #define SBI_PMU_TEST_OVERFLOW BIT(3) +#define SBI_PMU_OVERFLOW_IRQNUM_DEFAULT 5 struct test_args { int disabled_tests; + int overflow_irqnum; }; static struct test_args targs; @@ -478,7 +480,7 @@ static void test_pmu_events_snaphost(void) static void test_pmu_events_overflow(void) { - int num_counters = 0; + int num_counters = 0, i = 0; /* Verify presence of SBI PMU and minimum requrired SBI version */ verify_sbi_requirement_assert(); @@ -495,11 +497,15 @@ static void test_pmu_events_overflow(void) * Qemu supports overflow for cycle/instruction. * This test may fail on any platform that do not support overflow for these two events. */ - test_pmu_event_overflow(SBI_PMU_HW_CPU_CYCLES); - GUEST_ASSERT_EQ(vcpu_shared_irq_count, 1); + for (i = 0; i < targs.overflow_irqnum; i++) + test_pmu_event_overflow(SBI_PMU_HW_CPU_CYCLES); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum); + + vcpu_shared_irq_count = 0; - test_pmu_event_overflow(SBI_PMU_HW_INSTRUCTIONS); - GUEST_ASSERT_EQ(vcpu_shared_irq_count, 2); + for (i = 0; i < targs.overflow_irqnum; i++) + test_pmu_event_overflow(SBI_PMU_HW_INSTRUCTIONS); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, targs.overflow_irqnum); GUEST_DONE(); } @@ -621,8 +627,11 @@ static void test_vm_events_overflow(void *guest_code) static void test_print_help(char *name) { - pr_info("Usage: %s [-h] [-t ]\n", name); + pr_info("Usage: %s [-h] [-t ] [-n ]\n", + name); pr_info("\t-t: Test to run (default all). Available tests are 'basic', 'events', 'snapshot', 'overflow'\n"); + pr_info("\t-n: Number of LCOFI interrupt to trigger for each event in overflow test (default: %d)\n", + SBI_PMU_OVERFLOW_IRQNUM_DEFAULT); pr_info("\t-h: print this help screen\n"); } @@ -631,7 +640,9 @@ static bool parse_args(int argc, char *argv[]) int opt; int temp_disabled_tests = SBI_PMU_TEST_BASIC | SBI_PMU_TEST_EVENTS | SBI_PMU_TEST_SNAPSHOT | SBI_PMU_TEST_OVERFLOW; - while ((opt = getopt(argc, argv, "ht:")) != -1) { + int overflow_interrupts = 0; + + while ((opt = getopt(argc, argv, "ht:n:")) != -1) { switch (opt) { case 't': if (!strncmp("basic", optarg, 5)) @@ -646,12 +657,24 @@ static bool parse_args(int argc, char *argv[]) goto done; targs.disabled_tests = temp_disabled_tests; break; + case 'n': + overflow_interrupts = atoi_positive("Number of LCOFI", optarg); + break; case 'h': default: goto done; } } + if (overflow_interrupts > 0) { + if (targs.disabled_tests & SBI_PMU_TEST_OVERFLOW) { + pr_info("-n option is only available for overflow test\n"); + goto done; + } else { + targs.overflow_irqnum = overflow_interrupts; + } + } + return true; done: test_print_help(argv[0]); @@ -661,6 +684,7 @@ static bool parse_args(int argc, char *argv[]) int main(int argc, char *argv[]) { targs.disabled_tests = 0; + targs.overflow_irqnum = SBI_PMU_OVERFLOW_IRQNUM_DEFAULT; if (!parse_args(argc, argv)) exit(KSFT_SKIP);