From patchwork Tue Mar 4 21:12:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 14001419 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82876260384 for ; Tue, 4 Mar 2025 21:12:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741122748; cv=none; b=kElzjMNB6o1pn0oglBDixsn9ljNA7MqqJCLX8/zHZOqLewvK9Mq2twyRQ5pAuu+E+PJtihjn1DqgN9DpRED9pJVeeo0t8BFYJ+dYHFFBhP/O0Z0/tEEWuc7SomPe0A+JnMeV/OildnSMWfPwENSmYp0YiS3npdFQKcQK2jwSYK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741122748; c=relaxed/simple; bh=y6qgGnd5ZMoajYRCODWj9m3PLCmcLug0Er/BJ6OhDDc=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=AWYvajeOlYLpyLnL+eurQsYGPsadHwVahwBS5ry0KlFj0tNBBhHG3pNrmVp4IfWge+px8WHi1mpI9i0RHTPefPC/ze+emLVpUYqyYZ7W2kC/7cJv3oGKaz0X5QDvV7WJueQkpqTrppZZc/BAhgZbTQgXlOVOUAM4nebp+WzJ8yU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=Xnzz1AF+; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Xnzz1AF+" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-22366bcf24bso85127385ad.1 for ; Tue, 04 Mar 2025 13:12:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1741122747; x=1741727547; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=CyBKYw9sqcQ2PVLUXrhMEac3+jgRASv0Gacs/HY5HgI=; b=Xnzz1AF+Hj71UebGAzl8WYh9ekdHZLOtVspucE2QUriwRbq3pQx486M7oGP9QFQry0 IBFcPRQ0Q4GbR8QO21aL0uL2pDefLb7N3zQenMw2BiPVRzo9foagG2byqZJQCz+VJk5Q woKrJt4ck+YoELRnCUeVBP549pjH+GzSsr4T/ir0f0WLA3auPR3fXbEaGrMmkJpfRDVR sWuTdAEajvejj7NqB8OJzhR534IDfrOtrOxVjfMx3zQ1hvTW336loGVyH6RJeS+vcywQ KX3O2K8A3vVQFdsb4aSnHPg178vnfBNf1JXDPb8aTb/p6cSZg9QjFqZd70WLZHVfa+Ox RQRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741122747; x=1741727547; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=CyBKYw9sqcQ2PVLUXrhMEac3+jgRASv0Gacs/HY5HgI=; b=OlB89jmeiTwmYdwWbYUccMfVm649ySNNfro4yKk8n6TnBxmE171fSDSsmebCnnWDNb ZXEMCItqP4avMFN/t2q0Og+O0bw7RkDN14dwzNgnQZakN8dMsHkInKOCRq/fY4mWSDLW FWxJFZljRVhIVJ7msIux5fDxgU+YuEEdL24/lZjCPssaCyuQWYWNFp9K87ell8nAU5UT rmXYdySfXz49XXZ8NUGmOheoxdGpAe8sKmE20LOXd5OFnOVuKCwCL2tm24ld8PoidxB3 IRf9gWiSpNSKakTfU3I6EAhL2r6XwWmIGLZLZ4AOI1XChUKDeZmgWY0JwUo9WfgDhrIn 6yrQ== X-Gm-Message-State: AOJu0YxGnqDBxUbpnqqNygJYXD9KGOmMY1FLtRcrcIfHa8CwoUHKuysG Fx0SSzAFqvC1naV8WtU4dtsTsGZcIMYAZbPGcH68KB8RMgktEfKNPSVmqyv2FXn71Wl1LJ+EnfZ Mgw== X-Google-Smtp-Source: AGHT+IGmSTx5c3/S+Y9KMi+JOF9wy1Pe2LphtMtr3kQ4xVFlvgN903PenIMduyCCWEbfrnfg5SOMz29D1rw= X-Received: from plbkh14.prod.google.com ([2002:a17:903:64e:b0:223:432c:56d4]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:ec90:b0:221:7343:80f5 with SMTP id d9443c01a7336-223f1d8430bmr8488655ad.53.1741122746766; Tue, 04 Mar 2025 13:12:26 -0800 (PST) Reply-To: Sean Christopherson Date: Tue, 4 Mar 2025 13:12:22 -0800 In-Reply-To: <20250304211223.124321-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250304211223.124321-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250304211223.124321-2-seanjc@google.com> Subject: [kvm-unit-tests PATCH 1/2] x86: apic: Move helpers for querying APIC state to library code From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Expose the helpers to query if an APIC is enabled, and in xAPIC vs. x2APIC mode, to library code so that the helpers can be used by all tests. No funtional change intended. Signed-off-by: Sean Christopherson --- lib/x86/apic.h | 21 +++++++++++++++++++++ x86/apic.c | 20 -------------------- 2 files changed, 21 insertions(+), 20 deletions(-) diff --git a/lib/x86/apic.h b/lib/x86/apic.h index 23c771ed..cac6eab1 100644 --- a/lib/x86/apic.h +++ b/lib/x86/apic.h @@ -5,6 +5,7 @@ #include #include "apic-defs.h" +#include "processor.h" #include "smp.h" extern u8 id_map[MAX_TEST_CPUS]; @@ -67,6 +68,26 @@ void apic_setup_timer(int vector, u32 mode); void apic_start_timer(u32 counter); void apic_stop_timer(void); +static inline bool is_apic_hw_enabled(void) +{ + return rdmsr(MSR_IA32_APICBASE) & APIC_EN; +} + +static inline bool is_apic_sw_enabled(void) +{ + return apic_read(APIC_SPIV) & APIC_SPIV_APIC_ENABLED; +} + +static inline bool is_x2apic_enabled(void) +{ + return (rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == (APIC_EN | APIC_EXTD); +} + +static inline bool is_xapic_enabled(void) +{ + return (rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == APIC_EN; +} + /* Converts byte-addressable APIC register offset to 4-byte offset. */ static inline u32 apic_reg_index(u32 reg) { diff --git a/x86/apic.c b/x86/apic.c index dd7e7834..b45fc9c1 100644 --- a/x86/apic.c +++ b/x86/apic.c @@ -10,26 +10,6 @@ #define MAX_TPR 0xf -static bool is_apic_hw_enabled(void) -{ - return rdmsr(MSR_IA32_APICBASE) & APIC_EN; -} - -static bool is_apic_sw_enabled(void) -{ - return apic_read(APIC_SPIV) & APIC_SPIV_APIC_ENABLED; -} - -static bool is_x2apic_enabled(void) -{ - return (rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == (APIC_EN | APIC_EXTD); -} - -static bool is_xapic_enabled(void) -{ - return (rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == APIC_EN; -} - static void test_lapic_existence(void) { u8 version; From patchwork Tue Mar 4 21:12:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 14001420 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EABE277017 for ; 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Tue, 04 Mar 2025 13:12:28 -0800 (PST) Reply-To: Sean Christopherson Date: Tue, 4 Mar 2025 13:12:23 -0800 In-Reply-To: <20250304211223.124321-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250304211223.124321-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250304211223.124321-3-seanjc@google.com> Subject: [kvm-unit-tests PATCH 2/2] x86: nSVM: Ensure APIC MMIO tests run with APIC in xAPIC mode From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Implement prepare/restore logic for the nSVM/nNPT APIC MMIO passthrough tests to ensure the CPU is actually running with xAPIC enabled. As is, the test is effectively validating KVM's KVM_X86_QUIRK_LAPIC_MMIO_HOLE, or if x2AVIC is support, CPU behavior. The latter (x2AVIC enabled) is especially problematic, as AMD CPUs appear to return '0' for xAPIC reads when x2AVIC is enabled. And because KVM disables/inhibits AVIC and x2AVIC when running L2, the divergence in behavior (KVM provies 0xffs, CPU provides 0s) results in test failures. Opportunistically make the hardcoded APIC base pointer (eww) an unsigned long literal. Note, svm_test.finished() is invoked *before* svm_test.succeeded(), i.e. restoring x2APIC (if it was enabled) must be done in the "check" code. Signed-off-by: Sean Christopherson --- x86/svm_npt.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/x86/svm_npt.c b/x86/svm_npt.c index b791f1ac..bd5e8f35 100644 --- a/x86/svm_npt.c +++ b/x86/svm_npt.c @@ -1,3 +1,4 @@ +#include "apic.h" #include "svm.h" #include "vm.h" #include "alloc_page.h" @@ -134,8 +135,27 @@ static bool npt_rw_pfwalk_check(struct svm_test *test) && (vmcb->control.exit_info_2 == read_cr3()); } +static bool was_x2apic; + +static void npt_apic_prepare(void) +{ + was_x2apic = is_x2apic_enabled(); + + if (was_x2apic) + reset_apic(); +} + +static void npt_apic_restore(void) +{ + if (was_x2apic) + enable_x2apic(); + + was_x2apic = false; +} + static void npt_l1mmio_prepare(struct svm_test *test) { + npt_apic_prepare(); } u32 nested_apic_version1; @@ -154,6 +174,9 @@ static bool npt_l1mmio_check(struct svm_test *test) volatile u32 *data = (volatile void *)(0xfee00030); u32 lvr = *data; + /* Restore APIC state *after* reading LVR. */ + npt_apic_restore(); + return nested_apic_version1 == lvr && nested_apic_version2 == lvr; } @@ -162,6 +185,8 @@ static void npt_rw_l1mmio_prepare(struct svm_test *test) u64 *pte; + npt_apic_prepare(); + pte = npt_get_pte(0xfee00080); *pte &= ~(1ULL << 1); @@ -180,6 +205,8 @@ static bool npt_rw_l1mmio_check(struct svm_test *test) *pte |= (1ULL << 1); + npt_apic_restore(); + return (vmcb->control.exit_code == SVM_EXIT_NPF) && (vmcb->control.exit_info_1 == 0x100000007ULL); }