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20 Mar 2019 09:22:58 +0800 IronPort-SDR: 06NhEYuUOnoKdtgC2UMzLpSwpYkwBgRf19sXIiyEXSZkc8q1oBKT+SVasMOhGiUUsE6MpvvPE2 UVl7ZWJRp90c32kird5E9NKTa56sGFxY+WYg713YjTIf2eKYpvfUrAxyTR9eVoBEAHGNo9qDGO ECasZbENfpNnXbNkcfkLpodNI3awIXhJd1PSH3dFV4f/Bq1iP/ERuLhbi+7rFEoEou9HbK/Gxm ikr7RrxkxGsY/igRXMGfqKBSCtaDS8jGju7Xw3MzO49QMvVr3wW6FVS6n+A7D/phcRh9+cBYcr /LdhRhXSJJBCEnzFOsl2kP6H Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 19 Mar 2019 18:00:35 -0700 IronPort-SDR: 74e+9wDs7inGi9149LY/w680g5jI4wF9t01OZPlDKox8ntToAjyg0lLwP+CgtlDwo/xd7ozIvB VDVf78wUsXnqAi5UgIGpIOo8OgA8A3g0qKsOr6sEEvwsUzQS1ud/cjXMQCS6UtUu7Jar5iwls0 AzNAIFh5Ao8RBdQizSxZXV9zEH7NXSADMKS3scQpdVD0gysWU+RKIVlH+41hsavh030ucrSvGB OF9zsOLcOrwKMPj1eX3StIpbQN5bM9EsTpfXhL6FqiUSoVh2uVcFscWXvM7mAbh2neuWJjYLa/ tXE= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 19 Mar 2019 18:22:58 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [RFT/RFC PATCH v2 1/4] dt-binding: cpu-topology: Move cpu-map to a common binding. Date: Tue, 19 Mar 2019 18:22:48 -0700 Message-Id: <20190320012251.2728-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190320012251.2728-1-atish.patra@wdc.com> References: <20190320012251.2728-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190320_012401_366157_D8DDD777 X-CRM114-Status: GOOD ( 17.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "Rafael J. Wysocki" , "Peter Zijlstra \(Intel\)" , Catalin Marinas , Palmer Dabbelt , Will Deacon , Atish Patra , linux-riscv@lists.infradead.org, Morten Rasmussen , Dmitriy Cherkasov , Anup Patel , Ingo Molnar , devicetree@vger.kernel.org, Albert Ou , Rob Herring , Paul Walmsley , Thomas Gleixner , Ard Biesheuvel , Greg Kroah-Hartman , Jeremy Linton , Otto Sabart , Sudeep Holla Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra Reviewed-by: Sudeep Holla --- .../topology.txt => cpu/cpu-topology.txt} | 82 +++++++++++++++---- 1 file changed, 66 insertions(+), 16 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (86%) diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt similarity index 86% rename from Documentation/devicetree/bindings/arm/topology.txt rename to Documentation/devicetree/bindings/cpu/cpu-topology.txt index 3b8febb4..069addcc 100644 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ b/Documentation/devicetree/bindings/cpu/cpu-topology.txt @@ -1,12 +1,12 @@ =========================================== -ARM topology binding description +CPU topology binding description =========================================== =========================================== 1 - Introduction =========================================== -In an ARM system, the hierarchy of CPUs is defined through three entities that +In a SMP system, the hierarchy of CPUs is defined through three entities that are used to describe the layout of physical CPUs in the system: - socket @@ -14,9 +14,6 @@ are used to describe the layout of physical CPUs in the system: - core - thread -The cpu nodes (bindings defined in [1]) represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - The bottom hierarchy level sits at core or thread level depending on whether symmetric multi-threading (SMT) is supported or not. @@ -25,33 +22,31 @@ threads existing in the system and map to the hierarchy level "thread" above. In systems where SMT is not supported "cpu" nodes represent all cores present in the system and map to the hierarchy level "core" above. -ARM topology bindings allow one to associate cpu nodes with hierarchical groups +CPU topology bindings allow one to associate cpu nodes with hierarchical groups corresponding to the system hierarchy; syntactically they are defined as device tree nodes. -The remainder of this document provides the topology bindings for ARM, based -on the Devicetree Specification, available from: +Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be +used for any other architecture as well. -https://www.devicetree.org/specifications/ +The cpu nodes, as per bindings defined in [4], represent the devices that +correspond to physical CPUs and are to be mapped to the hierarchy levels. -If not stated otherwise, whenever a reference to a cpu node phandle is made its -value must point to a cpu node compliant with the cpu node bindings as -documented in [1]. A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [1] is therefore considered invalid. +with bindings standardized in [4] is therefore considered invalid. =========================================== 2 - cpu-map node =========================================== -The ARM CPU topology is defined within the cpu-map node, which is a direct +The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct child of the cpus node and provides a container where the actual topology nodes are listed. - cpu-map node - Usage: Optional - On ARM SMP systems provide CPUs topology to the OS. - ARM uniprocessor systems do not require a topology + Usage: Optional - On SMP systems provide CPUs topology to the OS. + Uniprocessor systems do not require a topology description and therefore should not define a cpu-map node. @@ -494,8 +489,63 @@ cpus { }; }; +Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) + +{ + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540g", "sifive,fu500"; + model = "sifive,hifive-unleashed-a00"; + + ... + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU1>; + }; + core1 { + cpu = <&CPU2>; + }; + core2 { + cpu0 = <&CPU2>; + }; + core3 { + cpu0 = <&CPU3>; + }; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x1>; + } + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x2>; + } + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x3>; + } + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x4>; + } + } +}; =============================================================================== [1] ARM Linux kernel documentation Documentation/devicetree/bindings/arm/cpus.yaml [2] Devicetree NUMA binding description Documentation/devicetree/bindings/numa.txt +[3] RISC-V Linux kernel documentation + Documentation/devicetree/bindings/riscv/cpus.txt +[4] https://www.devicetree.org/specifications/ From patchwork Wed Mar 20 01:22:50 2019 Content-Type: text/plain; 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20 Mar 2019 09:22:59 +0800 IronPort-SDR: LTzCueQwGGCm4jXO1LQdxvnHzSWpkSo9VmSjqUSbvAz2OXDAPShrV6Ggu+zpUkkw3kemf0tYla YFfesSNLhE4kHQe3WrbUzNZbrJxNPzYH77nZHAcobbCc0+mFaq4iJDhoETx6VmBIyMZbyQANdI FGII5cvZc2lInl6FI31xcs2rWOSqzpJQmkTUlkHdql2QmTyazKzsbAQyXy/fIo2fB6WweoNgWg TQRZlY++N0O6v/9l/9rHDTJUwJtMIiACLdMT1sANWxfvhIeeRUVn4XcBVwRssYr85qAluYPWus 684Bu5zF8sZcDqUP2MUTxnD+ Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 19 Mar 2019 18:00:36 -0700 IronPort-SDR: Mm5ffHnMXLnxzR1GUSYNkrtLoY2+7RghWhnwm3rbWmIpX08gxIVYkBbEC5fVJZJ9NDkJDK9Xin FhOTRoW7BlLxIMunZBjIBu0QNT6ma2EmmYIAWko25FHzceSMVH1ysTi8VHGeFo2mgdzRuljAhH dOsnYATokewlBOXrwwg8owTuQL28346eGYMJ+BUgEbg/nTNxtoRwgt7vyulnZowRtjtbpyGTNi MvpVbRYG7k13jQD+ietuBwFSjIxgDdPJnghQFwFrRBYaoSfnU+/UN0v72cNq7CPhPB3ppX79iI ISc= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 19 Mar 2019 18:22:59 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [RFT/RFC PATCH v2 3/4] arm: Use common cpu_topology Date: Tue, 19 Mar 2019 18:22:50 -0700 Message-Id: <20190320012251.2728-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190320012251.2728-1-atish.patra@wdc.com> References: <20190320012251.2728-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190319_212404_467755_474834A3 X-CRM114-Status: GOOD ( 16.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "Rafael J. Wysocki" , "Peter Zijlstra \(Intel\)" , Catalin Marinas , Palmer Dabbelt , Will Deacon , Atish Patra , linux-riscv@lists.infradead.org, Morten Rasmussen , Dmitriy Cherkasov , Anup Patel , Ingo Molnar , devicetree@vger.kernel.org, Albert Ou , Rob Herring , Paul Walmsley , Thomas Gleixner , Ard Biesheuvel , Greg Kroah-Hartman , Jeremy Linton , Otto Sabart , Sudeep Holla Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, ARM32 and ARM64 uses different data structures to represent their cpu toplogies. Since, we are moving the ARM64 topology to common code to be used by other architectures, we can reuse that for ARM32 as well. Signed-off-by: Atish Patra --- arch/arm/include/asm/topology.h | 22 +--------------------- arch/arm/kernel/topology.c | 10 +++++----- include/linux/arch_topology.h | 10 +++++++++- 3 files changed, 15 insertions(+), 27 deletions(-) diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h index 2a786f54..52f99ec8 100644 --- a/arch/arm/include/asm/topology.h +++ b/arch/arm/include/asm/topology.h @@ -5,26 +5,6 @@ #ifdef CONFIG_ARM_CPU_TOPOLOGY #include - -struct cputopo_arm { - int thread_id; - int core_id; - int socket_id; - cpumask_t thread_sibling; - cpumask_t core_sibling; -}; - -extern struct cputopo_arm cpu_topology[NR_CPUS]; - -#define topology_physical_package_id(cpu) (cpu_topology[cpu].socket_id) -#define topology_core_id(cpu) (cpu_topology[cpu].core_id) -#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) -#define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) - -void init_cpu_topology(void); -void store_cpu_topology(unsigned int cpuid); -const struct cpumask *cpu_coregroup_mask(int cpu); - #include /* Replace task scheduler's default frequency-invariant accounting */ @@ -38,7 +18,7 @@ const struct cpumask *cpu_coregroup_mask(int cpu); #else -static inline void init_cpu_topology(void) { } +static inline void init_cpu_topology(void) {} static inline void store_cpu_topology(unsigned int cpuid) { } #endif diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 60e375ce..0ddb24c7 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -180,7 +180,7 @@ static inline void update_cpu_capacity(unsigned int cpuid) {} /* * cpu topology table */ -struct cputopo_arm cpu_topology[NR_CPUS]; +struct cpu_topology cpu_topology[NR_CPUS]; EXPORT_SYMBOL_GPL(cpu_topology); const struct cpumask *cpu_coregroup_mask(int cpu) @@ -197,9 +197,9 @@ const struct cpumask *cpu_corepower_mask(int cpu) return &cpu_topology[cpu].thread_sibling; } -static void update_siblings_masks(unsigned int cpuid) +void update_siblings_masks(unsigned int cpuid) { - struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid]; + struct cpu_topology *cpu_topo, *cpuid_topo = &cpu_topology[cpuid]; int cpu; /* update core and thread sibling masks */ @@ -230,7 +230,7 @@ static void update_siblings_masks(unsigned int cpuid) */ void store_cpu_topology(unsigned int cpuid) { - struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid]; + struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; unsigned int mpidr; /* If the cpu topology has been already set, just return */ @@ -302,7 +302,7 @@ void __init init_cpu_topology(void) /* init core mask and capacity */ for_each_possible_cpu(cpu) { - struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]); + struct cpu_topology *cpu_topo = &(cpu_topology[cpu]); cpu_topo->thread_id = -1; cpu_topo->core_id = -1; diff --git a/include/linux/arch_topology.h b/include/linux/arch_topology.h index d4e76e0a..7c850611 100644 --- a/include/linux/arch_topology.h +++ b/include/linux/arch_topology.h @@ -36,17 +36,25 @@ unsigned long topology_get_freq_scale(int cpu) struct cpu_topology { int thread_id; int core_id; +#ifdef CONFIG_ARM_CPU_TOPOLOGY + int socket_id; +#else int package_id; int llc_id; + cpumask_t llc_sibling; +#endif cpumask_t thread_sibling; cpumask_t core_sibling; - cpumask_t llc_sibling; }; #ifdef CONFIG_GENERIC_ARCH_TOPOLOGY extern struct cpu_topology cpu_topology[NR_CPUS]; +#ifdef CONFIG_ARM_CPU_TOPOLOGY +#define topology_physical_package_id(cpu) (cpu_topology[cpu].socket_id) +#else #define topology_physical_package_id(cpu) (cpu_topology[cpu].package_id) +#endif #define topology_core_id(cpu) (cpu_topology[cpu].core_id) #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) #define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) From patchwork Wed Mar 20 01:22:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 10860727 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9245F1390 for ; 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19 Mar 2019 18:23:00 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [RFT/RFC PATCH v2 4/4] RISC-V: Parse cpu topology during boot. Date: Tue, 19 Mar 2019 18:22:51 -0700 Message-Id: <20190320012251.2728-5-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190320012251.2728-1-atish.patra@wdc.com> References: <20190320012251.2728-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190319_212405_590937_F1977046 X-CRM114-Status: GOOD ( 13.57 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "Rafael J. Wysocki" , "Peter Zijlstra \(Intel\)" , Catalin Marinas , Palmer Dabbelt , Will Deacon , Atish Patra , linux-riscv@lists.infradead.org, Morten Rasmussen , Dmitriy Cherkasov , Anup Patel , Ingo Molnar , devicetree@vger.kernel.org, Albert Ou , Rob Herring , Paul Walmsley , Thomas Gleixner , Ard Biesheuvel , Greg Kroah-Hartman , Jeremy Linton , Otto Sabart , Sudeep Holla Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, there are no topology defined for RISC-V. Parse the cpu-map node from device tree and setup the cpu topology. CPU topology after applying the patch. $cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list 0-3 $cat /sys/devices/system/cpu/cpu3/topology/core_siblings_list 0-3 $cat /sys/devices/system/cpu/cpu3/topology/physical_package_id 0 $cat /sys/devices/system/cpu/cpu3/topology/core_id 3 Signed-off-by: Atish Patra --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index eb56c82d..ac87a0ec 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -47,6 +47,7 @@ config RISCV select PCI_MSI if PCI select RISCV_TIMER select GENERIC_IRQ_MULTI_HANDLER + select GENERIC_ARCH_TOPOLOGY if SMP select ARCH_HAS_PTE_SPECIAL select HAVE_EBPF_JIT if 64BIT diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index f41eb193..a8fe590c 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -43,6 +44,7 @@ static DECLARE_COMPLETION(cpu_running); void __init smp_prepare_boot_cpu(void) { + init_cpu_topology(); } void __init smp_prepare_cpus(unsigned int max_cpus) @@ -146,6 +148,7 @@ asmlinkage void __init smp_callin(void) trap_init(); notify_cpu_starting(smp_processor_id()); + update_siblings_masks(smp_processor_id()); set_cpu_online(smp_processor_id(), 1); /* * Remote TLB flushes are ignored while the CPU is offline, so emit