From patchwork Wed Mar 5 13:34:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 14002719 Received: from cantor.telenet-ops.be (cantor.telenet-ops.be [195.130.132.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DE9224888C for ; Wed, 5 Mar 2025 13:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741181675; cv=none; b=FURRhmjgZGVyfcbiH4ZY6m0ouECGEzUTrUxRkSQ/QWx5jPej5wiIvv/H4Xp8trRBCoe6Ui3BPJdkdXkYCBlbKfvMU9u+rnJCKhPxoqWOIQO27GqvmYhkRPJ1JMDaACDFZTECiUm4GRZwE3iorKxOTJylsU03hCLoOvlJPsj3Uog= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741181675; c=relaxed/simple; bh=imVH2Wne9UX6v58rw6Wb8RgWDaX4qSg52ZAvFuprd3E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HBShgbcS2sT6nmyNFMuarKZG5mb7vxkH5uALiAjUNfYsG5zvD8MkKdtZxgKFZ4OU6BZWI07xCNm0+K9sLb43uDwfx7wKiFpHkC/Dlo2Jcl5iXUDBMHBeuPta0/Zv0iz4GMApV6jhEW1IFTT+lyOEHAvV2+TzVxfKtfURonUwjFo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [IPv6:2a02:1800:120:4::f00:14]) by cantor.telenet-ops.be (Postfix) with ESMTPS id 4Z7D6t3xKHz4wwyC for ; Wed, 05 Mar 2025 14:34:30 +0100 (CET) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:fba:8cad:3d23:9db3]) by xavier.telenet-ops.be with cmsmtp id M1aJ2E00F0exi8p011aJll; Wed, 05 Mar 2025 14:34:22 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1tposn-0000000Cv3q-0yNA; Wed, 05 Mar 2025 14:34:18 +0100 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1tpot8-00000008woN-1Iwi; Wed, 05 Mar 2025 14:34:18 +0100 From: Geert Uytterhoeven To: Yoshihiro Shimoda , "James E . J . Bottomley" , "Martin K . Petersen" , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 1/7] dt-bindings: ufs: renesas,ufs: Add calibration data Date: Wed, 5 Mar 2025 14:34:09 +0100 Message-ID: <2f337169f8183d48b7d94ee13565fea804aade84.1741179611.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On R-Car S4-8 ES1.2, the E-FUSE block contains PLL and AFE tuning parameters for the Universal Flash Storage controller. Document the related NVMEM properties, and update the example. Signed-off-by: Geert Uytterhoeven Acked-by: Conor Dooley --- v3: - New. --- .../devicetree/bindings/ufs/renesas,ufs.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml b/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml index 1949a15e73d25849..ac11ac7d1d12f6c9 100644 --- a/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml @@ -33,6 +33,16 @@ properties: resets: maxItems: 1 + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + items: + - const: calibration + +dependencies: + nvmem-cells: [ nvmem-cell-names ] + required: - compatible - reg @@ -58,4 +68,6 @@ examples: freq-table-hz = <200000000 200000000>, <38400000 38400000>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 1514>; + nvmem-cells = <&ufs_tune>; + nvmem-cell-names = "calibration"; }; From patchwork Wed Mar 5 13:34:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 14002747 Received: from riemann.telenet-ops.be (riemann.telenet-ops.be [195.130.137.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BD4E24C09A for ; Wed, 5 Mar 2025 13:44:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.80 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741182249; cv=none; b=dNnQjgL6nAtZ/S6QXY6WI/ZfpZQF8dGlWsXgyNHNUDCCzugPQf2mqnoDdEJ4MFgFwqQyVrKnjILZm09ywagDiMRy2ud6wPgkTIAPFnRkEeYZbhyUIDu5K6I/SvsHmPY+1q1X7SGshIwtvb4i/OPU9hrXhQnxN89DLowxUcCu/vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741182249; c=relaxed/simple; bh=hXHXF7DwvOYAHVDZGTYLczYMzUgvVqnWnwr10MhpiVU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BAf2Ik6mU2WWFl+tcDagXytjv1m2YYU4Bu8lpcZ5Y1Zft8lWPhxAFBf9Oy4T8jE5w/TkvkFCNLlQeBLdEsFnFVmcclmMOXCf+TpBf0xwuxcS3zqq4iTNkwysQmZKpGj95UPb1rIiVjb4O/5zV6R2EgtoZwWfvtQQ7YImfElTCGY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.137.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from laurent.telenet-ops.be (laurent.telenet-ops.be [IPv6:2a02:1800:110:4::f00:19]) by riemann.telenet-ops.be (Postfix) with ESMTPS id 4Z7D6s32cBz4wx7j for ; Wed, 05 Mar 2025 14:34:29 +0100 (CET) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:fba:8cad:3d23:9db3]) by laurent.telenet-ops.be with cmsmtp id M1aJ2E0030exi8p011aJms; Wed, 05 Mar 2025 14:34:22 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1tposn-0000000Cv3s-15Gb; Wed, 05 Mar 2025 14:34:18 +0100 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1tpot8-00000008woQ-1Yr9; Wed, 05 Mar 2025 14:34:18 +0100 From: Geert Uytterhoeven To: Yoshihiro Shimoda , "James E . J . Bottomley" , "Martin K . Petersen" , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 2/7] scsi: ufs: renesas: Replace init data by init code Date: Wed, 5 Mar 2025 14:34:10 +0100 Message-ID: <3520e27ac7ff512de6508f630eee3c1689a7c73d.1741179611.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Yoshihiro Shimoda Since initialization of the UFS controller on R-Car S4-8 ES1.0 requires only static values, the driver uses initialization data stored in the const ufs_param[] array. However, other UFS controller variants (R-Car S4-8 ES1.2) require dynamic values, like those obtained from E-FUSE. Refactor the initialization code to prepare for this. This also reduces kernel size by almost 30 KiB. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Geert Uytterhoeven --- v3: - Keep MAX_INDEX check, as it is still useful, - Prefix data parameters of ufs_renesas_write_d0_d4() by "data_", for consistency, - Reword, - Document kernel size impact, v2: - Keep *_INDEX* enums, as they are still used, - Combine declaration and initialization of ufs_renesas_init_param, - Drop "_param" from ufs_renesas_*() helper function names. --- drivers/ufs/host/ufs-renesas.c | 511 ++++++++++++++++++--------------- 1 file changed, 286 insertions(+), 225 deletions(-) diff --git a/drivers/ufs/host/ufs-renesas.c b/drivers/ufs/host/ufs-renesas.c index 03cd82db751b013d..ac096d013287b187 100644 --- a/drivers/ufs/host/ufs-renesas.c +++ b/drivers/ufs/host/ufs-renesas.c @@ -39,98 +39,6 @@ enum ufs_renesas_init_param_mode { MODE_WRITE, }; -#define PARAM_RESTORE(_reg, _index) \ - { .mode = MODE_RESTORE, .reg = _reg, .index = _index } -#define PARAM_SET(_index, _set) \ - { .mode = MODE_SET, .index = _index, .u.set = _set } -#define PARAM_SAVE(_reg, _mask, _index) \ - { .mode = MODE_SAVE, .reg = _reg, .mask = (u32)(_mask), \ - .index = _index } -#define PARAM_POLL(_reg, _expected, _mask) \ - { .mode = MODE_POLL, .reg = _reg, .u.expected = _expected, \ - .mask = (u32)(_mask) } -#define PARAM_WAIT(_delay_us) \ - { .mode = MODE_WAIT, .u.delay_us = _delay_us } - -#define PARAM_WRITE(_reg, _val) \ - { .mode = MODE_WRITE, .reg = _reg, .u.val = _val } - -#define PARAM_WRITE_D0_D4(_d0, _d4) \ - PARAM_WRITE(0xd0, _d0), PARAM_WRITE(0xd4, _d4) - -#define PARAM_WRITE_800_80C_POLL(_addr, _data_800) \ - PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \ - PARAM_WRITE_D0_D4(0x00000800, ((_data_800) << 16) | BIT(8) | (_addr)), \ - PARAM_WRITE(0xd0, 0x0000080c), \ - PARAM_POLL(0xd4, BIT(8), BIT(8)) - -#define PARAM_RESTORE_800_80C_POLL(_index) \ - PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \ - PARAM_WRITE(0xd0, 0x00000800), \ - PARAM_RESTORE(0xd4, _index), \ - PARAM_WRITE(0xd0, 0x0000080c), \ - PARAM_POLL(0xd4, BIT(8), BIT(8)) - -#define PARAM_WRITE_804_80C_POLL(_addr, _data_804) \ - PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \ - PARAM_WRITE_D0_D4(0x00000804, ((_data_804) << 16) | BIT(8) | (_addr)), \ - PARAM_WRITE(0xd0, 0x0000080c), \ - PARAM_POLL(0xd4, BIT(8), BIT(8)) - -#define PARAM_WRITE_828_82C_POLL(_data_828) \ - PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000), \ - PARAM_WRITE_D0_D4(0x00000828, _data_828), \ - PARAM_WRITE(0xd0, 0x0000082c), \ - PARAM_POLL(0xd4, _data_828, _data_828) - -#define PARAM_WRITE_PHY(_addr16, _data16) \ - PARAM_WRITE(0xf0, 1), \ - PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x18, (_data16) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x19, ((_data16) >> 8) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE(0xf0, 0) - -#define PARAM_SET_PHY(_addr16, _data16) \ - PARAM_WRITE(0xf0, 1), \ - PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE_804_80C_POLL(0x1a, 0), \ - PARAM_WRITE(0xd0, 0x00000808), \ - PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_LO), \ - PARAM_WRITE_804_80C_POLL(0x1b, 0), \ - PARAM_WRITE(0xd0, 0x00000808), \ - PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_HI), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE(0xf0, 0), \ - PARAM_WRITE(0xf0, 1), \ - PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \ - PARAM_SET(SET_PHY_INDEX_LO, ((_data16 & 0xff) << 16) | BIT(8) | 0x18), \ - PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_LO), \ - PARAM_SET(SET_PHY_INDEX_HI, (((_data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19), \ - PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_HI), \ - PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE(0xf0, 0) - -#define PARAM_INDIRECT_WRITE(_gpio, _addr, _data_800) \ - PARAM_WRITE(0xf0, _gpio), \ - PARAM_WRITE_800_80C_POLL(_addr, _data_800), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE(0xf0, 0) - -#define PARAM_INDIRECT_POLL(_gpio, _addr, _expected, _mask) \ - PARAM_WRITE(0xf0, _gpio), \ - PARAM_WRITE_800_80C_POLL(_addr, 0), \ - PARAM_WRITE(0xd0, 0x00000808), \ - PARAM_POLL(0xd4, _expected, _mask), \ - PARAM_WRITE(0xf0, 0) - struct ufs_renesas_init_param { enum ufs_renesas_init_param_mode mode; u32 reg; @@ -144,135 +52,6 @@ struct ufs_renesas_init_param { u32 index; }; -/* This setting is for SERIES B */ -static const struct ufs_renesas_init_param ufs_param[] = { - PARAM_WRITE(0xc0, 0x49425308), - PARAM_WRITE_D0_D4(0x00000104, 0x00000002), - PARAM_WAIT(1), - PARAM_WRITE_D0_D4(0x00000828, 0x00000200), - PARAM_WAIT(1), - PARAM_WRITE_D0_D4(0x00000828, 0x00000000), - PARAM_WRITE_D0_D4(0x00000104, 0x00000001), - PARAM_WRITE_D0_D4(0x00000940, 0x00000001), - PARAM_WAIT(1), - PARAM_WRITE_D0_D4(0x00000940, 0x00000000), - - PARAM_WRITE(0xc0, 0x49425308), - PARAM_WRITE(0xc0, 0x41584901), - - PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), - PARAM_WRITE_D0_D4(0x00000804, 0x00000000), - PARAM_WRITE(0xd0, 0x0000080c), - PARAM_POLL(0xd4, BIT(8), BIT(8)), - - PARAM_WRITE(REG_CONTROLLER_ENABLE, 0x00000001), - - PARAM_WRITE(0xd0, 0x00000804), - PARAM_POLL(0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)), - - PARAM_WRITE(0xd0, 0x00000d00), - PARAM_SAVE(0xd4, 0x0000ffff, TIMER_INDEX), - PARAM_WRITE(0xd4, 0x00000000), - PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000), - PARAM_WRITE_D0_D4(0x00000828, 0x08000000), - PARAM_WRITE(0xd0, 0x0000082c), - PARAM_POLL(0xd4, BIT(27), BIT(27)), - PARAM_WRITE(0xd0, 0x00000d2c), - PARAM_POLL(0xd4, BIT(0), BIT(0)), - - /* phy setup */ - PARAM_INDIRECT_WRITE(1, 0x01, 0x001f), - PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x5e, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x0d, 0x0003), - PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007), - PARAM_INDIRECT_WRITE(7, 0x5f, 0x0003), - PARAM_INDIRECT_WRITE(7, 0x60, 0x0003), - PARAM_INDIRECT_WRITE(7, 0x5b, 0x00a6), - PARAM_INDIRECT_WRITE(7, 0x5c, 0x0003), - - PARAM_INDIRECT_POLL(7, 0x3c, 0, BIT(7)), - PARAM_INDIRECT_POLL(7, 0x4c, 0, BIT(4)), - - PARAM_INDIRECT_WRITE(1, 0x32, 0x0080), - PARAM_INDIRECT_WRITE(1, 0x1f, 0x0001), - PARAM_INDIRECT_WRITE(0, 0x2c, 0x0001), - PARAM_INDIRECT_WRITE(0, 0x32, 0x0087), - - PARAM_INDIRECT_WRITE(1, 0x4d, 0x0061), - PARAM_INDIRECT_WRITE(4, 0x9b, 0x0009), - PARAM_INDIRECT_WRITE(4, 0xa6, 0x0005), - PARAM_INDIRECT_WRITE(4, 0xa5, 0x0058), - PARAM_INDIRECT_WRITE(1, 0x39, 0x0027), - PARAM_INDIRECT_WRITE(1, 0x47, 0x004c), - - PARAM_INDIRECT_WRITE(7, 0x0d, 0x0002), - PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007), - - PARAM_WRITE_PHY(0x0028, 0x0061), - PARAM_WRITE_PHY(0x4014, 0x0061), - PARAM_SET_PHY(0x401c, BIT(2)), - PARAM_WRITE_PHY(0x4000, 0x0000), - PARAM_WRITE_PHY(0x4001, 0x0000), - - PARAM_WRITE_PHY(0x10ae, 0x0001), - PARAM_WRITE_PHY(0x10ad, 0x0000), - PARAM_WRITE_PHY(0x10af, 0x0001), - PARAM_WRITE_PHY(0x10b6, 0x0001), - PARAM_WRITE_PHY(0x10ae, 0x0000), - - PARAM_WRITE_PHY(0x10ae, 0x0001), - PARAM_WRITE_PHY(0x10ad, 0x0000), - PARAM_WRITE_PHY(0x10af, 0x0002), - PARAM_WRITE_PHY(0x10b6, 0x0001), - PARAM_WRITE_PHY(0x10ae, 0x0000), - - PARAM_WRITE_PHY(0x10ae, 0x0001), - PARAM_WRITE_PHY(0x10ad, 0x0080), - PARAM_WRITE_PHY(0x10af, 0x0000), - PARAM_WRITE_PHY(0x10b6, 0x0001), - PARAM_WRITE_PHY(0x10ae, 0x0000), - - PARAM_WRITE_PHY(0x10ae, 0x0001), - PARAM_WRITE_PHY(0x10ad, 0x0080), - PARAM_WRITE_PHY(0x10af, 0x001a), - PARAM_WRITE_PHY(0x10b6, 0x0001), - PARAM_WRITE_PHY(0x10ae, 0x0000), - - PARAM_INDIRECT_WRITE(7, 0x70, 0x0016), - PARAM_INDIRECT_WRITE(7, 0x71, 0x0016), - PARAM_INDIRECT_WRITE(7, 0x72, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x73, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x74, 0x0000), - PARAM_INDIRECT_WRITE(7, 0x75, 0x0000), - PARAM_INDIRECT_WRITE(7, 0x76, 0x0010), - PARAM_INDIRECT_WRITE(7, 0x77, 0x0010), - PARAM_INDIRECT_WRITE(7, 0x78, 0x00ff), - PARAM_INDIRECT_WRITE(7, 0x79, 0x0000), - - PARAM_INDIRECT_WRITE(7, 0x19, 0x0007), - - PARAM_INDIRECT_WRITE(7, 0x1a, 0x0007), - - PARAM_INDIRECT_WRITE(7, 0x24, 0x000c), - - PARAM_INDIRECT_WRITE(7, 0x25, 0x000c), - - PARAM_INDIRECT_WRITE(7, 0x62, 0x0000), - PARAM_INDIRECT_WRITE(7, 0x63, 0x0000), - PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017), - PARAM_INDIRECT_WRITE(7, 0x5d, 0x0004), - PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017), - PARAM_INDIRECT_POLL(7, 0x55, 0, BIT(6)), - PARAM_INDIRECT_POLL(7, 0x41, 0, BIT(7)), - /* end of phy setup */ - - PARAM_WRITE(0xf0, 0), - PARAM_WRITE(0xd0, 0x00000d00), - PARAM_RESTORE(0xd4, TIMER_INDEX), -}; - static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba) { ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + "); @@ -320,13 +99,295 @@ static void ufs_renesas_reg_control(struct ufs_hba *hba, } } +static void ufs_renesas_poll(struct ufs_hba *hba, u32 reg, u32 expected, u32 mask) +{ + struct ufs_renesas_init_param param = { + .mode = MODE_POLL, + .reg = reg, + .u.expected = expected, + .mask = mask, + }; + + ufs_renesas_reg_control(hba, ¶m); +} + +static void ufs_renesas_restore(struct ufs_hba *hba, u32 reg, u32 index) +{ + struct ufs_renesas_init_param param = { + .mode = MODE_RESTORE, + .reg = reg, + .index = index, + }; + + ufs_renesas_reg_control(hba, ¶m); +} + +static void ufs_renesas_save(struct ufs_hba *hba, u32 reg, u32 mask, u32 index) +{ + struct ufs_renesas_init_param param = { + .mode = MODE_SAVE, + .reg = reg, + .mask = mask, + .index = index, + }; + + ufs_renesas_reg_control(hba, ¶m); +} + +static void ufs_renesas_set(struct ufs_hba *hba, u32 index, u32 set) +{ + struct ufs_renesas_init_param param = { + .mode = MODE_SAVE, + .index = index, + .u.set = set, + }; + + ufs_renesas_reg_control(hba, ¶m); +} + +static void ufs_renesas_wait(struct ufs_hba *hba, u32 delay_us) +{ + struct ufs_renesas_init_param param = { + .mode = MODE_WAIT, + .u.delay_us = delay_us, + }; + + ufs_renesas_reg_control(hba, ¶m); +} + +static void ufs_renesas_write(struct ufs_hba *hba, u32 reg, u32 value) +{ + struct ufs_renesas_init_param param = { + .mode = MODE_WRITE, + .reg = reg, + .u.val = value, + }; + + ufs_renesas_reg_control(hba, ¶m); +} + +static void ufs_renesas_write_d0_d4(struct ufs_hba *hba, u32 data_d0, u32 data_d4) +{ + ufs_renesas_write(hba, 0xd0, data_d0); + ufs_renesas_write(hba, 0xd4, data_d4); +} + +static void ufs_renesas_write_800_80c_poll(struct ufs_hba *hba, u32 addr, + u32 data_800) +{ + ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); + ufs_renesas_write_d0_d4(hba, 0x00000800, (data_800 << 16) | BIT(8) | addr); + ufs_renesas_write(hba, 0xd0, 0x0000080c); + ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); +} + +static void ufs_renesas_restore_800_80c_poll(struct ufs_hba *hba, u32 index) +{ + ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); + ufs_renesas_write(hba, 0xd0, 0x00000800); + ufs_renesas_restore(hba, 0xd4, index); + ufs_renesas_write(hba, 0xd0, 0x0000080c); + ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); +} + +static void ufs_renesas_write_804_80c_poll(struct ufs_hba *hba, u32 addr, u32 data_804) +{ + ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); + ufs_renesas_write_d0_d4(hba, 0x00000804, (data_804 << 16) | BIT(8) | addr); + ufs_renesas_write(hba, 0xd0, 0x0000080c); + ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); +} + +static void ufs_renesas_write_828_82c_poll(struct ufs_hba *hba, u32 data_828) +{ + ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000); + ufs_renesas_write_d0_d4(hba, 0x00000828, data_828); + ufs_renesas_write(hba, 0xd0, 0x0000082c); + ufs_renesas_poll(hba, 0xd4, data_828, data_828); +} + +static void ufs_renesas_write_phy(struct ufs_hba *hba, u32 addr16, u32 data16) +{ + ufs_renesas_write(hba, 0xf0, 1); + ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x18, data16 & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x19, (data16 >> 8) & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01); + ufs_renesas_write_828_82c_poll(hba, 0x0f000000); + ufs_renesas_write(hba, 0xf0, 0); +} + +static void ufs_renesas_set_phy(struct ufs_hba *hba, u32 addr16, u32 data16) +{ + ufs_renesas_write(hba, 0xf0, 1); + ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01); + ufs_renesas_write_828_82c_poll(hba, 0x0f000000); + ufs_renesas_write_804_80c_poll(hba, 0x1a, 0); + ufs_renesas_write(hba, 0xd0, 0x00000808); + ufs_renesas_save(hba, 0xd4, 0xff, SET_PHY_INDEX_LO); + ufs_renesas_write_804_80c_poll(hba, 0x1b, 0); + ufs_renesas_write(hba, 0xd0, 0x00000808); + ufs_renesas_save(hba, 0xd4, 0xff, SET_PHY_INDEX_HI); + ufs_renesas_write_828_82c_poll(hba, 0x0f000000); + ufs_renesas_write(hba, 0xf0, 0); + ufs_renesas_write(hba, 0xf0, 1); + ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff); + ufs_renesas_set(hba, SET_PHY_INDEX_LO, ((data16 & 0xff) << 16) | BIT(8) | 0x18); + ufs_renesas_restore_800_80c_poll(hba, SET_PHY_INDEX_LO); + ufs_renesas_set(hba, SET_PHY_INDEX_HI, (((data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19); + ufs_renesas_restore_800_80c_poll(hba, SET_PHY_INDEX_HI); + ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01); + ufs_renesas_write_828_82c_poll(hba, 0x0f000000); + ufs_renesas_write(hba, 0xf0, 0); +} + +static void ufs_renesas_indirect_write(struct ufs_hba *hba, u32 gpio, u32 addr, + u32 data_800) +{ + ufs_renesas_write(hba, 0xf0, gpio); + ufs_renesas_write_800_80c_poll(hba, addr, data_800); + ufs_renesas_write_828_82c_poll(hba, 0x0f000000); + ufs_renesas_write(hba, 0xf0, 0); +} + +static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr, + u32 expected, u32 mask) +{ + ufs_renesas_write(hba, 0xf0, gpio); + ufs_renesas_write_800_80c_poll(hba, addr, 0); + ufs_renesas_write(hba, 0xd0, 0x00000808); + ufs_renesas_poll(hba, 0xd4, expected, mask); + ufs_renesas_write(hba, 0xf0, 0); +} + static void ufs_renesas_pre_init(struct ufs_hba *hba) { - const struct ufs_renesas_init_param *p = ufs_param; - unsigned int i; + /* This setting is for SERIES B */ + ufs_renesas_write(hba, 0xc0, 0x49425308); + ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002); + ufs_renesas_wait(hba, 1); + ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000200); + ufs_renesas_wait(hba, 1); + ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000000); + ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000001); + ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000001); + ufs_renesas_wait(hba, 1); + ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000000); + + ufs_renesas_write(hba, 0xc0, 0x49425308); + ufs_renesas_write(hba, 0xc0, 0x41584901); + + ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); + ufs_renesas_write_d0_d4(hba, 0x00000804, 0x00000000); + ufs_renesas_write(hba, 0xd0, 0x0000080c); + ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); + + ufs_renesas_write(hba, REG_CONTROLLER_ENABLE, 0x00000001); + + ufs_renesas_write(hba, 0xd0, 0x00000804); + ufs_renesas_poll(hba, 0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)); + + ufs_renesas_write(hba, 0xd0, 0x00000d00); + ufs_renesas_save(hba, 0xd4, 0x0000ffff, TIMER_INDEX); + ufs_renesas_write(hba, 0xd4, 0x00000000); + ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000); + ufs_renesas_write_d0_d4(hba, 0x00000828, 0x08000000); + ufs_renesas_write(hba, 0xd0, 0x0000082c); + ufs_renesas_poll(hba, 0xd4, BIT(27), BIT(27)); + ufs_renesas_write(hba, 0xd0, 0x00000d2c); + ufs_renesas_poll(hba, 0xd4, BIT(0), BIT(0)); + + /* phy setup */ + ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0003); + ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007); + ufs_renesas_indirect_write(hba, 7, 0x5f, 0x0003); + ufs_renesas_indirect_write(hba, 7, 0x60, 0x0003); + ufs_renesas_indirect_write(hba, 7, 0x5b, 0x00a6); + ufs_renesas_indirect_write(hba, 7, 0x5c, 0x0003); + + ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7)); + ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4)); + + ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080); + ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001); + ufs_renesas_indirect_write(hba, 0, 0x2c, 0x0001); + ufs_renesas_indirect_write(hba, 0, 0x32, 0x0087); + + ufs_renesas_indirect_write(hba, 1, 0x4d, 0x0061); + ufs_renesas_indirect_write(hba, 4, 0x9b, 0x0009); + ufs_renesas_indirect_write(hba, 4, 0xa6, 0x0005); + ufs_renesas_indirect_write(hba, 4, 0xa5, 0x0058); + ufs_renesas_indirect_write(hba, 1, 0x39, 0x0027); + ufs_renesas_indirect_write(hba, 1, 0x47, 0x004c); + + ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002); + ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007); + + ufs_renesas_write_phy(hba, 0x0028, 0x0061); + ufs_renesas_write_phy(hba, 0x4014, 0x0061); + ufs_renesas_set_phy(hba, 0x401c, BIT(2)); + ufs_renesas_write_phy(hba, 0x4000, 0x0000); + ufs_renesas_write_phy(hba, 0x4001, 0x0000); + + ufs_renesas_write_phy(hba, 0x10ae, 0x0001); + ufs_renesas_write_phy(hba, 0x10ad, 0x0000); + ufs_renesas_write_phy(hba, 0x10af, 0x0001); + ufs_renesas_write_phy(hba, 0x10b6, 0x0001); + ufs_renesas_write_phy(hba, 0x10ae, 0x0000); + + ufs_renesas_write_phy(hba, 0x10ae, 0x0001); + ufs_renesas_write_phy(hba, 0x10ad, 0x0000); + ufs_renesas_write_phy(hba, 0x10af, 0x0002); + ufs_renesas_write_phy(hba, 0x10b6, 0x0001); + ufs_renesas_write_phy(hba, 0x10ae, 0x0000); + + ufs_renesas_write_phy(hba, 0x10ae, 0x0001); + ufs_renesas_write_phy(hba, 0x10ad, 0x0080); + ufs_renesas_write_phy(hba, 0x10af, 0x0000); + ufs_renesas_write_phy(hba, 0x10b6, 0x0001); + ufs_renesas_write_phy(hba, 0x10ae, 0x0000); + + ufs_renesas_write_phy(hba, 0x10ae, 0x0001); + ufs_renesas_write_phy(hba, 0x10ad, 0x0080); + ufs_renesas_write_phy(hba, 0x10af, 0x001a); + ufs_renesas_write_phy(hba, 0x10b6, 0x0001); + ufs_renesas_write_phy(hba, 0x10ae, 0x0000); + + ufs_renesas_indirect_write(hba, 7, 0x70, 0x0016); + ufs_renesas_indirect_write(hba, 7, 0x71, 0x0016); + ufs_renesas_indirect_write(hba, 7, 0x72, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x73, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x74, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x75, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x76, 0x0010); + ufs_renesas_indirect_write(hba, 7, 0x77, 0x0010); + ufs_renesas_indirect_write(hba, 7, 0x78, 0x00ff); + ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000); + + ufs_renesas_indirect_write(hba, 7, 0x19, 0x0007); + ufs_renesas_indirect_write(hba, 7, 0x1a, 0x0007); + ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c); + ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c); + ufs_renesas_indirect_write(hba, 7, 0x62, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x63, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017); + ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6)); + ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7)); + /* end of phy setup */ - for (i = 0; i < ARRAY_SIZE(ufs_param); i++) - ufs_renesas_reg_control(hba, &p[i]); + ufs_renesas_write(hba, 0xf0, 0); + ufs_renesas_write(hba, 0xd0, 0x00000d00); + ufs_renesas_restore(hba, 0xd4, TIMER_INDEX); } static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba, From patchwork Wed Mar 5 13:34:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 14002716 Received: from michel.telenet-ops.be (michel.telenet-ops.be [195.130.137.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77086245038 for ; Wed, 5 Mar 2025 13:34:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.88 ARC-Seal: i=1; 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spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:fba:8cad:3d23:9db3]) by michel.telenet-ops.be with cmsmtp id M1aJ2E0070exi8p061aJJC; Wed, 05 Mar 2025 14:34:22 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1tposn-0000000Cv3w-1CoI; Wed, 05 Mar 2025 14:34:18 +0100 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1tpot8-00000008woV-1gwa; Wed, 05 Mar 2025 14:34:18 +0100 From: Geert Uytterhoeven To: Yoshihiro Shimoda , "James E . J . Bottomley" , "Martin K . Petersen" , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 3/7] scsi: ufs: renesas: Add register read to remove save/set/restore Date: Wed, 5 Mar 2025 14:34:11 +0100 Message-ID: <9fa240a9dc0308d6675138f8434eccb77f051650.1741179611.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Yoshihiro Shimoda Add support for returning read register values from ufs_renesas_reg_control(), so ufs_renesas_set_phy() can use the existing ufs_renesas_write_phy() helper. Remove the now unused code to save to, set, and restore from a static array inside ufs_renesas_reg_control(). Signed-off-by: Yoshihiro Shimoda Signed-off-by: Geert Uytterhoeven --- v3: - Reword, v2: - Remove *_INDEX* enums only in this patch, - Move MODE_READ handling after MODE_POLL handling, - Move ufs_renesas_read() after ufs_renesas_poll(), --- drivers/ufs/host/ufs-renesas.c | 99 ++++++++-------------------------- 1 file changed, 23 insertions(+), 76 deletions(-) diff --git a/drivers/ufs/host/ufs-renesas.c b/drivers/ufs/host/ufs-renesas.c index ac096d013287b187..100186a2e1807445 100644 --- a/drivers/ufs/host/ufs-renesas.c +++ b/drivers/ufs/host/ufs-renesas.c @@ -23,18 +23,9 @@ struct ufs_renesas_priv { bool initialized; /* The hardware needs initialization once */ }; -enum { - SET_PHY_INDEX_LO = 0, - SET_PHY_INDEX_HI, - TIMER_INDEX, - MAX_INDEX -}; - enum ufs_renesas_init_param_mode { - MODE_RESTORE, - MODE_SET, - MODE_SAVE, MODE_POLL, + MODE_READ, MODE_WAIT, MODE_WRITE, }; @@ -45,7 +36,6 @@ struct ufs_renesas_init_param { union { u32 expected; u32 delay_us; - u32 set; u32 val; } u; u32 mask; @@ -57,25 +47,13 @@ static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba) ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + "); } -static void ufs_renesas_reg_control(struct ufs_hba *hba, - const struct ufs_renesas_init_param *p) +static u32 ufs_renesas_reg_control(struct ufs_hba *hba, + const struct ufs_renesas_init_param *p) { - static u32 save[MAX_INDEX]; + u32 val = 0; int ret; - u32 val; - - WARN_ON(p->index >= MAX_INDEX); switch (p->mode) { - case MODE_RESTORE: - ufshcd_writel(hba, save[p->index], p->reg); - break; - case MODE_SET: - save[p->index] |= p->u.set; - break; - case MODE_SAVE: - save[p->index] = ufshcd_readl(hba, p->reg) & p->mask; - break; case MODE_POLL: ret = readl_poll_timeout_atomic(hba->mmio_base + p->reg, val, @@ -85,6 +63,9 @@ static void ufs_renesas_reg_control(struct ufs_hba *hba, dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n", __func__, ret, val, p->mask, p->u.expected); break; + case MODE_READ: + val = ufshcd_readl(hba, p->reg); + break; case MODE_WAIT: if (p->u.delay_us > 1000) mdelay(DIV_ROUND_UP(p->u.delay_us, 1000)); @@ -97,6 +78,8 @@ static void ufs_renesas_reg_control(struct ufs_hba *hba, default: break; } + + return val; } static void ufs_renesas_poll(struct ufs_hba *hba, u32 reg, u32 expected, u32 mask) @@ -111,38 +94,14 @@ static void ufs_renesas_poll(struct ufs_hba *hba, u32 reg, u32 expected, u32 mas ufs_renesas_reg_control(hba, ¶m); } -static void ufs_renesas_restore(struct ufs_hba *hba, u32 reg, u32 index) -{ - struct ufs_renesas_init_param param = { - .mode = MODE_RESTORE, - .reg = reg, - .index = index, - }; - - ufs_renesas_reg_control(hba, ¶m); -} - -static void ufs_renesas_save(struct ufs_hba *hba, u32 reg, u32 mask, u32 index) +static u32 ufs_renesas_read(struct ufs_hba *hba, u32 reg) { struct ufs_renesas_init_param param = { - .mode = MODE_SAVE, + .mode = MODE_READ, .reg = reg, - .mask = mask, - .index = index, - }; - - ufs_renesas_reg_control(hba, ¶m); -} - -static void ufs_renesas_set(struct ufs_hba *hba, u32 index, u32 set) -{ - struct ufs_renesas_init_param param = { - .mode = MODE_SAVE, - .index = index, - .u.set = set, }; - ufs_renesas_reg_control(hba, ¶m); + return ufs_renesas_reg_control(hba, ¶m); } static void ufs_renesas_wait(struct ufs_hba *hba, u32 delay_us) @@ -181,15 +140,6 @@ static void ufs_renesas_write_800_80c_poll(struct ufs_hba *hba, u32 addr, ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); } -static void ufs_renesas_restore_800_80c_poll(struct ufs_hba *hba, u32 index) -{ - ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); - ufs_renesas_write(hba, 0xd0, 0x00000800); - ufs_renesas_restore(hba, 0xd4, index); - ufs_renesas_write(hba, 0xd0, 0x0000080c); - ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); -} - static void ufs_renesas_write_804_80c_poll(struct ufs_hba *hba, u32 addr, u32 data_804) { ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); @@ -220,6 +170,8 @@ static void ufs_renesas_write_phy(struct ufs_hba *hba, u32 addr16, u32 data16) static void ufs_renesas_set_phy(struct ufs_hba *hba, u32 addr16, u32 data16) { + u32 low, high; + ufs_renesas_write(hba, 0xf0, 1); ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff); ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff); @@ -227,22 +179,15 @@ static void ufs_renesas_set_phy(struct ufs_hba *hba, u32 addr16, u32 data16) ufs_renesas_write_828_82c_poll(hba, 0x0f000000); ufs_renesas_write_804_80c_poll(hba, 0x1a, 0); ufs_renesas_write(hba, 0xd0, 0x00000808); - ufs_renesas_save(hba, 0xd4, 0xff, SET_PHY_INDEX_LO); + low = ufs_renesas_read(hba, 0xd4) & 0xff; ufs_renesas_write_804_80c_poll(hba, 0x1b, 0); ufs_renesas_write(hba, 0xd0, 0x00000808); - ufs_renesas_save(hba, 0xd4, 0xff, SET_PHY_INDEX_HI); - ufs_renesas_write_828_82c_poll(hba, 0x0f000000); - ufs_renesas_write(hba, 0xf0, 0); - ufs_renesas_write(hba, 0xf0, 1); - ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff); - ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff); - ufs_renesas_set(hba, SET_PHY_INDEX_LO, ((data16 & 0xff) << 16) | BIT(8) | 0x18); - ufs_renesas_restore_800_80c_poll(hba, SET_PHY_INDEX_LO); - ufs_renesas_set(hba, SET_PHY_INDEX_HI, (((data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19); - ufs_renesas_restore_800_80c_poll(hba, SET_PHY_INDEX_HI); - ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01); + high = ufs_renesas_read(hba, 0xd4) & 0xff; ufs_renesas_write_828_82c_poll(hba, 0x0f000000); ufs_renesas_write(hba, 0xf0, 0); + + data16 |= (high << 8) | low; + ufs_renesas_write_phy(hba, addr16, data16); } static void ufs_renesas_indirect_write(struct ufs_hba *hba, u32 gpio, u32 addr, @@ -266,6 +211,8 @@ static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr, static void ufs_renesas_pre_init(struct ufs_hba *hba) { + u32 timer_val; + /* This setting is for SERIES B */ ufs_renesas_write(hba, 0xc0, 0x49425308); ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002); @@ -292,7 +239,7 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) ufs_renesas_poll(hba, 0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)); ufs_renesas_write(hba, 0xd0, 0x00000d00); - ufs_renesas_save(hba, 0xd4, 0x0000ffff, TIMER_INDEX); + timer_val = ufs_renesas_read(hba, 0xd4) & 0x0000ffff; ufs_renesas_write(hba, 0xd4, 0x00000000); ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000); ufs_renesas_write_d0_d4(hba, 0x00000828, 0x08000000); @@ -387,7 +334,7 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) ufs_renesas_write(hba, 0xf0, 0); ufs_renesas_write(hba, 0xd0, 0x00000d00); - ufs_renesas_restore(hba, 0xd4, TIMER_INDEX); + ufs_renesas_write(hba, 0xd4, timer_val); } static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba, From patchwork Wed Mar 5 13:34:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 14002717 Received: from gauss.telenet-ops.be (gauss.telenet-ops.be [195.130.132.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DE34248884 for ; Wed, 5 Mar 2025 13:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.49 ARC-Seal: i=1; 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spf=none smtp.mailfrom=linux-m68k.org Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [IPv6:2a02:1800:120:4::f00:14]) by gauss.telenet-ops.be (Postfix) with ESMTPS id 4Z7D6t3vVLz4x6ct for ; Wed, 05 Mar 2025 14:34:30 +0100 (CET) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:fba:8cad:3d23:9db3]) by xavier.telenet-ops.be with cmsmtp id M1aJ2E00J0exi8p011aJln; Wed, 05 Mar 2025 14:34:22 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1tposn-0000000Cv42-1LkA; Wed, 05 Mar 2025 14:34:18 +0100 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1tpot8-00000008woZ-1nvb; Wed, 05 Mar 2025 14:34:18 +0100 From: Geert Uytterhoeven To: Yoshihiro Shimoda , "James E . J . Bottomley" , "Martin K . Petersen" , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 4/7] scsi: ufs: renesas: Remove register control helper function Date: Wed, 5 Mar 2025 14:34:12 +0100 Message-ID: <69500e4c18be1ca1de360f9e797e282ffef04004.1741179611.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Yoshihiro Shimoda After refactoring the code, ufs_renesas_reg_control() is no longer needed, because all operations are simple and can be called directly. Remove the ufs_renesas_reg_control() helper function, and call udelay() directly. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Geert Uytterhoeven --- v3: - No changes, v2: - Remove not just MODE_WAIT, but all of the struct-based control. --- drivers/ufs/host/ufs-renesas.c | 102 +++++---------------------------- 1 file changed, 14 insertions(+), 88 deletions(-) diff --git a/drivers/ufs/host/ufs-renesas.c b/drivers/ufs/host/ufs-renesas.c index 100186a2e1807445..59e35ec4955f19af 100644 --- a/drivers/ufs/host/ufs-renesas.c +++ b/drivers/ufs/host/ufs-renesas.c @@ -23,106 +23,32 @@ struct ufs_renesas_priv { bool initialized; /* The hardware needs initialization once */ }; -enum ufs_renesas_init_param_mode { - MODE_POLL, - MODE_READ, - MODE_WAIT, - MODE_WRITE, -}; - -struct ufs_renesas_init_param { - enum ufs_renesas_init_param_mode mode; - u32 reg; - union { - u32 expected; - u32 delay_us; - u32 val; - } u; - u32 mask; - u32 index; -}; - static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba) { ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + "); } -static u32 ufs_renesas_reg_control(struct ufs_hba *hba, - const struct ufs_renesas_init_param *p) -{ - u32 val = 0; - int ret; - - switch (p->mode) { - case MODE_POLL: - ret = readl_poll_timeout_atomic(hba->mmio_base + p->reg, - val, - (val & p->mask) == p->u.expected, - 10, 1000); - if (ret) - dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n", - __func__, ret, val, p->mask, p->u.expected); - break; - case MODE_READ: - val = ufshcd_readl(hba, p->reg); - break; - case MODE_WAIT: - if (p->u.delay_us > 1000) - mdelay(DIV_ROUND_UP(p->u.delay_us, 1000)); - else - udelay(p->u.delay_us); - break; - case MODE_WRITE: - ufshcd_writel(hba, p->u.val, p->reg); - break; - default: - break; - } - - return val; -} - static void ufs_renesas_poll(struct ufs_hba *hba, u32 reg, u32 expected, u32 mask) { - struct ufs_renesas_init_param param = { - .mode = MODE_POLL, - .reg = reg, - .u.expected = expected, - .mask = mask, - }; - - ufs_renesas_reg_control(hba, ¶m); + int ret; + u32 val; + + ret = readl_poll_timeout_atomic(hba->mmio_base + reg, + val, (val & mask) == expected, + 10, 1000); + if (ret) + dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n", + __func__, ret, val, mask, expected); } static u32 ufs_renesas_read(struct ufs_hba *hba, u32 reg) { - struct ufs_renesas_init_param param = { - .mode = MODE_READ, - .reg = reg, - }; - - return ufs_renesas_reg_control(hba, ¶m); -} - -static void ufs_renesas_wait(struct ufs_hba *hba, u32 delay_us) -{ - struct ufs_renesas_init_param param = { - .mode = MODE_WAIT, - .u.delay_us = delay_us, - }; - - ufs_renesas_reg_control(hba, ¶m); + return ufshcd_readl(hba, reg); } static void ufs_renesas_write(struct ufs_hba *hba, u32 reg, u32 value) { - struct ufs_renesas_init_param param = { - .mode = MODE_WRITE, - .reg = reg, - .u.val = value, - }; - - ufs_renesas_reg_control(hba, ¶m); + ufshcd_writel(hba, value, reg); } static void ufs_renesas_write_d0_d4(struct ufs_hba *hba, u32 data_d0, u32 data_d4) @@ -216,13 +142,13 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) /* This setting is for SERIES B */ ufs_renesas_write(hba, 0xc0, 0x49425308); ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002); - ufs_renesas_wait(hba, 1); + udelay(1); ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000200); - ufs_renesas_wait(hba, 1); + udelay(1); ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000000); ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000001); ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000001); - ufs_renesas_wait(hba, 1); + udelay(1); ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000000); ufs_renesas_write(hba, 0xc0, 0x49425308); From patchwork Wed Mar 5 13:34:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 14002718 Received: from weierstrass.telenet-ops.be (weierstrass.telenet-ops.be [195.130.137.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BD7D24A04C for ; Wed, 5 Mar 2025 13:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.81 ARC-Seal: i=1; a=rsa-sha256; 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Wed, 05 Mar 2025 14:34:30 +0100 (CET) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:fba:8cad:3d23:9db3]) by xavier.telenet-ops.be with cmsmtp id M1aJ2E00K0exi8p011aJlo; Wed, 05 Mar 2025 14:34:22 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1tposn-0000000Cv48-1XDH; Wed, 05 Mar 2025 14:34:18 +0100 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1tpot8-00000008woe-1w1Y; Wed, 05 Mar 2025 14:34:18 +0100 From: Geert Uytterhoeven To: Yoshihiro Shimoda , "James E . J . Bottomley" , "Martin K . Petersen" , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 5/7] scsi: ufs: renesas: Refactor 0x10ad/0x10af PHY settings Date: Wed, 5 Mar 2025 14:34:13 +0100 Message-ID: <110eafd1ee24f9db0285a5e2bca224e35962268a.1741179611.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Yoshihiro Shimoda Extract specific PHY setting of the 0x10a[df] registers into a new function. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Geert Uytterhoeven --- v3: - No changes, v2: - Reword. --- drivers/ufs/host/ufs-renesas.c | 37 +++++++++++++--------------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/ufs/host/ufs-renesas.c b/drivers/ufs/host/ufs-renesas.c index 59e35ec4955f19af..e4510e9b1a2cb195 100644 --- a/drivers/ufs/host/ufs-renesas.c +++ b/drivers/ufs/host/ufs-renesas.c @@ -135,6 +135,16 @@ static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr, ufs_renesas_write(hba, 0xf0, 0); } +static void ufs_renesas_write_phy_10ad_10af(struct ufs_hba *hba, + u32 data_10ad, u32 data_10af) +{ + ufs_renesas_write_phy(hba, 0x10ae, 0x0001); + ufs_renesas_write_phy(hba, 0x10ad, data_10ad); + ufs_renesas_write_phy(hba, 0x10af, data_10af); + ufs_renesas_write_phy(hba, 0x10b6, 0x0001); + ufs_renesas_write_phy(hba, 0x10ae, 0x0000); +} + static void ufs_renesas_pre_init(struct ufs_hba *hba) { u32 timer_val; @@ -209,29 +219,10 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) ufs_renesas_write_phy(hba, 0x4000, 0x0000); ufs_renesas_write_phy(hba, 0x4001, 0x0000); - ufs_renesas_write_phy(hba, 0x10ae, 0x0001); - ufs_renesas_write_phy(hba, 0x10ad, 0x0000); - ufs_renesas_write_phy(hba, 0x10af, 0x0001); - ufs_renesas_write_phy(hba, 0x10b6, 0x0001); - ufs_renesas_write_phy(hba, 0x10ae, 0x0000); - - ufs_renesas_write_phy(hba, 0x10ae, 0x0001); - ufs_renesas_write_phy(hba, 0x10ad, 0x0000); - ufs_renesas_write_phy(hba, 0x10af, 0x0002); - ufs_renesas_write_phy(hba, 0x10b6, 0x0001); - ufs_renesas_write_phy(hba, 0x10ae, 0x0000); - - ufs_renesas_write_phy(hba, 0x10ae, 0x0001); - ufs_renesas_write_phy(hba, 0x10ad, 0x0080); - ufs_renesas_write_phy(hba, 0x10af, 0x0000); - ufs_renesas_write_phy(hba, 0x10b6, 0x0001); - ufs_renesas_write_phy(hba, 0x10ae, 0x0000); - - ufs_renesas_write_phy(hba, 0x10ae, 0x0001); - ufs_renesas_write_phy(hba, 0x10ad, 0x0080); - ufs_renesas_write_phy(hba, 0x10af, 0x001a); - ufs_renesas_write_phy(hba, 0x10b6, 0x0001); - ufs_renesas_write_phy(hba, 0x10ae, 0x0000); + ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0001); + ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0002); + ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x0000); + ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x001a); ufs_renesas_indirect_write(hba, 7, 0x70, 0x0016); ufs_renesas_indirect_write(hba, 7, 0x71, 0x0016); From patchwork Wed Mar 5 13:34:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 14002721 Received: from gauss.telenet-ops.be (gauss.telenet-ops.be [195.130.132.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FDBF24A051 for ; Wed, 5 Mar 2025 13:34:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741181676; cv=none; b=tO2BSz3xT6EPdQldwktkDn9ey5NYDv19ghoxBFnGAgJl01/gjcOhRYHyNyK7Y03TQk8KGTbcj7SgXElxsQ0al7b+yC5DgUgUFeUWq2Lc7k9Nezdl5lHgFtE6UWjQL+HbRt08w4NCnJbVgsv7J2m6AZsEdPsa9Anhz4vszbinQf8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741181676; c=relaxed/simple; bh=2CQfQYPB2DJ1ROQb4shpWr4KDmFhYio/1xwOBxthYMQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mAjnKyDNPFYUcPQ6J6qFEIK5lhqbTmkctqvkaMFJzyeMeUnbM32hc+JWxxnkLGkONXYNrOIhVKSxpxMdBBy7bHtmYNQj0I8uHNUCgGe0rQYnFgBnDypHMrIYmSpywolhdneNUZViHN1tg3vacjzUh5SN3m2Htu5kTPhng3ikrPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from albert.telenet-ops.be (albert.telenet-ops.be [IPv6:2a02:1800:110:4::f00:1a]) by gauss.telenet-ops.be (Postfix) with ESMTPS id 4Z7D6v3NZvz4x21w for ; Wed, 05 Mar 2025 14:34:31 +0100 (CET) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:fba:8cad:3d23:9db3]) by albert.telenet-ops.be with cmsmtp id M1aL2E00B0exi8p061aLDJ; Wed, 05 Mar 2025 14:34:23 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1tposn-0000000Cv4A-1dSZ; Wed, 05 Mar 2025 14:34:18 +0100 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1tpot8-00000008woj-23Ft; Wed, 05 Mar 2025 14:34:18 +0100 From: Geert Uytterhoeven To: Yoshihiro Shimoda , "James E . J . Bottomley" , "Martin K . Petersen" , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 6/7] scsi: ufs: renesas: Add reusable functions Date: Wed, 5 Mar 2025 14:34:14 +0100 Message-ID: <446d67b751a96645799de3aeefec539735aa78c8.1741179611.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Yoshihiro Shimoda Since some settings can be reused on other UFS controller (R-Car S4-8 ES1.2), add reusable functions. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Geert Uytterhoeven --- v3: - Rename ufs_renesas_init_ufshc() to ufs_renesas_init_step1_to_3(), - Extract ufs_renesas_init_step4_to_6(), - Move ufs_renesas_write_phy_10ad_10af() just before its sole user, v2: - No changes. --- drivers/ufs/host/ufs-renesas.c | 71 ++++++++++++++++++++++++---------- 1 file changed, 50 insertions(+), 21 deletions(-) diff --git a/drivers/ufs/host/ufs-renesas.c b/drivers/ufs/host/ufs-renesas.c index e4510e9b1a2cb195..d9ba766dcd2f4de7 100644 --- a/drivers/ufs/host/ufs-renesas.c +++ b/drivers/ufs/host/ufs-renesas.c @@ -135,21 +135,8 @@ static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr, ufs_renesas_write(hba, 0xf0, 0); } -static void ufs_renesas_write_phy_10ad_10af(struct ufs_hba *hba, - u32 data_10ad, u32 data_10af) +static void ufs_renesas_init_step1_to_3(struct ufs_hba *hba) { - ufs_renesas_write_phy(hba, 0x10ae, 0x0001); - ufs_renesas_write_phy(hba, 0x10ad, data_10ad); - ufs_renesas_write_phy(hba, 0x10af, data_10af); - ufs_renesas_write_phy(hba, 0x10b6, 0x0001); - ufs_renesas_write_phy(hba, 0x10ae, 0x0000); -} - -static void ufs_renesas_pre_init(struct ufs_hba *hba) -{ - u32 timer_val; - - /* This setting is for SERIES B */ ufs_renesas_write(hba, 0xc0, 0x49425308); ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002); udelay(1); @@ -163,7 +150,10 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) ufs_renesas_write(hba, 0xc0, 0x49425308); ufs_renesas_write(hba, 0xc0, 0x41584901); +} +static void ufs_renesas_init_step4_to_6(struct ufs_hba *hba) +{ ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); ufs_renesas_write_d0_d4(hba, 0x00000804, 0x00000000); ufs_renesas_write(hba, 0xd0, 0x0000080c); @@ -173,6 +163,11 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) ufs_renesas_write(hba, 0xd0, 0x00000804); ufs_renesas_poll(hba, 0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)); +} + +static u32 ufs_renesas_init_disable_timer(struct ufs_hba *hba) +{ + u32 timer_val; ufs_renesas_write(hba, 0xd0, 0x00000d00); timer_val = ufs_renesas_read(hba, 0xd4) & 0x0000ffff; @@ -184,6 +179,45 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) ufs_renesas_write(hba, 0xd0, 0x00000d2c); ufs_renesas_poll(hba, 0xd4, BIT(0), BIT(0)); + return timer_val; +} + +static void ufs_renesas_init_enable_timer(struct ufs_hba *hba, u32 timer_val) +{ + ufs_renesas_write(hba, 0xf0, 0); + ufs_renesas_write(hba, 0xd0, 0x00000d00); + ufs_renesas_write(hba, 0xd4, timer_val); +} + +static void ufs_renesas_write_phy_10ad_10af(struct ufs_hba *hba, + u32 data_10ad, u32 data_10af) +{ + ufs_renesas_write_phy(hba, 0x10ae, 0x0001); + ufs_renesas_write_phy(hba, 0x10ad, data_10ad); + ufs_renesas_write_phy(hba, 0x10af, data_10af); + ufs_renesas_write_phy(hba, 0x10b6, 0x0001); + ufs_renesas_write_phy(hba, 0x10ae, 0x0000); +} + +static void ufs_renesas_init_compensation_and_slicers(struct ufs_hba *hba) +{ + ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0001); + ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0002); + ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x0000); + ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x001a); +} + +static void ufs_renesas_pre_init(struct ufs_hba *hba) +{ + u32 timer_val; + + /* This setting is for SERIES B */ + ufs_renesas_init_step1_to_3(hba); + + ufs_renesas_init_step4_to_6(hba); + + timer_val = ufs_renesas_init_disable_timer(hba); + /* phy setup */ ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f); ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014); @@ -219,10 +253,7 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) ufs_renesas_write_phy(hba, 0x4000, 0x0000); ufs_renesas_write_phy(hba, 0x4001, 0x0000); - ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0001); - ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0002); - ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x0000); - ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x001a); + ufs_renesas_init_compensation_and_slicers(hba); ufs_renesas_indirect_write(hba, 7, 0x70, 0x0016); ufs_renesas_indirect_write(hba, 7, 0x71, 0x0016); @@ -249,9 +280,7 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7)); /* end of phy setup */ - ufs_renesas_write(hba, 0xf0, 0); - ufs_renesas_write(hba, 0xd0, 0x00000d00); - ufs_renesas_write(hba, 0xd4, timer_val); + ufs_renesas_init_enable_timer(hba, timer_val); } static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba, From patchwork Wed Mar 5 13:34:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 14002715 Received: from gauss.telenet-ops.be (gauss.telenet-ops.be [195.130.132.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77AFF24888C for ; Wed, 5 Mar 2025 13:34:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741181668; cv=none; b=SECkghi/USy6A613x5XDRU7mYTRVuOMqyahfGXu0ZF11Dm4pidbdjqoJtQ61y0KXqLapVHzTQiDE/L7hsluhFcGbEdJEBWDaWxIKdH7+6qtek6rZS+7q7Qm7Uh06TdSvVyyhdvPhzaV+j306twZywFXvJJzrZCpwixRDggu1J8Y= ARC-Message-Signature: i=1; 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Wed, 05 Mar 2025 14:34:22 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.97) (envelope-from ) id 1tposn-0000000Cv4F-1kOZ; Wed, 05 Mar 2025 14:34:18 +0100 Received: from geert by rox.of.borg with local (Exim 4.97) (envelope-from ) id 1tpot8-00000008woo-2Ewn; Wed, 05 Mar 2025 14:34:18 +0100 From: Geert Uytterhoeven To: Yoshihiro Shimoda , "James E . J . Bottomley" , "Martin K . Petersen" , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 7/7] scsi: ufs: renesas: Add initialization code for R-Car S4-8 ES1.2 Date: Wed, 5 Mar 2025 14:34:15 +0100 Message-ID: <97d83709495c764b2456d4d25846f5f48197cad0.1741179611.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Yoshihiro Shimoda Add initialization code for R-Car S4-8 ES1.2 to improve transfer stability. Using the new code requires downloading firmware and reading calibration data from E-FUSE. If either fails, the driver falls back to the old initialization code. Signed-off-by: Yoshihiro Shimoda Co-developed-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven --- v3: - New. --- drivers/ufs/host/ufs-renesas.c | 199 ++++++++++++++++++++++++++++++++- 1 file changed, 194 insertions(+), 5 deletions(-) diff --git a/drivers/ufs/host/ufs-renesas.c b/drivers/ufs/host/ufs-renesas.c index d9ba766dcd2f4de7..5bf7d0e77ad857c6 100644 --- a/drivers/ufs/host/ufs-renesas.c +++ b/drivers/ufs/host/ufs-renesas.c @@ -9,20 +9,31 @@ #include #include #include +#include #include #include #include +#include #include #include #include +#include #include #include "ufshcd-pltfrm.h" +#define EFUSE_CALIB_SIZE 8 + struct ufs_renesas_priv { + const struct firmware *fw; + void (*pre_init)(struct ufs_hba *hba); bool initialized; /* The hardware needs initialization once */ + u8 calib[EFUSE_CALIB_SIZE]; }; +#define UFS_RENESAS_FIRMWARE_NAME "r8a779f0_ufs.bin" +MODULE_FIRMWARE(UFS_RENESAS_FIRMWARE_NAME); + static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba) { ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + "); @@ -116,6 +127,22 @@ static void ufs_renesas_set_phy(struct ufs_hba *hba, u32 addr16, u32 data16) ufs_renesas_write_phy(hba, addr16, data16); } +static void ufs_renesas_reset_indirect_write(struct ufs_hba *hba, int gpio, + u32 addr, u32 data) +{ + ufs_renesas_write(hba, 0xf0, gpio); + ufs_renesas_write_800_80c_poll(hba, addr, data); +} + +static void ufs_renesas_reset_indirect_update(struct ufs_hba *hba) +{ + ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000); + ufs_renesas_write_d0_d4(hba, 0x00000828, 0x0f000000); + ufs_renesas_write(hba, 0xd0, 0x0000082c); + ufs_renesas_poll(hba, 0xd4, BIT(27) | BIT(26) | BIT(24), BIT(27) | BIT(26) | BIT(24)); + ufs_renesas_write(hba, 0xf0, 0); +} + static void ufs_renesas_indirect_write(struct ufs_hba *hba, u32 gpio, u32 addr, u32 data_800) { @@ -135,15 +162,19 @@ static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr, ufs_renesas_write(hba, 0xf0, 0); } -static void ufs_renesas_init_step1_to_3(struct ufs_hba *hba) +static void ufs_renesas_init_step1_to_3(struct ufs_hba *hba, bool init108) { ufs_renesas_write(hba, 0xc0, 0x49425308); ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002); + if (init108) + ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000002); udelay(1); ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000200); udelay(1); ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000000); ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000001); + if (init108) + ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000001); ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000001); udelay(1); ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000000); @@ -207,12 +238,12 @@ static void ufs_renesas_init_compensation_and_slicers(struct ufs_hba *hba) ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x001a); } -static void ufs_renesas_pre_init(struct ufs_hba *hba) +static void ufs_renesas_r8a779f0_es10_pre_init(struct ufs_hba *hba) { u32 timer_val; /* This setting is for SERIES B */ - ufs_renesas_init_step1_to_3(hba); + ufs_renesas_init_step1_to_3(hba, false); ufs_renesas_init_step4_to_6(hba); @@ -283,6 +314,105 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba) ufs_renesas_init_enable_timer(hba, timer_val); } +static void ufs_renesas_r8a779f0_init_step3_add(struct ufs_hba *hba, bool assert) +{ + u32 val_2x = 0, val_3x = 0, val_4x = 0; + + if (assert) { + val_2x = 0x0001; + val_3x = 0x0003; + val_4x = 0x0001; + } + + ufs_renesas_reset_indirect_write(hba, 7, 0x20, val_2x); + ufs_renesas_reset_indirect_write(hba, 7, 0x4a, val_4x); + ufs_renesas_reset_indirect_write(hba, 7, 0x35, val_3x); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_reset_indirect_write(hba, 7, 0x21, val_2x); + ufs_renesas_reset_indirect_write(hba, 7, 0x4b, val_4x); + ufs_renesas_reset_indirect_write(hba, 7, 0x36, val_3x); + ufs_renesas_reset_indirect_update(hba); +} + +static void ufs_renesas_r8a779f0_pre_init(struct ufs_hba *hba) +{ + struct ufs_renesas_priv *priv = ufshcd_get_variant(hba); + u32 timer_val; + u32 data; + int i; + + /* This setting is for SERIES B */ + ufs_renesas_init_step1_to_3(hba, true); + + ufs_renesas_r8a779f0_init_step3_add(hba, true); + ufs_renesas_reset_indirect_write(hba, 7, 0x5f, 0x0063); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_reset_indirect_write(hba, 7, 0x60, 0x0003); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_reset_indirect_write(hba, 7, 0x5b, 0x00a6); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_reset_indirect_write(hba, 7, 0x5c, 0x0003); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_r8a779f0_init_step3_add(hba, false); + + ufs_renesas_init_step4_to_6(hba); + + timer_val = ufs_renesas_init_disable_timer(hba); + + ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0007); + ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007); + + ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7)); + ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4)); + + ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080); + ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001); + ufs_renesas_indirect_write(hba, 1, 0x2c, 0x0001); + ufs_renesas_indirect_write(hba, 1, 0x32, 0x0087); + + ufs_renesas_indirect_write(hba, 1, 0x4d, priv->calib[2]); + ufs_renesas_indirect_write(hba, 1, 0x4e, priv->calib[3]); + ufs_renesas_indirect_write(hba, 1, 0x0d, 0x0006); + ufs_renesas_indirect_write(hba, 1, 0x0e, 0x0007); + ufs_renesas_write_phy(hba, 0x0028, priv->calib[3]); + ufs_renesas_write_phy(hba, 0x4014, priv->calib[3]); + + ufs_renesas_set_phy(hba, 0x401c, BIT(2)); + + ufs_renesas_write_phy(hba, 0x4000, priv->calib[6]); + ufs_renesas_write_phy(hba, 0x4001, priv->calib[7]); + + ufs_renesas_indirect_write(hba, 1, 0x14, 0x0001); + + ufs_renesas_init_compensation_and_slicers(hba); + + ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c); + ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c); + ufs_renesas_indirect_write(hba, 7, 0x62, 0x00c0); + ufs_renesas_indirect_write(hba, 7, 0x63, 0x0001); + + for (i = 0; i < priv->fw->size / 2; i++) { + data = (priv->fw->data[i * 2 + 1] << 8) | priv->fw->data[i * 2]; + ufs_renesas_write_phy(hba, 0xc000 + i, data); + } + + ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002); + ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007); + + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017); + ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6)); + ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7)); + + ufs_renesas_init_enable_timer(hba, timer_val); +} + static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba, enum ufs_notify_change_status status) { @@ -292,7 +422,7 @@ static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba, return 0; if (status == PRE_CHANGE) - ufs_renesas_pre_init(hba); + priv->pre_init(hba); priv->initialized = true; @@ -310,20 +440,78 @@ static int ufs_renesas_setup_clocks(struct ufs_hba *hba, bool on, return 0; } +static const struct soc_device_attribute ufs_fallback[] = { + { .soc_id = "r8a779f0", .revision = "ES1.[01]" }, + { /* Sentinel */ } +}; + static int ufs_renesas_init(struct ufs_hba *hba) { + const struct soc_device_attribute *attr; + struct nvmem_cell *cell = NULL; + struct device *dev = hba->dev; struct ufs_renesas_priv *priv; + u8 *data = NULL; + size_t len; + int ret; - priv = devm_kzalloc(hba->dev, sizeof(*priv), GFP_KERNEL); + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; ufshcd_set_variant(hba, priv); hba->quirks |= UFSHCD_QUIRK_HIBERN_FASTAUTO; + attr = soc_device_match(ufs_fallback); + if (attr) + goto fallback; + + ret = request_firmware(&priv->fw, UFS_RENESAS_FIRMWARE_NAME, dev); + if (ret) { + dev_warn(dev, "Failed to load firmware\n"); + goto fallback; + } + + cell = nvmem_cell_get(dev, "calibration"); + if (IS_ERR(cell)) { + dev_warn(dev, "No calibration data specified\n"); + goto fallback; + } + + data = nvmem_cell_read(cell, &len); + if (IS_ERR(data)) { + dev_warn(dev, "Failed to read calibration data: %pe\n", data); + goto fallback; + } + + if (len != EFUSE_CALIB_SIZE) { + dev_warn(dev, "Invalid calibration data size %zu\n", len); + goto fallback; + } + + memcpy(priv->calib, data, EFUSE_CALIB_SIZE); + priv->pre_init = ufs_renesas_r8a779f0_pre_init; + goto out; + +fallback: + dev_info(dev, "Using ES1.0 init code\n"); + priv->pre_init = ufs_renesas_r8a779f0_es10_pre_init; + +out: + kfree(data); + if (!IS_ERR_OR_NULL(cell)) + nvmem_cell_put(cell); + return 0; } +static void ufs_renesas_exit(struct ufs_hba *hba) +{ + struct ufs_renesas_priv *priv = ufshcd_get_variant(hba); + + release_firmware(priv->fw); +} + static int ufs_renesas_set_dma_mask(struct ufs_hba *hba) { return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); @@ -332,6 +520,7 @@ static int ufs_renesas_set_dma_mask(struct ufs_hba *hba) static const struct ufs_hba_variant_ops ufs_renesas_vops = { .name = "renesas", .init = ufs_renesas_init, + .exit = ufs_renesas_exit, .set_dma_mask = ufs_renesas_set_dma_mask, .setup_clocks = ufs_renesas_setup_clocks, .hce_enable_notify = ufs_renesas_hce_enable_notify,