From patchwork Wed Mar 20 09:49:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861215 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96FFF1575 for ; Wed, 20 Mar 2019 09:50:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 846C629A3B for ; Wed, 20 Mar 2019 09:50:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 78A5E29AA4; Wed, 20 Mar 2019 09:50:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1E1FE29A3B for ; Wed, 20 Mar 2019 09:50:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727528AbfCTJtl (ORCPT ); Wed, 20 Mar 2019 05:49:41 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50192 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725996AbfCTJtl (ORCPT ); Wed, 20 Mar 2019 05:49:41 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id EDA7A60E7A; Wed, 20 Mar 2019 09:49:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1553075379; bh=OJALzsWlECZ4X10Xb4pxyAdKOLu5a0A06V+PzDVAsIc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jr5w5w74hexB0gSDO9U3LTDJAjSXPHAMo47jw/l/nKf4QUkkI0dzoluwpt9/gPdsi 8FGpFx8EEK23esGk4vvYBzgyi1X1teVZX7moXHRvssXyNlsrM+X1wENEENz+w/gTdZ gKmt2E0WXGg4DX0qg48xThAEOa6ejQnQ8hBx7I8g= Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 691C06072E; Wed, 20 Mar 2019 09:49:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1553075379; bh=OJALzsWlECZ4X10Xb4pxyAdKOLu5a0A06V+PzDVAsIc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jr5w5w74hexB0gSDO9U3LTDJAjSXPHAMo47jw/l/nKf4QUkkI0dzoluwpt9/gPdsi 8FGpFx8EEK23esGk4vvYBzgyi1X1teVZX7moXHRvssXyNlsrM+X1wENEENz+w/gTdZ gKmt2E0WXGg4DX0qg48xThAEOa6ejQnQ8hBx7I8g= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 691C06072E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 01/11] OPP: Don't overwrite rounded clk rate Date: Wed, 20 Mar 2019 15:19:08 +0530 Message-Id: <20190320094918.20234-2-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stephen Boyd Doing this allows us to call this API with any rate requested and have it not need to match in the OPP table. Instead, we'll round the rate up to the nearest OPP that we see so that we can get the voltage or level that's required for that OPP. This supports users of OPP that want to specify the 'fmax' tables of a device instead of every single frequency that they need. And for devices that required the exact frequency, we can rely on the clk framework to round the rate to the nearest supported frequency instead of the OPP framework to do so. Note that this may affect drivers that don't want the clk framework to do rounding, but instead want the OPP table to do the rounding for them. Do we have that case? Should we add some flag to the OPP table to indicate this and then not have that flag set when there isn't an OPP table for the device and also introduce a property like 'opp-use-clk' to tell the table that it should use the clk APIs to round rates instead of OPP? Signed-off-by: Stephen Boyd Signed-off-by: Rajendra Nayak --- drivers/opp/core.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 0420f7e8ad5b..bc9a7762dd4c 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -703,7 +703,7 @@ static int _set_required_opps(struct device *dev, int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq) { struct opp_table *opp_table; - unsigned long freq, old_freq; + unsigned long freq, opp_freq, old_freq, old_opp_freq; struct dev_pm_opp *old_opp, *opp; struct clk *clk; int ret; @@ -742,13 +742,15 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq) goto put_opp_table; } - old_opp = _find_freq_ceil(opp_table, &old_freq); + old_opp_freq = old_freq; + old_opp = _find_freq_ceil(opp_table, &old_opp_freq); if (IS_ERR(old_opp)) { dev_err(dev, "%s: failed to find current OPP for freq %lu (%ld)\n", __func__, old_freq, PTR_ERR(old_opp)); } - opp = _find_freq_ceil(opp_table, &freq); + opp_freq = freq; + opp = _find_freq_ceil(opp_table, &opp_freq); if (IS_ERR(opp)) { ret = PTR_ERR(opp); dev_err(dev, "%s: failed to find OPP for freq %lu (%d)\n", From patchwork Wed Mar 20 09:49:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861119 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 490661823 for ; Wed, 20 Mar 2019 09:49:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 347CD299CE for ; Wed, 20 Mar 2019 09:49:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2770629AA4; Wed, 20 Mar 2019 09:49:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B8B9229A3B for ; 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Wed, 20 Mar 2019 09:49:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1553075383; bh=6K/mOBjwq4m7bf70C+pKlJIhBb1FQQx0UG/7mUG4KO4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cozizOBOAhpHZfTp+WVFQlO/Ic5NMirM/LNjRv5s9byRfT6W7a0ZWyGMFEV0SKL03 YSgBkVIvFsvJ/IEsmsP7ppJ+WqsmCZUIBtkIchooQkJNtv8L7ELIPluOOWGOTMZ4UC g3OHHv38NVB8I3SekGkHZ5kdAODth/r7y4Q0kZpw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 92A6960E3F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 02/11] OPP: Make dev_pm_opp_set_rate() with freq=0 as valid Date: Wed, 20 Mar 2019 15:19:09 +0530 Message-Id: <20190320094918.20234-3-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For devices with performance state, we use dev_pm_opp_set_rate() to set the appropriate clk rate and the performance state. We do need a way to *remove* the performance state vote when we idle the device and turn the clocks off. Use dev_pm_opp_set_rate() with freq=0 to achieve this. Signed-off-by: Rajendra Nayak Signed-off-by: Stephen Boyd --- drivers/opp/core.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index bc9a7762dd4c..d6acc880676e 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -708,18 +708,24 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq) struct clk *clk; int ret; - if (unlikely(!target_freq)) { - dev_err(dev, "%s: Invalid target frequency %lu\n", __func__, - target_freq); - return -EINVAL; - } - opp_table = _find_opp_table(dev); if (IS_ERR(opp_table)) { dev_err(dev, "%s: device opp doesn't exist\n", __func__); return PTR_ERR(opp_table); } + if (unlikely(!target_freq)) { + if (opp_table->required_opp_tables) { + /* drop the performance state vote */ + dev_pm_genpd_set_performance_state(dev, 0); + return 0; + } else { + dev_err(dev, "%s: Invalid target frequency %lu\n", __func__, + target_freq); + return -EINVAL; + } + } + clk = opp_table->clk; if (IS_ERR(clk)) { dev_err(dev, "%s: No clock available for the device\n", From patchwork Wed Mar 20 09:49:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861207 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB80A17E0 for ; Wed, 20 Mar 2019 09:50:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A982328780 for ; Wed, 20 Mar 2019 09:50:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9DB4629A87; Wed, 20 Mar 2019 09:50:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4221828780 for ; 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Wed, 20 Mar 2019 09:49:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1553075387; bh=IV7tUmqAOcOybIWc52/kxVT+D89R6Hy8mjlfXdDcBx8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N4ewvYYjEq5SNt+QfxgbKWj219wZqEDViPQ9LMDO/hZlHAvM+pvDYpY+l2nRbmi5c jzuMDcKVEWgdd2KKw4Ep6E5Panyjj2VD7jv56/XP4idM+KULM+NR1Jszo8lk/9JzYR m8TNGt9bBmU1pfvYHbpFSohjpmArUWdVO2sOlysk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9F21360FEA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 03/11] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Date: Wed, 20 Mar 2019 15:19:10 +0530 Message-Id: <20190320094918.20234-4-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP geni serial needs to express a perforamnce state requirement on CX depending on the frequency of the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak Signed-off-by: Stephen Boyd --- drivers/tty/serial/qcom_geni_serial.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 3bcec1c20219..422852911141 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -115,6 +116,7 @@ struct qcom_geni_serial_port { bool brk; unsigned int tx_remaining; + struct device *dev; }; static const struct uart_ops qcom_geni_console_pops; @@ -961,7 +963,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, goto out_restart_rx; uport->uartclk = clk_rate; - clk_set_rate(port->se.clk, clk_rate); + dev_pm_opp_set_rate(port->dev, clk_rate); ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; @@ -1198,8 +1200,10 @@ static void qcom_geni_serial_pm(struct uart_port *uport, if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) geni_se_resources_on(&port->se); else if (new_state == UART_PM_STATE_OFF && - old_state == UART_PM_STATE_ON) + old_state == UART_PM_STATE_ON) { + dev_pm_opp_set_rate(port->dev, 0); geni_se_resources_off(&port->se); + } } static const struct uart_ops qcom_geni_console_pops = { @@ -1265,6 +1269,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Invalid line %d\n", line); return PTR_ERR(port); } + port->dev = &pdev->dev; uport = &port->uport; /* Don't allow 2 drivers to access the same port */ @@ -1286,6 +1291,12 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return -EINVAL; uport->mapbase = res->start; + ret = dev_pm_opp_of_add_table(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to init OPP table: %d\n", ret); + return ret; + } + port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; From patchwork Wed Mar 20 09:49:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861203 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DEBF117E0 for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KMch30hUliwKuV4UflNp832h+jG5WfiZw127EZi/2uDOePetJiwVvkDThSuFZqoS9 Misl5nL1vVBi0LRJ7E7fZqeptUVLvZgOqqWNsJSXJlJJtPC8uZxZRpWZGPjdNvISrJ /NFMkouris2qEKig+CJFuBTsQm1wjhzIy/sP24vA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org AC0BF61155 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 04/11] spi: spi-geni-qcom: Use OPP API to set clk/perf state Date: Wed, 20 Mar 2019 15:19:11 +0530 Message-Id: <20190320094918.20234-5-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP geni spi needs to express a perforamnce state requirement on CX depending on the frequency of the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak Signed-off-by: Stephen Boyd --- drivers/spi/spi-geni-qcom.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 5f0b0d5bfef4..c251e6df1bc0 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -96,7 +97,6 @@ static int get_spi_clk_cfg(unsigned int speed_hz, { unsigned long sclk_freq; unsigned int actual_hz; - struct geni_se *se = &mas->se; int ret; ret = geni_se_clk_freq_match(&mas->se, @@ -113,9 +113,9 @@ static int get_spi_clk_cfg(unsigned int speed_hz, dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, actual_hz, sclk_freq, *clk_idx, *clk_div); - ret = clk_set_rate(se->clk, sclk_freq); + ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); if (ret) - dev_err(mas->dev, "clk_set_rate failed %d\n", ret); + dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); return ret; } @@ -560,6 +560,12 @@ static int spi_geni_probe(struct platform_device *pdev) if (!spi) return -ENOMEM; + ret = dev_pm_opp_of_add_table(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to init OPP table: %d\n", ret); + return ret; + } + platform_set_drvdata(pdev, spi); mas = spi_master_get_devdata(spi); mas->irq = irq; @@ -625,6 +631,8 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) struct spi_master *spi = dev_get_drvdata(dev); struct spi_geni_master *mas = spi_master_get_devdata(spi); + /* Drop the performance state vote */ + dev_pm_opp_set_rate(dev, 0); return geni_se_resources_off(&mas->se); } From patchwork Wed Mar 20 09:49:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861193 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04F0E1575 for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O4DZmksQuyr/L5fNI154eDOGC6kLocTBNFNXl7a3aVkr7f34k76q7NWxc3SqHBvsD 5jueceYjHBM7LIcXJvt1/mu5sBU1vYCe0n+KKA1xCNXK2Hw4pCqcUfRrnA2GuBT411 wH4NVMopdv+aGi/EpnTyQ6qCCQ+jiP6dH+FKLw3U= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B762E61197 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 05/11] arm64: dts: sdm845: Add OPP table for all qup devices Date: Wed, 20 Mar 2019 15:19:12 +0530 Message-Id: <20190320094918.20234-6-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP qup has a requirement to vote on the performance state of the CX domain in sdm845 devices. Add OPP tables for these and also add power-domains property for all qup instances. Signed-off-by: Rajendra Nayak Signed-off-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 115 +++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e4b69c74fe07..027ffe6e93e8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -409,6 +409,25 @@ clock-names = "core"; }; + qup_opp_table: qup-opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x6000>; @@ -430,6 +449,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -443,6 +464,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -454,6 +477,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart0_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -467,6 +492,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -480,6 +507,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -491,6 +520,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart1_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -504,6 +535,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -517,6 +550,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -528,6 +563,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -541,6 +578,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -554,6 +593,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -565,6 +606,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -578,6 +621,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -591,6 +636,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -602,6 +649,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart4_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -615,6 +664,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -628,6 +679,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -639,6 +692,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart5_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -652,6 +707,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -665,6 +722,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -676,6 +735,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -689,6 +750,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -702,6 +765,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -713,6 +778,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; @@ -738,6 +805,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -751,6 +820,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -762,6 +833,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart8_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -775,6 +848,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -788,6 +863,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -799,6 +876,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart9_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -812,6 +891,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -825,6 +906,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -836,6 +919,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart10_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -849,6 +934,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -862,6 +949,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -873,6 +962,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart11_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -886,6 +977,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -899,6 +992,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -910,6 +1005,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart12_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -923,6 +1020,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -936,6 +1035,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -947,6 +1048,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart13_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -960,6 +1063,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -973,6 +1078,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -984,6 +1091,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart14_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -997,6 +1106,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1010,6 +1121,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1021,6 +1134,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart15_default>; interrupts = ; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; From patchwork Wed Mar 20 09:49:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861143 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5972A1708 for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Na9n01Ied7Ip0EVp98ZckL0Hy43nQJ6lo/UvC1uSVAmWg+jdtE69C53+FEP/QAzGK NnfESvLHC1nVF6gs2BOnbXL7m2YRGAOaJdN8W8y+O7nB0Cr1KNUpbRTIVLHrHKnytE B/EVV4yJsbkl1c8rgo+bvhVunKEnbOGZjnqbiu7o= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C6511611BE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 06/11] scsi: ufs: Add support to manage multiple power domains in ufshcd-pltfrm Date: Wed, 20 Mar 2019 15:19:13 +0530 Message-Id: <20190320094918.20234-7-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some UFS devices need to manage multiple powerdomains. Add support for it as part of the ufshcd-pltfrm driver. Signed-off-by: Rajendra Nayak --- drivers/scsi/ufs/ufshcd-pltfrm.c | 52 +++++++++++++++++++++++++++++++- drivers/scsi/ufs/ufshcd.h | 3 ++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c index 238a79f21e74..ce33eb8b7510 100644 --- a/drivers/scsi/ufs/ufshcd-pltfrm.c +++ b/drivers/scsi/ufs/ufshcd-pltfrm.c @@ -34,6 +34,7 @@ */ #include +#include #include #include @@ -289,6 +290,43 @@ static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba) } } +static int ufshcd_attach_pds(struct device *dev, struct ufs_hba *hba, int num_pds) +{ + int i, ret; + + hba->virt_devs = devm_kzalloc(dev, sizeof(struct device *) * num_pds, + GFP_KERNEL); + if (!hba->virt_devs) + return -ENOMEM; + + hba->num_virt_devs = num_pds; + for (i = 0; i < num_pds; i++) { + hba->virt_devs[i] = dev_pm_domain_attach_by_id(dev, i); + if (IS_ERR(hba->virt_devs[i])) { + ret = PTR_ERR(hba->virt_devs[i]); + goto unroll_attach; + } + device_link_add(dev,hba->virt_devs[i], DL_FLAG_RPM_ACTIVE | + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); + } + + return ret; + +unroll_attach: + for (i--; i >= 0; i--) + dev_pm_domain_detach(hba->virt_devs[i], false); + + return ret; +} + +static void ufshcd_detach_pds(struct ufs_hba *hba) +{ + int i; + + for (i = 0; i < hba->num_virt_devs; i++) + dev_pm_domain_detach(hba->virt_devs[i], false); +} + /** * ufshcd_pltfrm_init - probe routine of the driver * @pdev: pointer to Platform device handle @@ -302,7 +340,7 @@ int ufshcd_pltfrm_init(struct platform_device *pdev, struct ufs_hba *hba; void __iomem *mmio_base; struct resource *mem_res; - int irq, err; + int irq, err, num_pds; struct device *dev = &pdev->dev; mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -340,6 +378,16 @@ int ufshcd_pltfrm_init(struct platform_device *pdev, goto dealloc_host; } + num_pds = of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + if (num_pds > 1) { + err = ufshcd_attach_pds(&pdev->dev, hba, num_pds); + if (err) { + dev_err(&pdev->dev, "%s: attach of power domains failed %d\n", + __func__, err); + goto dealloc_host; + } + } pm_runtime_get_noresume(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); @@ -358,6 +406,8 @@ int ufshcd_pltfrm_init(struct platform_device *pdev, return 0; out_disable_rpm: + if (num_pds > 1) + ufshcd_detach_pds(hba); pm_runtime_disable(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); pm_runtime_put_noidle(&pdev->dev); diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index ecfa898b9ccc..bca1e008f506 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -517,6 +517,9 @@ struct ufs_hba { struct Scsi_Host *host; struct device *dev; + struct device **virt_devs; + u8 num_virt_devs; + /* * This field is to keep a reference to "scsi_device" corresponding to * "UFS device" W-LU. From patchwork Wed Mar 20 09:49:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861187 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E64D317E0 for ; Wed, 20 Mar 2019 09:50:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D430A29AB0 for ; Wed, 20 Mar 2019 09:50:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C7D3629A2F; Wed, 20 Mar 2019 09:50:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7479329AB0 for ; Wed, 20 Mar 2019 09:50:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727756AbfCTJuI (ORCPT ); Wed, 20 Mar 2019 05:50:08 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:51064 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727694AbfCTJuI (ORCPT ); Wed, 20 Mar 2019 05:50:08 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 526B4613A3; Wed, 20 Mar 2019 09:50:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1553075406; bh=MJQt3iSoG7Hb5v8EXTLAvfULjqQjr1k8J9tx/gTgULw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Nm92Gdpm1fHv5U/7r6mKwW8HQ8Xqm2TBGh+EJ6bbk+hze9YafBoPCIUNkYLsSXGDY kNU2Sn4NuvHQ+9aZwdoawHyKvie4OqoNRuG8QENYcDAAuuteD7XkQOHLrM3gowEVYd 6EXAEgd2lKmvdVOo4kkk7TexypYFxDZznnXUWxL8= Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4F8CA61340; Wed, 20 Mar 2019 09:50:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1553075404; bh=MJQt3iSoG7Hb5v8EXTLAvfULjqQjr1k8J9tx/gTgULw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YeSyNfwEUlfv7n6eWpm60/VqPdycTGpUtAcitQX+BOnl3+mI8NXU3b4iekkn5q7HQ t0Nm2IqT0SAMPv6Iaz/TU4DLK3wTXNz+wNOl0Ta0F/bNhA8UsjmfgW3vzL/C6cZuja miH1EAx8MHkcdr1kv5PEwL84/ZB6BBYRUXo2nzrE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4F8CA61340 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 07/11] scsi: ufs: Add support for specifying OPP tables in DT Date: Wed, 20 Mar 2019 15:19:14 +0530 Message-Id: <20190320094918.20234-8-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some platforms like qualcomms sdm845 SoC have a need to set a performance state of a power domain for UFS along with setting the clock rate. Add support for passing this freq/perf state tuple from DT as an OPP table. Modify the driver to read the OPP table and register with OPP layer. Signed-off-by: Rajendra Nayak --- drivers/scsi/ufs/ufshcd.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index ffa9e58680b4..2b260e83874a 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -913,6 +913,16 @@ static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up) if (ret) return ret; + if (hba->virt_devs) { + struct dev_pm_opp *opp; + unsigned long freq = scale_up ? INT_MAX: 0; + if (scale_up) + opp = dev_pm_opp_find_freq_floor(hba->dev, &freq); + else + opp = dev_pm_opp_find_freq_ceil(hba->dev, &freq); + dev_pm_opp_set_rate(hba->dev, dev_pm_opp_get_freq(opp)); + } + list_for_each_entry(clki, head, list) { if (!IS_ERR_OR_NULL(clki->clk)) { if (scale_up && clki->max_freq) { @@ -1318,6 +1328,7 @@ static int ufshcd_devfreq_init(struct ufs_hba *hba) struct list_head *clk_list = &hba->clk_list_head; struct ufs_clk_info *clki; struct devfreq *devfreq; + struct device *virt_dev; int ret; /* Skip devfreq if we don't have any clocks in the list */ @@ -1325,8 +1336,14 @@ static int ufshcd_devfreq_init(struct ufs_hba *hba) return 0; clki = list_first_entry(clk_list, struct ufs_clk_info, list); - dev_pm_opp_add(hba->dev, clki->min_freq, 0); - dev_pm_opp_add(hba->dev, clki->max_freq, 0); + + if (dev_pm_opp_of_add_table(hba->dev)) { + dev_pm_opp_add(hba->dev, clki->min_freq, 0); + dev_pm_opp_add(hba->dev, clki->max_freq, 0); + } else { + virt_dev = hba->virt_devs[hba->num_virt_devs -1]; + dev_pm_opp_set_genpd_virt_dev(hba->dev, virt_dev, 0); + } devfreq = devfreq_add_device(hba->dev, &ufs_devfreq_profile, From patchwork Wed Mar 20 09:49:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861165 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F05281823 for ; Wed, 20 Mar 2019 09:50:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD16F29AB0 for ; Wed, 20 Mar 2019 09:50:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D1B3829A9D; Wed, 20 Mar 2019 09:50:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 697CE29A3C for ; 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Wed, 20 Mar 2019 09:50:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1553075408; bh=7aydc5AQ+/xKBttzzkD8dHxaZRt09wA65scQVcjJiQ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T7uP6b425b7x+UFr96hEXxfUbJryY+3nlGdqfKci2zT4kiT8dgZ56vk2N3hsZPSIB IAMIMsdgVJDZrBWDURpOZb7za6XIEWl3e0KchtlmObcS7auPE2mxFrKv0h1otO2fSf uh0wD094d+KqihKc60dJnio8SMgsljY/4ocDa4VA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D3D3960F3E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 08/11] arm64: dts: sdm845: Add ufs opps and power-domains Date: Wed, 20 Mar 2019 15:19:15 +0530 Message-Id: <20190320094918.20234-9-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the additional power domain and the OPP table for ufs on sdm845 so the driver can set the appropriate performance state of the power domain while setting the clock rate. Signed-off-by: Rajendra Nayak --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 027ffe6e93e8..a3af4a1757b4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1140,6 +1140,21 @@ }; }; + ufs_opp_table: ufs-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_nom>; + + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -1148,7 +1163,7 @@ phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; lanes-per-direction = <2>; - power-domains = <&gcc UFS_PHY_GDSC>; + power-domains = <&gcc UFS_PHY_GDSC>, <&rpmhpd SDM845_CX>; iommus = <&apps_smmu 0x100 0xf>; @@ -1170,6 +1185,9 @@ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + + operating-points-v2 = <&ufs_opp_table>; + freq-table-hz = <50000000 200000000>, <0 0>, From patchwork Wed Mar 20 09:49:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861153 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B635418EC for ; Wed, 20 Mar 2019 09:50:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A036A29AFE for ; Wed, 20 Mar 2019 09:50:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9428629B05; Wed, 20 Mar 2019 09:50:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 90A3E29AFE for ; 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Wed, 20 Mar 2019 09:50:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1553075413; bh=vE4lNkXde4s9Lm5OFadg0y4mx23Es0CYK64WiLr/7g4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O+Wd36r+fgMWjg6mHIFPwMi8wL4Y9F6LPyEUukwDiSvgFFLFWolFhfGbSu4BsdU9B w9gsYMWvkb5alCJhKxkn3buxIoJW1bbQAFzCYxaaVD7edDPRwlzAmLr3miZbpFRkXT 5SpaiMTCnDXgrv8lxhVdllkWu7FW11jP/GKrJUfU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 463F16141B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 09/11] drm/msm/dpu: Use OPP API to set clk/perf state Date: Wed, 20 Mar 2019 15:19:16 +0530 Message-Id: <20190320094918.20234-10-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On some qualcomm platforms DPU needs to express a perforamnce state requirement on a power domain depennding on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 7 ++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 9 +++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 9f20f397f77d..db21a86b242b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -298,7 +299,11 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate) rate = core_clk->max_rate; core_clk->rate = rate; - return msm_dss_clk_set_rate(core_clk, 1); + + if (dev_pm_opp_get_opp_table(&kms->pdev->dev)) + return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate); + else + return msm_dss_clk_set_rate(core_clk, 1); } static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 885bf88afa3e..684bd6982aaf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "msm_drv.h" #include "msm_mmu.h" @@ -1014,6 +1015,12 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) if (!dpu_kms) return -ENOMEM; + dev_pm_opp_set_clkname(dev, "core"); + + ret = dev_pm_opp_of_add_table(dev); + if (ret) + dev_err(dev, "failed to init OPP table: %d\n", ret); + mp = &dpu_kms->mp; ret = msm_dss_parse_clock(pdev, mp); if (ret) { @@ -1040,6 +1047,7 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data) struct dpu_kms *dpu_kms = platform_get_drvdata(pdev); struct dss_module_power *mp = &dpu_kms->mp; + dev_pm_opp_of_remove_table(dev); msm_dss_put_clk(mp->clk_config, mp->num_clk); devm_kfree(&pdev->dev, mp->clk_config); mp->num_clk = 0; @@ -1078,6 +1086,7 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev) return rc; } + dev_pm_opp_set_rate(dev, 0); rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); if (rc) DPU_ERROR("clock disable failed rc:%d\n", rc); From patchwork Wed Mar 20 09:49:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861183 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3750317E0 for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c02nylt+scrxcb3PU35/ROd2TY23MEakDhJvIZ3cC0OgMenW/gVibmur+yR/aKvlM o9r5GibJkQ8Nla6mvJsSYoXw8IoSOCrI+M4uKTnD7HWW8qxb+LTmOm0ZcM+x/EqCbT 85SMwPbM2Z1/DkXkjh0NvQ4kaLJ3Gb0OdUy+06tQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C25606141D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 10/11] drm/msm: dsi: Use OPP API to set clk/perf state Date: Wed, 20 Mar 2019 15:19:17 +0530 Message-Id: <20190320094918.20234-11-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On SDM845 DSI needs to express a perforamnce state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak --- drivers/gpu/drm/msm/dsi/dsi.h | 2 + drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +- drivers/gpu/drm/msm/dsi/dsi_host.c | 88 +++++++++++++++++++++++++++--- 3 files changed, 84 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 9c6b31c2d79f..b4398a798370 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -188,8 +188,10 @@ int msm_dsi_runtime_suspend(struct device *dev); int msm_dsi_runtime_resume(struct device *dev); int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host); +int dsi_link_clk_enable_6g_v2(struct msm_dsi_host *msm_host); void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host); void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host); +void dsi_link_clk_disable_6g_v2(struct msm_dsi_host *msm_host); int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size); int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size); void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index dcdfb1bb54f9..c18532f92e4a 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -159,8 +159,8 @@ const static struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = { }; const static struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = { - .link_clk_enable = dsi_link_clk_enable_6g, - .link_clk_disable = dsi_link_clk_disable_6g, + .link_clk_enable = dsi_link_clk_enable_6g_v2, + .link_clk_disable = dsi_link_clk_disable_6g_v2, .clk_init_ver = dsi_clk_init_6g_v2, .tx_buf_alloc = dsi_tx_buf_alloc_6g, .tx_buf_get = dsi_tx_buf_get_6g, diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 610183db1daf..6ed9e6a0520c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -511,7 +512,7 @@ int msm_dsi_runtime_resume(struct device *dev) return dsi_bus_clk_enable(msm_host); } -int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) +static int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) { int ret; @@ -521,29 +522,65 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); if (ret) { pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); - goto error; + return ret; } ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); if (ret) { pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); - goto error; + return ret; } if (msm_host->byte_intf_clk) { ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_clk_rate / 2); - if (ret) { + if (ret) + pr_err("%s: Failed to set rate byte intf clk, %d\n", + __func__, ret); + } + + return ret; +} + +static int dsi_link_clk_set_rate_6g_v2(struct msm_dsi_host *msm_host) +{ + int ret; + struct device *dev = &msm_host->pdev->dev; + + DBG("Set clk rates: pclk=%d, byteclk=%d", + msm_host->mode->clock, msm_host->byte_clk_rate); + + ret = dev_pm_opp_set_rate(dev, msm_host->byte_clk_rate); + if (ret) { + pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); + return ret; + } + + ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); + if (ret) { + pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); + return ret; + } + + if (msm_host->byte_intf_clk) { + ret = clk_set_rate(msm_host->byte_intf_clk, + msm_host->byte_clk_rate / 2); + if (ret) pr_err("%s: Failed to set rate byte intf clk, %d\n", __func__, ret); - goto error; - } } + return ret; +} + +static int dsi_link_clk_prepare_enable_6g(struct msm_dsi_host *msm_host) +{ + int ret; + ret = clk_prepare_enable(msm_host->esc_clk); if (ret) { pr_err("%s: Failed to enable dsi esc clk\n", __func__); - goto error; + return ret; } ret = clk_prepare_enable(msm_host->byte_clk); @@ -575,10 +612,31 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->byte_clk); byte_clk_err: clk_disable_unprepare(msm_host->esc_clk); -error: return ret; } +int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) +{ + int ret; + + ret = dsi_link_clk_set_rate_6g(msm_host); + if (ret) + return ret; + + return dsi_link_clk_prepare_enable_6g(msm_host); +} + +int dsi_link_clk_enable_6g_v2(struct msm_dsi_host *msm_host) +{ + int ret; + + ret = dsi_link_clk_set_rate_6g_v2(msm_host); + if (ret) + return ret; + + return dsi_link_clk_prepare_enable_6g(msm_host); +} + int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) { int ret; @@ -656,6 +714,13 @@ void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->byte_clk); } +void dsi_link_clk_disable_6g_v2(struct msm_dsi_host *msm_host) +{ + /* Drop the performance state vote */ + dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); + dsi_link_clk_disable_6g(msm_host); +} + void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) { clk_disable_unprepare(msm_host->pixel_clk); @@ -1864,6 +1929,12 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) goto fail; } + dev_pm_opp_set_clkname(&pdev->dev, "byte"); + + ret = dev_pm_opp_of_add_table(&pdev->dev); + if (ret < 0) + dev_err(&pdev->dev, "failed to init OPP table: %d\n", ret); + msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); if (!msm_host->rx_buf) { ret = -ENOMEM; @@ -1896,6 +1967,7 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host) struct msm_dsi_host *msm_host = to_msm_dsi_host(host); DBG(""); + dev_pm_opp_of_remove_table(&msm_host->pdev->dev); dsi_tx_buf_free(msm_host); if (msm_host->workqueue) { flush_workqueue(msm_host->workqueue); From patchwork Wed Mar 20 09:49:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10861171 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0B34139A for ; Wed, 20 Mar 2019 09:50:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7ED2429AFE for ; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, viresh.kumar@linaro.org, dianders@chromium.org, rafael@kernel.org, Rajendra Nayak Subject: [RFC v2 11/11] arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains Date: Wed, 20 Mar 2019 15:19:18 +0530 Message-Id: <20190320094918.20234-12-rnayak@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org> References: <20190320094918.20234-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the OPP tables for DSI and MDP based on the perf state/clk requirements, and add the power-domains property to specify the scalable power domain. Signed-off-by: Rajendra Nayak --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index a3af4a1757b4..675954fde391 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1857,6 +1857,59 @@ #reset-cells = <1>; }; + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-344000000 { + opp-hz = /bits/ 64 <344000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-328580000 { + opp-hz = /bits/ 64 <328580000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + mdss: mdss@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; @@ -1901,6 +1954,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; assigned-clock-rates = <300000000>, <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; interrupt-parent = <&mdss>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; @@ -1947,6 +2002,8 @@ "core", "iface", "bus"; + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; phys = <&dsi0_phy>; phy-names = "dsi"; @@ -2013,6 +2070,8 @@ "core", "iface", "bus"; + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; phys = <&dsi1_phy>; phy-names = "dsi";