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Sun, 9 Mar 2025 11:41:58 -0700 From: Tariq Toukan To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan CC: Gal Pressman , Mark Bloch , "Moshe Shemesh" , , , , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Cosmin Ratiu , Leon Romanovsky , Yael Chemla Subject: [PATCH mlx5-next] net/mlx5: Add IFC bits for PPCNT recovery counters group Date: Sun, 9 Mar 2025 20:41:37 +0200 Message-ID: <1741545697-23041-1-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000018:EE_|DS5PPFBB8C78349:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fb8061e-893c-4057-4f5e-08dd5f3a1920 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: GOejs5ABq00PlVNCuIwjiMvfYfkEOsYDDa773ZXDosrayUYOxoph3+kUfDClx3IKNLOFY0L+8uwf+CB9ac8pHcRaQaEUGHlx8yOWwiEi1KRwkjvPx093J/mll0gjS0h+Z50afLVTrQ5o91DrYUDXnkuCKk4PgFRf3LIZiJCZFwfKhKsX7O7UOR59NBovvtgqP5adsuTccpTqom/5G7tWrsP2S9UnSrjSovhp1sXgy3gzT5YQejuO0WnRMXUg9qdr7CzvQgmvwT0Ru8fHZN/pZGXd7p0r7Ckk0SumrGRhzYEmpj4kItHqVKnDizOxwfe2XvPXT8e+nrUtsKZIfgqkVoBx/kgjLFz2kT1ApR2Ze7Xki/WtrutefJUvkRdldunIv2QkmP+7dwEsBtTOmrG7Oh1bopO91/tGZodQ7pQdhVyr0HyR0bueqeBXRnckhkO7alr/PDBfmMxZEjnLrmiwgCIjUM2tExp8NPZ5roikoJnYDxwh8kAS3kT53SCaktWzihH3zmqpVW9nFX2540Iy0t/Fozh5WB/YgrfL3xCKRj02E5mKd8GH6A/mfkRs4EA5SgX8yBicWITafToWL96bGlsI+aYPkO2e9gM955y9NIUVf8eSCntA5jLa1eqV97+tX4ytVXlNyVBSZt5/5ny6Cpwt1icKTcCnE3WQRuKuiHr4vqsLbDqTVCjjZmtSYfu3A2SBlJIeBcNELl3Ypl8a59t9O9yB6GSaYkrIi8YNrCUTs9uQxOVhIuOwzC7hqgvkhBKknfh/hyQXAzuwwO/nm8L1zhzBsCAQwS4FuVNffSehBi/xLcQWMjqJCASLC9eKW+Wnpiny9ah7drCi8pXxpCcwr76st3HtICnIBYiu/H4v6dUQpc0g1bM+n42Z5Wu7J6YNnyXdmMK88fBaNfE1JilXn6gSlwqUXvsibiXlAdKVRF5S3B+Q6/bqLAZSXBl59hMw3SdeUkDTZ1dzm/xUrW+5IUHwLKMtaSIF7WYYfGmPxuW3Vn9EhrqAuPM9z5E9o90lGx50Ywu4W09eaz+xmXqFxF8NuiRqf6+VLrGXmqYFcjpqV4XmJ25ncLqDSVoDazG4/kUFwowbiqydeRcgynN6+RWZnEgA7gLsNg+8vD8m3ZinNvOtBFIqjTRB4zJDFUlWSt0i5CX8okgCXIR+gAodXDFBTdclApl6ec7bZ5jOHuqcZ3dcEhT0KHiKzG+wJrh1V3dvonSa7RxZmluULslkMZdLElzEQB3pHBkUu4ptBMe0iJlrZgFnpUmrqv52DbZp5+s7qyLlg6yneEEzb1jrSsH72yPabzbn2WyZ8czfW5q3atXF79WKnBS8OGwSNc8lFn0FN9SjWaVvm98FbTuFrmq2tONa4dl55mE4g7R+OBsCuP24xhA1KtTFRzMXc5zaVrFHt6pRf6dY8emQgS3ky9w0lyyVxoSARoedIV1FulSIQ0XSKUK1Brh23HkZxt4pQEWwNMVa1qJ/s5jFHRabfmy2Y9KhUMa/s9vUdu4= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2025 18:42:08.9518 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fb8061e-893c-4057-4f5e-08dd5f3a1920 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000018.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPFBB8C78349 From: Yael Chemla Add recovery counters group layout of PPCNT (Ports Performance Counters Register). This group counts recovery events per link. Also add the corresponding bit in PCAM to indicate this group is supported. Signed-off-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- include/linux/mlx5/device.h | 1 + include/linux/mlx5/mlx5_ifc.h | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) base-commit: 15b103df80b25025040faa8f35164c2595977bdb diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 8fe56d0362c6..904804e995aa 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1517,6 +1517,7 @@ enum { MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, + MLX5_PHYSICAL_LAYER_RECOVERY_GROUP = 0x1a, MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP = 0x21, }; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index fea8af42f954..2c09df4ee574 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -2645,6 +2645,12 @@ struct mlx5_ifc_field_select_802_1qau_rp_bits { u8 field_select_8021qaurp[0x20]; }; +struct mlx5_ifc_phys_layer_recovery_cntrs_bits { + u8 total_successful_recovery_events[0x20]; + + u8 reserved_at_20[0x7a0]; +}; + struct mlx5_ifc_phys_layer_cntrs_bits { u8 time_since_last_clear_high[0x20]; @@ -4846,6 +4852,7 @@ union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; + struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; u8 reserved_at_0[0x7c0]; }; @@ -10584,7 +10591,9 @@ struct mlx5_ifc_mtutc_reg_bits { }; struct mlx5_ifc_pcam_enhanced_features_bits { - u8 reserved_at_0[0x1d]; + u8 reserved_at_0[0x10]; + u8 ppcnt_recovery_counters[0x1]; + u8 reserved_at_11[0xc]; u8 fec_200G_per_lane_in_pplm[0x1]; u8 reserved_at_1e[0x2a]; u8 fec_100G_per_lane_in_pplm[0x1];