From patchwork Mon Mar 10 19:59:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ariel D'Alessandro X-Patchwork-Id: 14010583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7949AC28B30 for ; Mon, 10 Mar 2025 20:00:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D98FA10E2B6; Mon, 10 Mar 2025 20:00:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b="XI445Uks"; dkim-atps=neutral Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C9FF10E2B6 for ; Mon, 10 Mar 2025 20:00:11 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; t=1741636795; cv=none; d=zohomail.com; s=zohoarc; b=dTbDcDa5VbZ+n/fO3/EG23vIfbAUbjH25Kvi/6G6UUkf9B43GNk7v0B7XujY+vgRKc3ULX22Xv3G4igq7lXUoOo/WQurSmKjK3HqG6bV+YDybro145U301lWUoF7vXQeAvx2aiZvFlAHswL8uk0nZO+XBJlTBQNCkkKvLNutkgw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741636795; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=zCHAjF0Z7uci82elReH6b009mfaaTOtclxm2AxNJYSk=; b=Zor3RI1wzM02pifNC+UKbVhP3LMu419DTQ6JeJaQXGI5c4XaYrBC2B0SdsNGfsgCc9DWhMS20zCfTKuJjtATdDv3exkFIJFd3q9Oc1gPKBLQOgPlYFUqAGEowUm8IT8x/gHOSohvzqJXBFjhlgnfa1tPcqB5XElnEQPPwu38eRo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=ariel.dalessandro@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1741636795; s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=zCHAjF0Z7uci82elReH6b009mfaaTOtclxm2AxNJYSk=; b=XI445Uks/5ycTftE+M/lmMubk4qJ8c0Uwss88U2YMIF6ZD4lb49GiMzzbHjg7q8R BfE3kRH59JTzpaClDZF2aD5Nt9r2z2fDIv7Nxje+yCiBZlZwIurfowMnOcwedYI8EQ7 8Y7qkXZXIlQThT8OIqSbQU4Jp4371e6FP0p7cY3s= Received: by mx.zohomail.com with SMTPS id 1741636791693559.3943284745002; Mon, 10 Mar 2025 12:59:51 -0700 (PDT) From: Ariel D'Alessandro To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: boris.brezillon@collabora.com, robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com, Ariel D'Alessandro Subject: [PATCH v1 1/6] drm/panfrost: Set IOMMU_CACHE flag Date: Mon, 10 Mar 2025 16:59:16 -0300 Message-ID: <20250310195921.157511-2-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250310195921.157511-1-ariel.dalessandro@collabora.com> References: <20250310195921.157511-1-ariel.dalessandro@collabora.com> MIME-Version: 1.0 X-ZohoMailClient: External X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Panfrost does not support uncached mappings, so flag them properly. Also flag the pages that are mapped as response to a page fault as cached. Signed-off-by: Boris Brezillon Signed-off-by: Ariel D'Alessandro Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_mmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index b91019cd5acb1..9e6f198ef5c1b 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -327,7 +327,7 @@ int panfrost_mmu_map(struct panfrost_gem_mapping *mapping) struct drm_gem_object *obj = &shmem->base; struct panfrost_device *pfdev = to_panfrost_device(obj->dev); struct sg_table *sgt; - int prot = IOMMU_READ | IOMMU_WRITE; + int prot = IOMMU_READ | IOMMU_WRITE | IOMMU_CACHE; if (WARN_ON(mapping->active)) return 0; @@ -528,7 +528,7 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, goto err_map; mmu_map_sg(pfdev, bomapping->mmu, addr, - IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt); + IOMMU_WRITE | IOMMU_READ | IOMMU_CACHE | IOMMU_NOEXEC, sgt); bomapping->active = true; bo->heap_rss_size += SZ_2M; From patchwork Mon Mar 10 19:59:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ariel D'Alessandro X-Patchwork-Id: 14010584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9D77C282DE for ; Mon, 10 Mar 2025 20:00:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24E5E10E4D1; Mon, 10 Mar 2025 20:00:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b="N7KRso9X"; dkim-atps=neutral Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0BEF010E4D1 for ; Mon, 10 Mar 2025 20:00:15 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; t=1741636801; cv=none; d=zohomail.com; s=zohoarc; b=LXjc8Zt46R7A38mKRWL4qBI4rBU0978hFZBjxjFGvg7bc6WhSrUZ/SKnMItwoGRsZlQ4L2MwdHGEMOorDX46nXWQTOw/vlnF86YIuCGL01woP84gFepKrnnoCuOr5XzNUp2YljNzdaMrCyNlG+1iXsYlayxlWXG+To0jMlZZ/YM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741636801; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=QlTpBVrKFp8ajXuiOKOxz/qINTtZfJYc0IqswtnjYwY=; b=WEuJOhn0MaH7zRFkzcjjv6Ns/fycIvr7KERJAaoN3r2l9YHcZzz7ZJP73k649hzJkNncH9oeM5N3Brh5CO5JgBqg8X1Al/a/nkomoPVONHEaVEZjNbGgwtpN/1WCgdZYEMrk+lFpuRt2AvQpD4MZnzVkLxS2m7RVx98hiEcdB38= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=ariel.dalessandro@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1741636801; s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=QlTpBVrKFp8ajXuiOKOxz/qINTtZfJYc0IqswtnjYwY=; b=N7KRso9XInL5q2GYtL7ka4H6m+T/tNvZ8N6u3ZCP8Qgfckv4H4e8aRV3n6n7UogC lNQsZ7k8VRc9H+YVE1r+hcdBUSg3ig9438/bvCbpCxDY5ODHhRAhT4D4Jqboh6n+W2q S6Ts6xCyWujR4v75z/1k3cXEucYj3vH5yI8wKr48= Received: by mx.zohomail.com with SMTPS id 1741636799309149.4467471604056; Mon, 10 Mar 2025 12:59:59 -0700 (PDT) From: Ariel D'Alessandro To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: boris.brezillon@collabora.com, robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com, Ariel D'Alessandro Subject: [PATCH v1 2/6] drm/panfrost: Use GPU_MMU_FEATURES_VA_BITS/PA_BITS macros Date: Mon, 10 Mar 2025 16:59:17 -0300 Message-ID: <20250310195921.157511-3-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250310195921.157511-1-ariel.dalessandro@collabora.com> References: <20250310195921.157511-1-ariel.dalessandro@collabora.com> MIME-Version: 1.0 X-ZohoMailClient: External X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" As done in panthor, define and use these GPU_MMU_FEATURES_* macros, which makes code easier to read and reuse. Signed-off-by: Ariel D'Alessandro Reviewed-by: Boris Brezillon Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_mmu.c | 6 ++++-- drivers/gpu/drm/panfrost/panfrost_regs.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index 9e6f198ef5c1b..294f86b3c25e7 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -615,6 +615,8 @@ static void panfrost_drm_mm_color_adjust(const struct drm_mm_node *node, struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev) { + u32 va_bits = GPU_MMU_FEATURES_VA_BITS(pfdev->features.mmu_features); + u32 pa_bits = GPU_MMU_FEATURES_PA_BITS(pfdev->features.mmu_features); struct panfrost_mmu *mmu; mmu = kzalloc(sizeof(*mmu), GFP_KERNEL); @@ -633,8 +635,8 @@ struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev) mmu->pgtbl_cfg = (struct io_pgtable_cfg) { .pgsize_bitmap = SZ_4K | SZ_2M, - .ias = FIELD_GET(0xff, pfdev->features.mmu_features), - .oas = FIELD_GET(0xff00, pfdev->features.mmu_features), + .ias = va_bits, + .oas = pa_bits, .coherent_walk = pfdev->coherent, .tlb = &mmu_tlb_ops, .iommu_dev = pfdev->dev, diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/panfrost/panfrost_regs.h index c7bba476ab3f3..b5f279a19a084 100644 --- a/drivers/gpu/drm/panfrost/panfrost_regs.h +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h @@ -16,6 +16,8 @@ #define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */ #define GPU_MMU_FEATURES 0x014 /* (RO) MMU features */ +#define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0)) +#define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0)) #define GPU_AS_PRESENT 0x018 /* (RO) Address space slots present */ #define GPU_JS_PRESENT 0x01C /* (RO) Job slots present */ From patchwork Mon Mar 10 19:59:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ariel D'Alessandro X-Patchwork-Id: 14010585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B95EC282DE for ; Mon, 10 Mar 2025 20:00:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE31A10E4D9; Mon, 10 Mar 2025 20:00:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b="TKCbmJJX"; dkim-atps=neutral Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD80810E4D9 for ; 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s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=2zhv36KL2NS19H8dU1GGarEClA3dye5rhXTkWyrsrIE=; b=TKCbmJJXGqx2hwYssKFXHjMcEtoS6TrLM95ti+VBMg/NmmodRObFBkuqF5G7esS+ 4RoCoAfqTYjF2C3gpRhkDF2sWihCIrHky7EDO9erY+sopQrh50+q4QK7xsetGNgZiqI BKK/ZaHeuhqeEuoZeHqsrFzjjxQHe2rxbH3k8Fg4= Received: by mx.zohomail.com with SMTPS id 1741636804736523.5407434249297; Mon, 10 Mar 2025 13:00:04 -0700 (PDT) From: Ariel D'Alessandro To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: boris.brezillon@collabora.com, robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com, Ariel D'Alessandro Subject: [PATCH v1 3/6] drm/panfrost: Unify panfrost_mmu_enable/disable common code Date: Mon, 10 Mar 2025 16:59:18 -0300 Message-ID: <20250310195921.157511-4-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250310195921.157511-1-ariel.dalessandro@collabora.com> References: <20250310195921.157511-1-ariel.dalessandro@collabora.com> MIME-Version: 1.0 X-ZohoMailClient: External X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Both these functions write to MMU_AS_CONTROL register in the same way. Define a common _panfrost_mmu_as_control_write function with the shared code. Signed-off-by: Ariel D'Alessandro --- drivers/gpu/drm/panfrost/panfrost_mmu.c | 33 ++++++++++++------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index 294f86b3c25e7..31df3a96f89bd 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -121,38 +121,37 @@ static int mmu_hw_do_operation(struct panfrost_device *pfdev, return ret; } -static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) +static void +_panfrost_mmu_as_control_write(struct panfrost_device *pfdev, u32 as_nr, + u64 transtab, u64 memattr) { - int as_nr = mmu->as; - struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg; - u64 transtab = cfg->arm_mali_lpae_cfg.transtab; - u64 memattr = cfg->arm_mali_lpae_cfg.memattr; - mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), lower_32_bits(transtab)); mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), upper_32_bits(transtab)); - /* Need to revisit mem attrs. - * NC is the default, Mali driver is inner WT. - */ mmu_write(pfdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr)); mmu_write(pfdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr)); write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); } -static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr) +static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) { - mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); - - mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0); - mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0); + int as_nr = mmu->as; + struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg; + u64 transtab = cfg->arm_mali_lpae_cfg.transtab; + u64 memattr = cfg->arm_mali_lpae_cfg.memattr; - mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0); - mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0); + /* Need to revisit mem attrs. + * NC is the default, Mali driver is inner WT. + */ + _panfrost_mmu_as_control_write(pfdev, as_nr, transtab, memattr); +} - write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); +static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr) +{ + _panfrost_mmu_as_control_write(pfdev, as_nr, 0, 0); } u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) From patchwork Mon Mar 10 19:59:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ariel D'Alessandro X-Patchwork-Id: 14010586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8EE1FC282DE for ; Mon, 10 Mar 2025 20:00:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0282710E4DB; Mon, 10 Mar 2025 20:00:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=ariel.dalessandro@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1741636811; s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=zatpsj+gdBdKamfThnzVCKLLy8nFW3cK+OjTia4Wf/g=; b=HOtJv/GIBUsBZfsoeK54HQWiqrQmiCPP5JeIXb8i1AK5+TYJVFSApzAIFsXUWsY2 VRvZMxIodZQBQ+tHTg41diDE2ei2z7IYxNPI2V5z/+cCxKmd6cv7OPqYtivCIXz6/Vj z3aX5ilOWxApoJ5eJV3wOwj7H4M/XUK+3OZVka7s= Received: by mx.zohomail.com with SMTPS id 1741636809673712.2564638878398; Mon, 10 Mar 2025 13:00:09 -0700 (PDT) From: Ariel D'Alessandro To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: boris.brezillon@collabora.com, robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com, Ariel D'Alessandro Subject: [PATCH v1 4/6] drm/panfrost: Add support for AARCH64_4K page table format Date: Mon, 10 Mar 2025 16:59:19 -0300 Message-ID: <20250310195921.157511-5-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250310195921.157511-1-ariel.dalessandro@collabora.com> References: <20250310195921.157511-1-ariel.dalessandro@collabora.com> MIME-Version: 1.0 X-ZohoMailClient: External X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently, Panfrost only supports MMU configuration in "LEGACY" (as Bifrost calls it) mode, a (modified) version of LPAE "Large Physical Address Extension", which in Linux we've called "mali_lpae". This commit adds support for conditionally enabling AARCH64_4K page table format. To achieve that, a "GPU optional configurations" field was added to `struct panfrost_features` with the related flag. Note that, in order to enable AARCH64_4K mode, the GPU variant must have the HW_FEATURE_AARCH64_MMU feature flag present. Signed-off-by: Ariel D'Alessandro --- drivers/gpu/drm/panfrost/panfrost_device.h | 16 +++ drivers/gpu/drm/panfrost/panfrost_mmu.c | 132 +++++++++++++++++++-- drivers/gpu/drm/panfrost/panfrost_regs.h | 34 ++++++ 3 files changed, 169 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h index cffcb0ac7c111..0385702aa43c7 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -42,6 +42,14 @@ enum panfrost_gpu_pm { GPU_PM_VREG_OFF, }; +/** + * enum panfrost_gpu_config - GPU optional configurations + * @GPU_CONFIG_AARCH64_4K: Use AARCH64_4K page table format + */ +enum panfrost_gpu_config { + GPU_CONFIG_AARCH64_4K, +}; + struct panfrost_features { u16 id; u16 revision; @@ -95,6 +103,9 @@ struct panfrost_compatible { /* Allowed PM features */ u8 pm_features; + + /* GPU features */ + u8 gpu_configs; }; struct panfrost_device { @@ -162,6 +173,11 @@ struct panfrost_mmu { int as; atomic_t as_count; struct list_head list; + struct { + u64 transtab; + u64 memattr; + u64 transcfg; + } cfg; }; struct panfrost_engine_usage { diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index 31df3a96f89bd..4a9b8de2ff987 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -26,6 +26,48 @@ #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg) #define mmu_read(dev, reg) readl(dev->iomem + reg) +static u64 mair_to_memattr(u64 mair, bool coherent) +{ + u64 memattr = 0; + u32 i; + + for (i = 0; i < 8; i++) { + u8 in_attr = mair >> (8 * i), out_attr; + u8 outer = in_attr >> 4, inner = in_attr & 0xf; + + /* For caching to be enabled, inner and outer caching policy + * have to be both write-back, if one of them is write-through + * or non-cacheable, we just choose non-cacheable. Device + * memory is also translated to non-cacheable. + */ + if (!(outer & 3) || !(outer & 4) || !(inner & 4)) { + out_attr = AS_MEMATTR_AARCH64_INNER_OUTER_NC | + AS_MEMATTR_AARCH64_SH_MIDGARD_INNER | + AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(false, false); + } else { + out_attr = AS_MEMATTR_AARCH64_INNER_OUTER_WB | + AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(inner & 1, inner & 2); + /* Use SH_MIDGARD_INNER mode when device isn't coherent, + * so SH_IS, which is used when IOMMU_CACHE is set, maps + * to Mali's internal-shareable mode. As per the Mali + * Spec, inner and outer-shareable modes aren't allowed + * for WB memory when coherency is disabled. + * Use SH_CPU_INNER mode when coherency is enabled, so + * that SH_IS actually maps to the standard definition of + * inner-shareable. + */ + if (!coherent) + out_attr |= AS_MEMATTR_AARCH64_SH_MIDGARD_INNER; + else + out_attr |= AS_MEMATTR_AARCH64_SH_CPU_INNER; + } + + memattr |= (u64)out_attr << (8 * i); + } + + return memattr; +} + static int wait_ready(struct panfrost_device *pfdev, u32 as_nr) { int ret; @@ -121,9 +163,57 @@ static int mmu_hw_do_operation(struct panfrost_device *pfdev, return ret; } +static void mmu_cfg_init_mali_lpae(struct panfrost_mmu *mmu) +{ + struct io_pgtable_cfg *pgtbl_cfg = &mmu->pgtbl_cfg; + + /* TODO: The following fields are duplicated between the MMU and Page + * Table config structs. Ideally, should be kept in one place. + */ + mmu->cfg.transtab = pgtbl_cfg->arm_mali_lpae_cfg.transtab; + mmu->cfg.memattr = pgtbl_cfg->arm_mali_lpae_cfg.memattr; + mmu->cfg.transcfg = AS_TRANSCFG_ADRMODE_LEGACY; +} + +static void mmu_cfg_init_aarch64_4k(struct panfrost_mmu *mmu) +{ + struct io_pgtable_cfg *pgtbl_cfg = &mmu->pgtbl_cfg; + + mmu->cfg.transtab = pgtbl_cfg->arm_lpae_s1_cfg.ttbr & + AS_TRANSTAB_AARCH64_4K_ADDR_MASK; + + mmu->cfg.memattr = mair_to_memattr(pgtbl_cfg->arm_lpae_s1_cfg.mair, + pgtbl_cfg->coherent_walk); + + mmu->cfg.transcfg = AS_TRANSCFG_PTW_MEMATTR_WB | + AS_TRANSCFG_PTW_RA | + AS_TRANSCFG_ADRMODE_AARCH64_4K | + AS_TRANSCFG_INA_BITS(55 - pgtbl_cfg->ias); + if (pgtbl_cfg->coherent_walk) + mmu->cfg.transcfg |= AS_TRANSCFG_PTW_SH_OS; +} + +static void panfrost_mmu_cfg_init(struct panfrost_mmu *mmu, + enum io_pgtable_fmt fmt) +{ + struct panfrost_device *pfdev = mmu->pfdev; + + switch (fmt) { + case ARM_64_LPAE_S1: + mmu_cfg_init_aarch64_4k(mmu); + break; + case ARM_MALI_LPAE: + mmu_cfg_init_mali_lpae(mmu); + break; + default: + dev_WARN_ONCE(pfdev->dev, 1, "Unhandled page table format\n"); + break; + } +} + static void _panfrost_mmu_as_control_write(struct panfrost_device *pfdev, u32 as_nr, - u64 transtab, u64 memattr) + u64 transtab, u64 memattr, u64 transcfg) { mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); @@ -133,25 +223,28 @@ _panfrost_mmu_as_control_write(struct panfrost_device *pfdev, u32 as_nr, mmu_write(pfdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr)); mmu_write(pfdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr)); + mmu_write(pfdev, AS_TRANSCFG_LO(as_nr), lower_32_bits(transcfg)); + mmu_write(pfdev, AS_TRANSCFG_HI(as_nr), upper_32_bits(transcfg)); + write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); + + dev_dbg(pfdev->dev, "mmu_as_control: as=%d, transtab=0x%016llx, memattr=0x%016llx, transcfg=0x%016llx", + as_nr, transtab, memattr, transcfg); } static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) { - int as_nr = mmu->as; - struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg; - u64 transtab = cfg->arm_mali_lpae_cfg.transtab; - u64 memattr = cfg->arm_mali_lpae_cfg.memattr; - /* Need to revisit mem attrs. * NC is the default, Mali driver is inner WT. */ - _panfrost_mmu_as_control_write(pfdev, as_nr, transtab, memattr); + _panfrost_mmu_as_control_write(pfdev, mmu->as, mmu->cfg.transtab, + mmu->cfg.memattr, mmu->cfg.transcfg); } static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr) { - _panfrost_mmu_as_control_write(pfdev, as_nr, 0, 0); + _panfrost_mmu_as_control_write(pfdev, as_nr, 0, 0, + AS_TRANSCFG_ADRMODE_UNMAPPED); } u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) @@ -616,6 +709,7 @@ struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev) { u32 va_bits = GPU_MMU_FEATURES_VA_BITS(pfdev->features.mmu_features); u32 pa_bits = GPU_MMU_FEATURES_PA_BITS(pfdev->features.mmu_features); + enum io_pgtable_fmt fmt = ARM_MALI_LPAE; struct panfrost_mmu *mmu; mmu = kzalloc(sizeof(*mmu), GFP_KERNEL); @@ -641,16 +735,28 @@ struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev) .iommu_dev = pfdev->dev, }; - mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg, - mmu); - if (!mmu->pgtbl_ops) { - kfree(mmu); - return ERR_PTR(-EINVAL); + if (pfdev->comp->gpu_configs & BIT(GPU_CONFIG_AARCH64_4K)) { + if (!panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU)) { + dev_err_once(pfdev->dev, + "AARCH64_4K page table not supported\n"); + goto err_free_mmu; + } + fmt = ARM_64_LPAE_S1; } + mmu->pgtbl_ops = alloc_io_pgtable_ops(fmt, &mmu->pgtbl_cfg, mmu); + if (!mmu->pgtbl_ops) + goto err_free_mmu; + + panfrost_mmu_cfg_init(mmu, fmt); + kref_init(&mmu->refcount); return mmu; + +err_free_mmu: + kfree(mmu); + return ERR_PTR(-EINVAL); } static const char *access_type_name(struct panfrost_device *pfdev, diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/panfrost/panfrost_regs.h index b5f279a19a084..2b8f1617b8369 100644 --- a/drivers/gpu/drm/panfrost/panfrost_regs.h +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h @@ -301,6 +301,17 @@ #define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */ #define AS_MEMATTR_LO(as) (MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low word. */ #define AS_MEMATTR_HI(as) (MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high word. */ +#define AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL (2 << 2) +#define AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r) ((3 << 2) | \ + ((w) ? BIT(0) : 0) | \ + ((r) ? BIT(1) : 0)) +#define AS_MEMATTR_AARCH64_SH_MIDGARD_INNER (0 << 4) +#define AS_MEMATTR_AARCH64_SH_CPU_INNER (1 << 4) +#define AS_MEMATTR_AARCH64_SH_CPU_INNER_SHADER_COH (2 << 4) +#define AS_MEMATTR_AARCH64_SHARED (0 << 6) +#define AS_MEMATTR_AARCH64_INNER_OUTER_NC (1 << 6) +#define AS_MEMATTR_AARCH64_INNER_OUTER_WB (2 << 6) +#define AS_MEMATTR_AARCH64_FAULT (3 << 6) #define AS_LOCKADDR_LO(as) (MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, low word */ #define AS_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */ #define AS_COMMAND(as) (MMU_AS(as) + 0x18) /* (WO) MMU command register for address space n */ @@ -311,6 +322,24 @@ /* Additional Bifrost AS registers */ #define AS_TRANSCFG_LO(as) (MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address space n, low word */ #define AS_TRANSCFG_HI(as) (MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */ +#define AS_TRANSCFG_ADRMODE_LEGACY (0 << 0) +#define AS_TRANSCFG_ADRMODE_UNMAPPED (1 << 0) +#define AS_TRANSCFG_ADRMODE_IDENTITY (2 << 0) +#define AS_TRANSCFG_ADRMODE_AARCH64_4K (6 << 0) +#define AS_TRANSCFG_ADRMODE_AARCH64_64K (8 << 0) +#define AS_TRANSCFG_INA_BITS(x) ((x) << 6) +#define AS_TRANSCFG_OUTA_BITS(x) ((x) << 14) +#define AS_TRANSCFG_SL_CONCAT BIT(22) +#define AS_TRANSCFG_PTW_MEMATTR_NC (1 << 24) +#define AS_TRANSCFG_PTW_MEMATTR_WB (2 << 24) +#define AS_TRANSCFG_PTW_SH_NS (0 << 28) +#define AS_TRANSCFG_PTW_SH_OS (2 << 28) +#define AS_TRANSCFG_PTW_SH_IS (3 << 28) +#define AS_TRANSCFG_PTW_RA BIT(30) +#define AS_TRANSCFG_DISABLE_HIER_AP BIT(33) +#define AS_TRANSCFG_DISABLE_AF_FAULT BIT(34) +#define AS_TRANSCFG_WXN BIT(35) +#define AS_TRANSCFG_XREADABLE BIT(36) #define AS_FAULTEXTRA_LO(as) (MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */ #define AS_FAULTEXTRA_HI(as) (MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */ @@ -326,6 +355,11 @@ #define AS_TRANSTAB_LPAE_READ_INNER BIT(2) #define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4) +/* + * Begin AARCH64_4K MMU TRANSTAB register values + */ +#define AS_TRANSTAB_AARCH64_4K_ADDR_MASK 0xfffffffffffffff0 + #define AS_STATUS_AS_ACTIVE 0x01 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8) From patchwork Mon Mar 10 19:59:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ariel D'Alessandro X-Patchwork-Id: 14010587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEA42C282DE for ; Mon, 10 Mar 2025 20:00:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2538A10E4DA; Mon, 10 Mar 2025 20:00:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b="XRFB2hK9"; dkim-atps=neutral Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) by gabe.freedesktop.org (Postfix) with ESMTPS id 571D510E4DA for ; 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s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=ZFdaB7brRwLIqNemNPKTG25GbzNbXSuAOMUD7Q7r3hc=; b=XRFB2hK94KDo+X/2ol9lRhnmk62XqlLS4u/WptOz30sIj5qc6tC7UxaCtuf0AkPI 6miSmXzgg42EZpN5SyzRZZXLBYVaxRVJe0B/RLcJpyO7ar9tfplJ5JZTCmX11DZDwwW QEJ7Y1ZPxnc6rsuyL8lPygnXwV3YwKRN169eQELw= Received: by mx.zohomail.com with SMTPS id 1741636814321993.7241909367491; Mon, 10 Mar 2025 13:00:14 -0700 (PDT) From: Ariel D'Alessandro To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: boris.brezillon@collabora.com, robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com, Ariel D'Alessandro Subject: [PATCH v1 5/6] drm/panfrost: Enable AARCH64_4K page table format on mediatek_mt8188 Date: Mon, 10 Mar 2025 16:59:20 -0300 Message-ID: <20250310195921.157511-6-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250310195921.157511-1-ariel.dalessandro@collabora.com> References: <20250310195921.157511-1-ariel.dalessandro@collabora.com> MIME-Version: 1.0 X-ZohoMailClient: External X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now that Panfrost supports AARCH64_4K page table format, let's enable it on Mediatek MT8188. Signed-off-by: Ariel D'Alessandro Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c index 0f3935556ac76..d7b8bded6d784 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -824,6 +824,7 @@ static const struct panfrost_compatible mediatek_mt8188_data = { .num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names = mediatek_mt8183_pm_domains, .pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), + .gpu_configs = BIT(GPU_CONFIG_AARCH64_4K), }; static const char * const mediatek_mt8192_supplies[] = { "mali", NULL }; From patchwork Mon Mar 10 19:59:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ariel D'Alessandro X-Patchwork-Id: 14010588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A159CC282DE for ; Mon, 10 Mar 2025 20:00:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1063010E4DC; Mon, 10 Mar 2025 20:00:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b="HrkY0K1V"; dkim-atps=neutral Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) by gabe.freedesktop.org (Postfix) with ESMTPS id C1D8310E4DC for ; Mon, 10 Mar 2025 20:00:32 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; t=1741636820; cv=none; d=zohomail.com; s=zohoarc; b=Ep1jAyWe1+XXmXUKDfGKdFqzwvvx567SCPi/EfuLlFK1zh0y4LBX0Exk9U5dGmI1gQJUoWg3uPZ0uOcZiTgCPpTGHxgl1usND5ilmo9DT5ATrMJyrpDKaKM/EVOKdFbhpB7fLqwd0G5lHrmYf8dKMFfbI4jLSbHrKAe3ioduwWU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741636820; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Ri5NxGP83GAWZRTNAwusSEW6eUICnHU4WNe3YwZobXY=; b=fGPxV/0+GRiJAv1SHqyW9RDRFCRf4N7/wFT/IWpWVnUOGkU+fcyfhBgiOcJXq91mWlq4Ozox9dpp7ZLBc1B9PxOJ9h07SY+PbMB37EwuWjr5PLtWGuRVr7bW5HoGVC/ldA3ztN9E7dasfowC3Q1MPDSjB79/ka4LWwZFPYNUQ48= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=ariel.dalessandro@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1741636820; s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=Ri5NxGP83GAWZRTNAwusSEW6eUICnHU4WNe3YwZobXY=; b=HrkY0K1V0fypJT4eC4spkdxIKpb07lKFGZP7EJJx+FXGftYALB/4BzpES7ozc/xe hyJfrUnyI0M49ueGBJZbTvucN82b3KrQNG7DkFWFwR6cXNb3euNo6PPIPRTMEa1uUE9 cyZBgbL+Kg+WTuVUQrLQhx7IGQeIoXSMmBFoEe8k= Received: by mx.zohomail.com with SMTPS id 1741636818884184.34015520872072; Mon, 10 Mar 2025 13:00:18 -0700 (PDT) From: Ariel D'Alessandro To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: boris.brezillon@collabora.com, robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com, Ariel D'Alessandro Subject: [PATCH v1 6/6] drm/panfrost: Set HW_FEATURE_AARCH64_MMU feature flag on Bifrost models Date: Mon, 10 Mar 2025 16:59:21 -0300 Message-ID: <20250310195921.157511-7-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250310195921.157511-1-ariel.dalessandro@collabora.com> References: <20250310195921.157511-1-ariel.dalessandro@collabora.com> MIME-Version: 1.0 X-ZohoMailClient: External X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Set this feature flag on all Mali Bifrost platforms as the MMU supports AARCH64 4K page table format. Signed-off-by: Ariel D'Alessandro Reviewed-by: Boris Brezillon --- drivers/gpu/drm/panfrost/panfrost_features.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_features.h b/drivers/gpu/drm/panfrost/panfrost_features.h index 7ed0cd3ea2d4c..52f9d69f6db9d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_features.h +++ b/drivers/gpu/drm/panfrost/panfrost_features.h @@ -54,6 +54,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \ BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \ BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ + BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) #define hw_features_g72 (\ @@ -64,6 +65,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \ BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \ + BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) #define hw_features_g51 hw_features_g72 @@ -77,6 +79,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \ BIT_ULL(HW_FEATURE_IDVS_GROUP_SIZE) | \ + BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) #define hw_features_g76 (\