From patchwork Wed Mar 20 11:52:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yash Shah X-Patchwork-Id: 10861493 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 136B61390 for ; Wed, 20 Mar 2019 11:53:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E63F329B5F for ; Wed, 20 Mar 2019 11:53:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D9C6729B6B; Wed, 20 Mar 2019 11:53:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 862CF29B5F for ; Wed, 20 Mar 2019 11:53:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=htUXQQLwYcJhH8oN5eLCqmEMlyQQb4+0yYjikVYh/A4=; b=Km++u18+dj+CQioclMyhY8JXU1 MrFF/9RLK5P/1lOuq3p1GhlOfslb1ik62B6nIN3RTVQ2Uw5PiJeshM00eOyhSsaFzFnz3edsO8nt/ c/COb86w2o+5nD9269suJRFIedGwSXXlA8q7jQo3POM8Eso/5I0pgL4awJi4TtMcjfF4W658qIwkG AiDsW3GgcFaUXhBgpNSR8qCk/2wXrlEeOHaZknVW3o7SJi6Xwe+UPi/sHjd6UArPnWg5QrreWB7TR ZLECEZt45PiuHD7122iDnS7zbaNqKklmjQufbWrg/SeOR6DO0/UIc1a/NlIJENIgVDSoUVKtBlnAt zjRBvuhg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h6Zmz-000484-T0; Wed, 20 Mar 2019 11:53:45 +0000 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h6Zmx-00047E-Pz for linux-riscv@lists.infradead.org; Wed, 20 Mar 2019 11:53:44 +0000 Received: by mail-pf1-x444.google.com with SMTP id c8so1762005pfd.10 for ; Wed, 20 Mar 2019 04:53:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ImPJCN+vsTzjzXErHaf6oGJCBI+1ar28iCl0HZa9VJQ=; b=aqrgRi2XiQUISUC2hN202lYS7gbLH0k54i5sP9YK9JMdormsXoYFybNxHb8Ifb83rW iS2V7dlDwSJHCpbAEgTWxyb0+Ib6wEgDsFG3qOgI8Axk3xicYpFdhBpMiIU1CAiuIk2l Y4CTb3P+9c7azxNbpLkGt+T/kwmi2LsDUSbPuuhqFm/WqClrxiMhurtj2grqXpnOC9mO Dug1pVmIKFGywdy6OhOKwEPXCVauQwK0gbSClY4AlZkT9nf1dVKvWYK618h4MWL3sot8 Lx2Mly41pDxZ/NDL+BjLn37+wFG8mTYwbRZIXjhNtoLN2aQ907nxOdI57o+iyni0tGeV MOZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ImPJCN+vsTzjzXErHaf6oGJCBI+1ar28iCl0HZa9VJQ=; b=TyEqofM2siVYw3CsVMCFVe+WUUsoKpRUpVM3pb3SC6aJz7+5WGcTIjbP6bGoSb5O/0 ghaEfSaQSfqyKB/qOp2am6nE9+kl38MEjZrkmUiMUdxRPKikxKw7ykqibak4IvsF0klk v8kG1AzSdwPiWigY77iIaP0lGLtKALNI84MMOwT9Fc3+UWLY14dqrM+nPhckizffeP+m mnTHIuchF926tuLnjUCBHTjewCtumLxEE25jCBSja+nYrHCdXXrU8Yrnvg7OTUu9zgK9 o3aufAXtTZEuZOTrQXRhSufrYipAvE1bMbEWYEmKW2jOixje0t9E+V2Yey/fMyEHPjv1 OXDA== X-Gm-Message-State: APjAAAUvzedlmyy8fURCV6S3pP9Xmj2gVZt3sdnQum58H+kIZNE393EM D7pWeRXEe1ZOXAf1pazWuiXzYSmAQRE= X-Google-Smtp-Source: APXvYqylgTysB+3yhU/KJWubLD4VCZXV5AxUqj+FUcQXvuuCDxz3Ibplyw/B3I9277VuVdluFL/mYQ== X-Received: by 2002:a17:902:6b08:: with SMTP id o8mr30982481plk.105.1553082822850; Wed, 20 Mar 2019 04:53:42 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id u10sm1999435pgr.2.2019.03.20.04.53.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 04:53:41 -0700 (PDT) From: Yash Shah To: linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, palmer@sifive.com, paul.walmsley@sifive.com Subject: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive EDAC driver and subcomponent Date: Wed, 20 Mar 2019 17:22:07 +0530 Message-Id: <1553082728-9232-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1553082728-9232-1-git-send-email-yash.shah@sifive.com> References: <1553082728-9232-1-git-send-email-yash.shah@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190320_045343_839442_A8F9EF82 X-CRM114-Status: GOOD ( 10.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah , robh+dt@kernel.org, bp@alien8.de, mchehab@kernel.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP DT documentation for EDAC driver added. DT documentation for subcomponent L2 cache controller also added. Signed-off-by: Yash Shah --- .../devicetree/bindings/edac/sifive-edac.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/sifive-edac.txt diff --git a/Documentation/devicetree/bindings/edac/sifive-edac.txt b/Documentation/devicetree/bindings/edac/sifive-edac.txt new file mode 100644 index 0000000..c0e3ac7 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/sifive-edac.txt @@ -0,0 +1,40 @@ +SiFive ECC Manager +This driver uses the EDAC framework to implement the SiFive ECC Manager. + +Required Properties: +- compatible : Should be "sifive,ecc-manager" +- #address-cells: must be 2 +- #size-cells: must be 2 +- ranges : standard definition, should translate from local addresses + +Subcomponents: + +L2 Cache ECC +Required Properties: +- compatible: Should be "sifive,-ccache" and "sifive,ccache". + Supported compatible strings are: + "sifive,fu540-c000-ccache" for the SiFive cache controller v0 as integrated + onto the SiFive FU540 chip, and "sifive,ccache0" for the SiFive + cache controller v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details +- interrupt-parent: Must be core interrupt controller +- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals +- reg: Physical base address and size of L2 cache controller registers map + A second range can indicate L2 Loosely Integrated Memory + +Example: + +eccmgr: eccmgr { + compatible = "sifive,ecc-manager"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + l2-ecc@2010000 { + compatible = "sifive,fu540-c000-ccache", "sifive,ccache0"; + interrupt-parent = <&plic0>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; + }; +}; + From patchwork Wed Mar 20 11:52:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yash Shah X-Patchwork-Id: 10861495 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1CE801390 for ; Wed, 20 Mar 2019 11:53:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EDD3529B66 for ; Wed, 20 Mar 2019 11:53:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E160E29B68; Wed, 20 Mar 2019 11:53:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1D96429B67 for ; Wed, 20 Mar 2019 11:53:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=GGGxdlNKrhJxHq04e8no2Xomd3/bt2BhIs+326MOhBo=; b=C8NAB/QrhJXHVjr+VO1wGWRfDx 7lF9eLOMTSiMfzpx9IbFse3kk+BqXFRdv4uUl8+ealeXAQffzEEUnLPbqlB9MrdPwvTYFS5BksVtQ pqnULGDgqkZMZXDMe0c57tpooKHwh8A8R1+TO1IUbUun3F4avsJTRuFk9DM485bUd9m6yJIbNExPB XJMnhhB0M0rJNbsOmORJGyk/4W2fZ8/pFIrGvfVISPNWUKpkZN2Z1tQfso+pGSN3iFB8lNnyb60Jz DmkqKwKkH6zMZQccPFh0oHzgZg6eGrqzZi23rGlCHXHoC/znUa86oH2otn5Tn8NjQfGkrCGqcvnOM FwAyt52g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h6Zn8-0004Bn-FW; Wed, 20 Mar 2019 11:53:54 +0000 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h6Zn5-0004BC-2N for linux-riscv@lists.infradead.org; Wed, 20 Mar 2019 11:53:52 +0000 Received: by mail-pf1-x444.google.com with SMTP id v64so1786880pfb.1 for ; Wed, 20 Mar 2019 04:53:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LrD9ef6jRi4Ew9eqOrL8wZ6fmVnDcVu1JDMZzlUdXhI=; b=Acfp+eAuP4FcMzudDyaISlQscfeq6qEVrip9EmU6wJSr68mBEsOLpc+L54O4cHGjnx nLR198WR+TNRZZEkGR5+v1bDr3Y7HvHhWLScSdMZuagtXD1QUQlD4LFW0xP3wg8L4zLP O3dj8rOy4kJVAm9QypTO2bTFzxohzgaXH/DH18lLNOu5UmpUqTysp8F5PLfYh0AKmmfr 4gOCL7S/DPxdyvrq/ZHf2pEGE0o2q/JYXIK2fhRIwR/7P+ZMO2pSV/VpJsQK1IDdoY8z s94G5rKQARpJDsrQ1YitbbNDzMxinluNx9Lu/GYdDp83BjigNjmGHz19/jWwQjREzEdH qVIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LrD9ef6jRi4Ew9eqOrL8wZ6fmVnDcVu1JDMZzlUdXhI=; b=hiQaWaOK5t90wWP5FgqVS+cibH9cKMkyhv/39tlpkseIpIQ9VHRjBgiOT5bbSpKyea q1ZoG9x+aAC1IlOb707m5N1BRlCRwTfzLNqiijATpaFDuv0yYmfLrri8WTJ5hHB9V4Lh 3HLLiGarhex0TlZHHmRWzDZwhQ7ln2m4Bm2yG4jzvYPk2bmp8PrFhDpo4X3zO55Ho0Ri nfr1IROHY3CHj3BG9sl+XztO2hMgU71+rrCIIkZFSufQoetIWQq3wPxelAVuBlqLfRgn cy+lUB+LDyDoqde3aGIGu4Xrb2Gnmmf3EyRx6M2roQm0gbozvvq+ZXvqB9SHyfbE0dn6 ts3g== X-Gm-Message-State: APjAAAUimnqKwoAe++il+civRT1maV7KWs/uuOY7wjX3qdgSWTxyvM6T XkpODLzhD6tNTgfDbXa6TgabvDXSlGE= X-Google-Smtp-Source: APXvYqwwpLIdxLHcYrba/mguyegxfGR9Ysvb9Rp2MSHSyc2iPeB3O8JmvkZP/HRor//68tk5Qn+v+g== X-Received: by 2002:aa7:8609:: with SMTP id p9mr7538948pfn.166.1553082830117; Wed, 20 Mar 2019 04:53:50 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id u10sm1999435pgr.2.2019.03.20.04.53.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 04:53:49 -0700 (PDT) From: Yash Shah To: linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, palmer@sifive.com, paul.walmsley@sifive.com Subject: [PATCH 2/2] edac: sifive: Add EDAC driver for SiFive FU540-C000 chip Date: Wed, 20 Mar 2019 17:22:08 +0530 Message-Id: <1553082728-9232-3-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1553082728-9232-1-git-send-email-yash.shah@sifive.com> References: <1553082728-9232-1-git-send-email-yash.shah@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190320_045351_118692_38FCB44A X-CRM114-Status: GOOD ( 19.31 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah , robh+dt@kernel.org, bp@alien8.de, mchehab@kernel.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This EDAC driver supports: - Initial configuration reporting on bootup via debug logs - ECC event monitoring and reporting through the EDAC framework - ECC event injection This driver is partially based on pnd2_edac.c and altera_edac.c Initially L2 Cache controller is added as a subcomponent to this EDAC driver. Signed-off-by: Yash Shah --- arch/riscv/Kconfig | 1 + drivers/edac/Kconfig | 13 ++ drivers/edac/Makefile | 1 + drivers/edac/sifive_edac.c | 297 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 312 insertions(+) create mode 100644 drivers/edac/sifive_edac.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 515fc3c..fede4b6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -49,6 +49,7 @@ config RISCV select RISCV_TIMER select GENERIC_IRQ_MULTI_HANDLER select ARCH_HAS_PTE_SPECIAL + select EDAC_SUPPORT config MMU def_bool y diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index e286b5b..112d9d1 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -440,6 +440,19 @@ config EDAC_ALTERA_SDMMC Support for error detection and correction on the Altera SDMMC FIFO Memory for Altera SoCs. +config EDAC_SIFIVE + tristate "Sifive ECC" + depends on RISCV + help + Support for error detection and correction on the SiFive SoCs. + +config EDAC_SIFIVE_L2 + bool "SiFive L2 Cache ECC" + depends on EDAC_SIFIVE=y + help + Support for error detection and correction of the L2 cache + memory on SiFive SoCs. + config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" depends on ARCH_ZYNQ || ARCH_ZYNQMP diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 716096d..b16dce8 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -74,6 +74,7 @@ obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o obj-$(CONFIG_EDAC_THUNDERX) += thunderx_edac.o obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o +obj-$(CONFIG_EDAC_SIFIVE) += sifive_edac.o obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c new file mode 100644 index 0000000..e11ae6b5 --- /dev/null +++ b/drivers/edac/sifive_edac.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SiFive EDAC Driver + * + * Copyright (C) 2018-2019 SiFive, Inc. + * + */ +#include +#include +#include +#include +#include +#include +#include "edac_module.h" + +#define SIFIVE_EDAC_DIRFIX_LOW 0x100 +#define SIFIVE_EDAC_DIRFIX_HIGH 0x104 +#define SIFIVE_EDAC_DIRFIX_COUNT 0x108 + +#define SIFIVE_EDAC_DATFIX_LOW 0x140 +#define SIFIVE_EDAC_DATFIX_HIGH 0x144 +#define SIFIVE_EDAC_DATFIX_COUNT 0x148 + +#define SIFIVE_EDAC_DATFAIL_LOW 0x160 +#define SIFIVE_EDAC_DATFAIL_HIGH 0x164 +#define SIFIVE_EDAC_DATFAIL_COUNT 0x168 + +#define SIFIVE_EDAC_ECCINJECTERR 0x40 +#define SIFIVE_EDAC_CONFIG 0x00 + +#define SIFIVE_EDAC_MAX_INTR 3 + +/************************* EDAC Parent Probe *************************/ + +static const struct of_device_id sifive_edac_device_of_match[]; + +static const struct of_device_id sifive_edac_of_match[] = { + { .compatible = "sifive,ecc-manager" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sifive_edac_of_match); + +static int sifive_edac_probe(struct platform_device *pdev) +{ + of_platform_populate(pdev->dev.of_node, sifive_edac_device_of_match, + NULL, &pdev->dev); + return 0; +} + +static struct platform_driver sifive_edac_driver = { + .probe = sifive_edac_probe, + .driver = { + .name = "ecc_manager", + .of_match_table = sifive_edac_of_match, + }, +}; +module_platform_driver(sifive_edac_driver); + +struct sifive_edac_device_prv { + void (*setup)(struct edac_device_ctl_info *dci); + irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id); + const struct file_operations *inject_fops; +}; + +struct sifive_edac_device_dev { + void __iomem *base; + int irq[SIFIVE_EDAC_MAX_INTR]; + struct sifive_edac_device_prv *data; + char *edac_dev_name; +}; + +enum { + dir_corr = 0, + data_corr, + data_uncorr, +}; + +static struct dentry *sifive_edac_test; + +static ssize_t sifive_edac_l2_write(struct file *file, const char __user *data, + size_t count, loff_t *ppos) +{ + struct edac_device_ctl_info *dci = file->private_data; + struct sifive_edac_device_dev *drvdata = dci->pvt_info; + unsigned int val; + + if (kstrtouint_from_user(data, count, 0, &val)) + return -EINVAL; + if ((val >= 0 && val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) + writel(val, drvdata->base + SIFIVE_EDAC_ECCINJECTERR); + else + return -EINVAL; + return count; +} + +static const struct file_operations sifive_edac_l2_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .write = sifive_edac_l2_write +}; + +static void setup_sifive_debug(struct edac_device_ctl_info *edac_dci, + const struct sifive_edac_device_prv *prv) +{ + struct sifive_edac_device_dev *drvdata = edac_dci->pvt_info; + + if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) + return; + + sifive_edac_test = edac_debugfs_create_dir(drvdata->edac_dev_name); + if (!sifive_edac_test) + return; + + if (!edac_debugfs_create_file("sifive_debug_inject_error", 0200, + sifive_edac_test, edac_dci, + prv->inject_fops)) + debugfs_remove_recursive(sifive_edac_test); +} + +static void teardown_sifive_debug(void) +{ + debugfs_remove_recursive(sifive_edac_test); +} + +/* + * sifive_edac_l2_int_handler - ISR function for l2 cache controller + * @irq: Irq Number + * @device: Pointer to the edac device controller instance + * + * This routine is triggered whenever there is ECC error detected + * + * Return: Always returns IRQ_HANDLED + */ +static irqreturn_t sifive_edac_l2_int_handler(int irq, void *device) +{ + struct edac_device_ctl_info *dci = + (struct edac_device_ctl_info *)device; + struct sifive_edac_device_dev *drvdata = dci->pvt_info; + u32 regval, add_h, add_l; + + if (irq == drvdata->irq[dir_corr]) { + add_h = readl(drvdata->base + SIFIVE_EDAC_DIRFIX_HIGH); + add_l = readl(drvdata->base + SIFIVE_EDAC_DIRFIX_LOW); + dev_err(dci->dev, + "DirError at address 0x%08X.%08X\n", add_h, add_l); + regval = readl(drvdata->base + SIFIVE_EDAC_DIRFIX_COUNT); + edac_device_handle_ce(dci, 0, 0, "DirECCFix"); + } + if (irq == drvdata->irq[data_corr]) { + add_h = readl(drvdata->base + SIFIVE_EDAC_DATFIX_HIGH); + add_l = readl(drvdata->base + SIFIVE_EDAC_DATFIX_LOW); + dev_err(dci->dev, + "DataError at address 0x%08X.%08X\n", add_h, add_l); + regval = readl(drvdata->base + SIFIVE_EDAC_DATFIX_COUNT); + edac_device_handle_ce(dci, 0, 0, "DatECCFix"); + } + if (irq == drvdata->irq[data_uncorr]) { + add_h = readl(drvdata->base + SIFIVE_EDAC_DATFAIL_HIGH); + add_l = readl(drvdata->base + SIFIVE_EDAC_DATFAIL_LOW); + dev_err(dci->dev, + "DataFail at address 0x%08X.%08X\n", add_h, add_l); + regval = readl(drvdata->base + SIFIVE_EDAC_DATFAIL_COUNT); + edac_device_handle_ue(dci, 0, 0, "DatECCFail"); + } + + return IRQ_HANDLED; +} + +static void sifive_edac_l2_config_read(struct edac_device_ctl_info *dci) +{ + struct sifive_edac_device_dev *drvdata = dci->pvt_info; + u32 regval, val; + + regval = readl(drvdata->base + SIFIVE_EDAC_CONFIG); + val = regval & 0xFF; + dev_info(dci->dev, "No. of Banks in the cache: %d\n", val); + val = (regval & 0xFF00) >> 8; + dev_info(dci->dev, "No. of ways per bank: %d\n", val); + val = (regval & 0xFF0000) >> 16; + dev_info(dci->dev, "Sets per bank: %llu\n", (uint64_t)1 << val); + val = (regval & 0xFF000000) >> 24; + dev_info(dci->dev, + "Bytes per cache block: %llu\n", (uint64_t)1 << val); +} + +static const struct sifive_edac_device_prv l2ecc_data = { + .setup = sifive_edac_l2_config_read, + .inject_fops = &sifive_edac_l2_fops, + .ecc_irq_handler = sifive_edac_l2_int_handler, +}; + +/* + * sifive_edac_device_probe() + * This is a generic EDAC device driver that will support + * various SiFive memory devices as well as the memories + * for other peripherals. Module specific initialization is + * done by passing the function index in the device tree. + */ +static int sifive_edac_device_probe(struct platform_device *pdev) +{ + struct edac_device_ctl_info *dci; + struct sifive_edac_device_dev *drvdata; + int rc, i; + struct resource *res; + void __iomem *baseaddr; + struct device_node *np = pdev->dev.of_node; + char *ecc_name = (char *)np->name; + static int dev_instance; + + /* Get the data from the platform device */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + baseaddr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(baseaddr)) + return PTR_ERR(baseaddr); + + dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, + 1, ecc_name, 1, 1, NULL, 0, + dev_instance++); + if (IS_ERR(dci)) + return PTR_ERR(dci); + + drvdata = dci->pvt_info; + drvdata->base = baseaddr; + drvdata->edac_dev_name = ecc_name; + dci->dev = &pdev->dev; + dci->mod_name = "Sifive ECC Manager"; + dci->ctl_name = dev_name(&pdev->dev); + dci->dev_name = dev_name(&pdev->dev); + + /* Get driver specific data for this EDAC device */ + drvdata->data = of_match_node(sifive_edac_device_of_match, np)->data; + + setup_sifive_debug(dci, drvdata->data); + + if (drvdata->data->setup) + drvdata->data->setup(dci); + + for (i = 0; i < SIFIVE_EDAC_MAX_INTR; i++) { + drvdata->irq[i] = platform_get_irq(pdev, i); + rc = devm_request_irq(&pdev->dev, drvdata->irq[i], + sifive_edac_l2_int_handler, 0, + dev_name(&pdev->dev), (void *)dci); + if (rc) { + dev_err(&pdev->dev, + "Could not request IRQ %d\n", drvdata->irq[i]); + goto del_edac_device; + } + } + + rc = edac_device_add_device(dci); + if (rc) { + dev_err(&pdev->dev, "failed to register with EDAC core\n"); + goto del_edac_device; + } + + return rc; + +del_edac_device: + teardown_sifive_debug(); + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(dci); + + return rc; +} + +static int sifive_edac_device_remove(struct platform_device *pdev) +{ + struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); + + teardown_sifive_debug(); + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(dci); + + return 0; +} + +static const struct of_device_id sifive_edac_device_of_match[] = { + { .compatible = "sifive,ccache0", .data = &l2ecc_data }, + { /* end of table */ }, +}; +MODULE_DEVICE_TABLE(of, sifive_edac_device_of_match); + +static struct platform_driver sifive_edac_device_driver = { + .driver = { + .name = "sifive_edac_device", + .owner = THIS_MODULE, + .of_match_table = sifive_edac_device_of_match, + }, + .probe = sifive_edac_device_probe, + .remove = sifive_edac_device_remove, +}; + +module_platform_driver(sifive_edac_device_driver); + +MODULE_AUTHOR("SiFive Inc."); +MODULE_DESCRIPTION("SiFive EDAC driver"); +MODULE_LICENSE("GPL v2");