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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfba9sm19480872f8f.39.2025.03.11.14.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 14:12:47 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 95e918ae-febd-11ef-9898-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741727568; x=1742332368; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MYYWoFXQadYNqg3ppNES3f8YOcne8bmt2zBhfPE0KsI=; b=NQ7ppZ5BoMP+56b3zvvq0pg9IntpOq2H7hwB9NAWZHQgz9Vev0XfpO+inCeHB/FD5Q zgNjofAmDPEnnlOuu5w+LRA3sFAZ5T5xj/9UleERfO84m7FYCcQ5LmNf1Z8b+vsbuKoj 9EVOA3/9AHmOibF/D7j7KuX4aN/Ou7MHC8loA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741727568; x=1742332368; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MYYWoFXQadYNqg3ppNES3f8YOcne8bmt2zBhfPE0KsI=; b=NmygXvVXZ5hdakzcLs+Lx7gqPw4hRbZ6a2ayj7LQe2LfZUGq+OechiYj0d8JupEZnW p+h3ooUyWl6c7Ca0whSOH82Lx4XSidiwwOFthbmYLfZIN24mPJ/YCPjF8MvwZkoX7kKI TJp+psLXh4EdGywgoBd7EnBYJqwbzOroS82og7+mExVLyXsDgp1IUILmg3+FQJaW8BJO UNS0CkJvGPSioqkfqd+dwmk6+d91fiCiHvEIkwJV/YUIXFATqAbN+pc5b/8vvIxXZUSy EbGAAhMV/kFcFUHtRD387eZ3WaCzdhQPDNOca3BKXHgzcgVRJqOLXggWe27uLL2tvQ0H TGWQ== X-Gm-Message-State: AOJu0YxtNDVnCCwP3tqQuMAV3qb2J4L/3z8iW2d79SP1bhrgAPQqcOnz nzredl4bMW+mOakCqwJhBbYTOGXBjpLKbmHcFxAX3ufHxz8FqPJdwP3w1kpnnyeaI84TZ4xto6d z X-Gm-Gg: ASbGncuq/HjRfF9g/5MlXIP+HnUiK2yOr8RySPFuzLJIAs2GEh/W1xnUqN+vqD229P7 Iv75CmxDw5mPgfpAhzjeY1nutTt17KEJTDiNZhx9ToZgOI2sxb22yfi6gWWIJLKpoF66LwCUJ62 wRYurEYT3W/nAh9mYcwxEm3gY44sURqckAyZtezO9Wz6pgqWRjifj6SoNPNu6jd2/UQUbS1lpiK KT7Y2vUTa6meqzASa2D53RGI4gYzF6NR8QzHRmGbUzcsrJkTwKO207K0rMnIoxGkDGnrwes2Lo3 fQykMhNvmVoY49Gdo+ML2r3pWAaCBwayWXQ6kkYS8SrseUrk+Y8NDxAlCHZVHyrOB0QzTdYrs59 FvuC/aCDeVUiKLTRaH5pvF3cpcxpIvPz40vU= X-Google-Smtp-Source: AGHT+IFZgdnQQjNxx8ghjAcICekZILUDfTG+OshKCf0R9bGe78OIZA2mDQRW7kigxJY2ri5dUHihpg== X-Received: by 2002:a05:6000:4011:b0:38d:badf:9df5 with SMTP id ffacd0b85a97d-392641bfd05mr5345571f8f.17.1741727568219; Tue, 11 Mar 2025 14:12:48 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 1/8] x86/regs: Fold x86_64/regs.h into it's single includer Date: Tue, 11 Mar 2025 21:10:36 +0000 Message-Id: <20250311211043.3629696-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250311211043.3629696-1-andrew.cooper3@citrix.com> References: <20250311211043.3629696-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/include/asm/regs.h | 21 ++++++++++++++++++- xen/arch/x86/include/asm/x86_64/regs.h | 28 -------------------------- 2 files changed, 20 insertions(+), 29 deletions(-) delete mode 100644 xen/arch/x86/include/asm/x86_64/regs.h diff --git a/xen/arch/x86/include/asm/regs.h b/xen/arch/x86/include/asm/regs.h index ddf5e14e5719..4f2f06b60161 100644 --- a/xen/arch/x86/include/asm/regs.h +++ b/xen/arch/x86/include/asm/regs.h @@ -2,7 +2,26 @@ #ifndef __X86_REGS_H__ #define __X86_REGS_H__ -#include +#define ring_0(r) (((r)->cs & 3) == 0) +#define ring_1(r) (((r)->cs & 3) == 1) +#define ring_2(r) (((r)->cs & 3) == 2) +#define ring_3(r) (((r)->cs & 3) == 3) + +#define guest_kernel_mode(v, r) \ + (!is_pv_32bit_vcpu(v) ? \ + (ring_3(r) && ((v)->arch.flags & TF_kernel_mode)) : \ + (ring_1(r))) + +#define permit_softint(dpl, v, r) \ + ((dpl) >= (guest_kernel_mode(v, r) ? 1 : 3)) + +/* Check for null trap callback handler: Is the EIP null? */ +#define null_trap_bounce(v, tb) \ + (!is_pv_32bit_vcpu(v) ? ((tb)->eip == 0) : (((tb)->cs & ~3) == 0)) + +/* Number of bytes of on-stack execution state to be context-switched. */ +/* NB. Segment registers and bases are not saved/restored on x86/64 stack. */ +#define CTXT_SWITCH_STACK_BYTES (offsetof(struct cpu_user_regs, es)) #define guest_mode(r) \ ({ \ diff --git a/xen/arch/x86/include/asm/x86_64/regs.h b/xen/arch/x86/include/asm/x86_64/regs.h deleted file mode 100644 index 171cf9a2e217..000000000000 --- a/xen/arch/x86/include/asm/x86_64/regs.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _X86_64_REGS_H -#define _X86_64_REGS_H - -#include -#include - -#define ring_0(r) (((r)->cs & 3) == 0) -#define ring_1(r) (((r)->cs & 3) == 1) -#define ring_2(r) (((r)->cs & 3) == 2) -#define ring_3(r) (((r)->cs & 3) == 3) - -#define guest_kernel_mode(v, r) \ - (!is_pv_32bit_vcpu(v) ? \ - (ring_3(r) && ((v)->arch.flags & TF_kernel_mode)) : \ - (ring_1(r))) - -#define permit_softint(dpl, v, r) \ - ((dpl) >= (guest_kernel_mode(v, r) ? 1 : 3)) - -/* Check for null trap callback handler: Is the EIP null? */ -#define null_trap_bounce(v, tb) \ - (!is_pv_32bit_vcpu(v) ? ((tb)->eip == 0) : (((tb)->cs & ~3) == 0)) - -/* Number of bytes of on-stack execution state to be context-switched. */ -/* NB. Segment registers and bases are not saved/restored on x86/64 stack. */ -#define CTXT_SWITCH_STACK_BYTES (offsetof(struct cpu_user_regs, es)) - -#endif From patchwork Tue Mar 11 21:10:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14012703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D04B8C282EC for ; Tue, 11 Mar 2025 21:13:08 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.909298.1316294 (Exim 4.92) (envelope-from ) id 1ts6uD-0000mW-Px; Tue, 11 Mar 2025 21:12:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 909298.1316294; Tue, 11 Mar 2025 21:12:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uD-0000mG-MZ; Tue, 11 Mar 2025 21:12:53 +0000 Received: by outflank-mailman (input) for mailman id 909298; Tue, 11 Mar 2025 21:12:51 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uB-0008V9-T0 for xen-devel@lists.xenproject.org; Tue, 11 Mar 2025 21:12:51 +0000 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [2a00:1450:4864:20::332]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 96898c2d-febd-11ef-9898-31a8f345e629; Tue, 11 Mar 2025 22:12:50 +0100 (CET) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-43690d4605dso37356815e9.0 for ; Tue, 11 Mar 2025 14:12:50 -0700 (PDT) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. [92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfba9sm19480872f8f.39.2025.03.11.14.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 14:12:48 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 96898c2d-febd-11ef-9898-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741727569; x=1742332369; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3tUvTAv3blqytxViw6Vvd9NJKdvVm3sZY5QDWdB8lnM=; b=iL/AhS5u/a8tlcYimgK2oHOuYGIjbPkDKm1TC8UnNVOwGkJvdpgLDhLezZnIXw3+xz /Wn7+QvbgUJvFXnz6fsk8UEL5OTfUHbHmbaMd556Evd3Rvqm7FzF7/9gKx1nmYhGAbTz Uyl6OGK84IFbEjIoul10Fq4aIevCDLwJ2wc4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741727569; x=1742332369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3tUvTAv3blqytxViw6Vvd9NJKdvVm3sZY5QDWdB8lnM=; b=HImng6Olq4ld6l2sVEJADauDXPbUMyFv/dQgxnj89hLyClFg2OgpXayu92UTcn3pMp dUtzOt+WuD/GOI9liOFgvPcoxlm/VGBFNIrcB8uBEN/raQcdZvH3/MOvbgqbjYNDEE1v y2tKTnxUc/aYFLfaNkEct3T2YUdrN68mA1hOw15rDLFSvhvxS8t0fb6lA4Gx4pv34d9H g0yUeZERPkxJ5Ug86rnTHi3FIrHyt+dYLHLiv5Ct1A4QGZVJFokSSaJb4Uo4QTX/7zNn 7c6fJllVbHtz4cfIQPdgokzzW3ZklW1lKS6C9LW4rpW9LVu86uCdcwiPUC9UfbRdZ6cF hfVg== X-Gm-Message-State: AOJu0Ywgs0MNM3bKg4lSZeYrSIi8ftzbBk9j0NahSFLF+X6LP04sn+j6 Q5aYS2x5T4GwRI37hvFae3PlyNQevrBRkLsP+91PfYGMX1uZnSaotM4+RUwUqE7pkbsdCxxdNg8 I X-Gm-Gg: ASbGncsOogRdUp4qwEpPwaJ6/pDgRhOeJyGY6Uw2San8NKLHg2S0mLOKxymdz9P8NC1 KmYzLcafnIt4lfKR1vZ2lBeCT9r6D9e429RlQM5C/2UJCdqPTW792pdIIVWeFrBoqw3Of4wfEbn cpxz2wY+oaBT2YxAq70e1+/yCAkC+vtrRKGA3/b+JA43t9JRvI9TFmUJ1BnWID2I6IoLay5kGpu 18s9ZYsRUDJy/oPSvLgfMm3RJn01WPOtRjcAcJwinQVJQNjWYkkaEyuIv97UqTjfeI9iCZttMa2 /bPUN0IWeMCmENQ/a7eZ7ET2eFuqq160Vw7mTGfFTffjas68qYL4Ox+6/qMQeB3zHXjglQCYJ16 nHB5sL8NPC0oMSI8nlxbDjXKP X-Google-Smtp-Source: AGHT+IHDtuMEgcwGjelrzYRwcrT2OmMihNokulS7s+soekb61kdamUYko2fDPfbSIEcFLf335JFhLw== X-Received: by 2002:a05:6000:18a3:b0:391:2df9:772d with SMTP id ffacd0b85a97d-39132d3bad8mr17084750f8f.13.1741727569105; Tue, 11 Mar 2025 14:12:49 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 2/8] x86/traps: Rework register state printing to use a struct Date: Tue, 11 Mar 2025 21:10:37 +0000 Message-Id: <20250311211043.3629696-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250311211043.3629696-1-andrew.cooper3@citrix.com> References: <20250311211043.3629696-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 ... in preference to the crs[8] array. This avoids abusing crs[5..7] for the fs/gs bases, giving them proper named fields instead, and avoids storage for cr1 which is unused in the x86 architecture. In show_registers(), remove a redundant read_cr2(). read_registers() already did the same, and it is only the PV path which needs to override with arch_get_cr2(). In vcpu_show_registers(), express the gsb/gss decision using SWAP(). The determination is going to get even more complicated under FRED. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/x86_64/traps.c | 96 +++++++++++++++++++++---------------- 1 file changed, 54 insertions(+), 42 deletions(-) diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index ac0fafd72d31..01b4f0623282 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -23,6 +23,11 @@ #include #include +struct extra_state +{ + unsigned long cr0, cr2, cr3, cr4; + unsigned long fsb, gsb, gss; +}; static void print_xen_info(void) { @@ -35,28 +40,29 @@ static void print_xen_info(void) enum context { CTXT_hypervisor, CTXT_pv_guest, CTXT_hvm_guest }; -/* (ab)use crs[5..7] for fs/gs bases. */ -static void read_registers(struct cpu_user_regs *regs, unsigned long crs[8]) +static void read_registers(struct cpu_user_regs *regs, struct extra_state *state) { - crs[0] = read_cr0(); - crs[2] = read_cr2(); - crs[3] = read_cr3(); - crs[4] = read_cr4(); + state->cr0 = read_cr0(); + state->cr2 = read_cr2(); + state->cr3 = read_cr3(); + state->cr4 = read_cr4(); + read_sregs(regs); - crs[5] = read_fs_base(); - crs[6] = read_gs_base(); - crs[7] = read_gs_shadow(); + + state->fsb = read_fs_base(); + state->gsb = read_gs_base(); + state->gss = read_gs_shadow(); } static void get_hvm_registers(struct vcpu *v, struct cpu_user_regs *regs, - unsigned long crs[8]) + struct extra_state *state) { struct segment_register sreg; - crs[0] = v->arch.hvm.guest_cr[0]; - crs[2] = v->arch.hvm.guest_cr[2]; - crs[3] = v->arch.hvm.guest_cr[3]; - crs[4] = v->arch.hvm.guest_cr[4]; + state->cr0 = v->arch.hvm.guest_cr[0]; + state->cr2 = v->arch.hvm.guest_cr[2]; + state->cr3 = v->arch.hvm.guest_cr[3]; + state->cr4 = v->arch.hvm.guest_cr[4]; hvm_get_segment_register(v, x86_seg_cs, &sreg); regs->cs = sreg.sel; @@ -69,20 +75,20 @@ static void get_hvm_registers(struct vcpu *v, struct cpu_user_regs *regs, hvm_get_segment_register(v, x86_seg_fs, &sreg); regs->fs = sreg.sel; - crs[5] = sreg.base; + state->fsb = sreg.base; hvm_get_segment_register(v, x86_seg_gs, &sreg); regs->gs = sreg.sel; - crs[6] = sreg.base; + state->gsb = sreg.base; hvm_get_segment_register(v, x86_seg_ss, &sreg); regs->ss = sreg.sel; - crs[7] = hvm_get_reg(v, MSR_SHADOW_GS_BASE); + state->gss = hvm_get_reg(v, MSR_SHADOW_GS_BASE); } static void _show_registers( - const struct cpu_user_regs *regs, unsigned long crs[8], + const struct cpu_user_regs *regs, const struct extra_state *state, enum context context, const struct vcpu *v) { static const char *const context_names[] = { @@ -112,10 +118,10 @@ static void _show_registers( printk("r12: %016lx r13: %016lx r14: %016lx\n", regs->r12, regs->r13, regs->r14); printk("r15: %016lx cr0: %016lx cr4: %016lx\n", - regs->r15, crs[0], crs[4]); - printk("cr3: %016lx cr2: %016lx\n", crs[3], crs[2]); + regs->r15, state->cr0, state->cr4); + printk("cr3: %016lx cr2: %016lx\n", state->cr3, state->cr2); printk("fsb: %016lx gsb: %016lx gss: %016lx\n", - crs[5], crs[6], crs[7]); + state->fsb, state->gsb, state->gss); printk("ds: %04x es: %04x fs: %04x gs: %04x " "ss: %04x cs: %04x\n", regs->ds, regs->es, regs->fs, @@ -125,34 +131,33 @@ static void _show_registers( void show_registers(const struct cpu_user_regs *regs) { struct cpu_user_regs fault_regs = *regs; - unsigned long fault_crs[8]; + struct extra_state fault_state; enum context context; struct vcpu *v = system_state >= SYS_STATE_smp_boot ? current : NULL; if ( guest_mode(regs) && is_hvm_vcpu(v) ) { - get_hvm_registers(v, &fault_regs, fault_crs); + get_hvm_registers(v, &fault_regs, &fault_state); context = CTXT_hvm_guest; } else { - read_registers(&fault_regs, fault_crs); + read_registers(&fault_regs, &fault_state); if ( guest_mode(regs) ) { context = CTXT_pv_guest; - fault_crs[2] = arch_get_cr2(v); + fault_state.cr2 = arch_get_cr2(v); } else { context = CTXT_hypervisor; - fault_crs[2] = read_cr2(); } } print_xen_info(); printk("CPU: %d\n", smp_processor_id()); - _show_registers(&fault_regs, fault_crs, context, v); + _show_registers(&fault_regs, &fault_state, context, v); if ( ler_msr && !guest_mode(regs) ) { @@ -173,34 +178,41 @@ void vcpu_show_registers(struct vcpu *v) { const struct cpu_user_regs *regs = &v->arch.user_regs; struct cpu_user_regs aux_regs; + struct extra_state state; enum context context; - unsigned long crs[8]; if ( is_hvm_vcpu(v) ) { aux_regs = *regs; - get_hvm_registers(v, &aux_regs, crs); + get_hvm_registers(v, &aux_regs, &state); regs = &aux_regs; context = CTXT_hvm_guest; } else { bool kernel = guest_kernel_mode(v, regs); + unsigned long gsb, gss; + + state.cr0 = v->arch.pv.ctrlreg[0]; + state.cr2 = arch_get_cr2(v); + state.cr3 = pagetable_get_paddr(kernel + ? v->arch.guest_table + : v->arch.guest_table_user); + state.cr4 = v->arch.pv.ctrlreg[4]; + + gsb = v->arch.pv.gs_base_user; + gss = v->arch.pv.gs_base_kernel; + if ( kernel ) + SWAP(gsb, gss); - crs[0] = v->arch.pv.ctrlreg[0]; - crs[2] = arch_get_cr2(v); - crs[3] = pagetable_get_paddr(kernel ? - v->arch.guest_table : - v->arch.guest_table_user); - crs[4] = v->arch.pv.ctrlreg[4]; - crs[5] = v->arch.pv.fs_base; - crs[6 + !kernel] = v->arch.pv.gs_base_kernel; - crs[7 - !kernel] = v->arch.pv.gs_base_user; + state.fsb = v->arch.pv.fs_base; + state.gsb = gsb; + state.gss = gss; context = CTXT_pv_guest; } - _show_registers(regs, crs, context, v); + _show_registers(regs, &state, context, v); } void show_page_walk(unsigned long addr) @@ -268,7 +280,7 @@ void show_page_walk(unsigned long addr) void asmlinkage do_double_fault(struct cpu_user_regs *regs) { unsigned int cpu; - unsigned long crs[8]; + struct extra_state state; console_force_unlock(); @@ -279,10 +291,10 @@ void asmlinkage do_double_fault(struct cpu_user_regs *regs) printk("*** DOUBLE FAULT ***\n"); print_xen_info(); - read_registers(regs, crs); + read_registers(regs, &state); printk("CPU: %d\n", cpu); - _show_registers(regs, crs, CTXT_hypervisor, NULL); + _show_registers(regs, &state, CTXT_hypervisor, NULL); show_code(regs); show_stack_overflow(cpu, regs); From patchwork Tue Mar 11 21:10:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14012704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A6F7C28B2F for ; Tue, 11 Mar 2025 21:13:11 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.909297.1316284 (Exim 4.92) (envelope-from ) id 1ts6uC-0000XY-J6; Tue, 11 Mar 2025 21:12:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 909297.1316284; Tue, 11 Mar 2025 21:12:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uC-0000XP-FU; Tue, 11 Mar 2025 21:12:52 +0000 Received: by outflank-mailman (input) for mailman id 909297; Tue, 11 Mar 2025 21:12:51 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uB-0008Uq-D9 for xen-devel@lists.xenproject.org; Tue, 11 Mar 2025 21:12:51 +0000 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [2a00:1450:4864:20::430]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 96d77c12-febd-11ef-9ab9-95dc52dad729; Tue, 11 Mar 2025 22:12:50 +0100 (CET) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-39133f709f5so2403710f8f.0 for ; Tue, 11 Mar 2025 14:12:50 -0700 (PDT) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. 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See commit 6065a05adf15 ("x86/traps: 'Fix' safety of read_registers() in #DF path"). There are 3 callers of _show_registers(): 1. vcpu_show_registers(), which always operates on a scheduled-out vCPU, where v->arch.user_regs (or aux_regs on the stack) is always in-bounds. 2. show_registers() where regs is always an on-stack frame. regs is copied into a local variable first (which is an OoB read for constructs such as WARN()), before being modified (so no OoB write). 3. do_double_fault(), where regs is adjacent to the stack guard page, and written into directly. This is an out of bounds read and write, with a bodge to avoid the writes hitting the guard page. Include the data segment selectors in struct extra_state, and use those fields instead of the fields in regs. This resolves the OoB write on the #DF path. Resolve the OoB read in show_registers() by doing a partial memcpy() rather than full structure copy. This is temporary until we've finished untangling the vm86 fields fully. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/x86_64/traps.c | 39 +++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index 01b4f0623282..23622cdb1440 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -27,6 +27,7 @@ struct extra_state { unsigned long cr0, cr2, cr3, cr4; unsigned long fsb, gsb, gss; + uint16_t ds, es, fs, gs; }; static void print_xen_info(void) @@ -40,18 +41,21 @@ static void print_xen_info(void) enum context { CTXT_hypervisor, CTXT_pv_guest, CTXT_hvm_guest }; -static void read_registers(struct cpu_user_regs *regs, struct extra_state *state) +static void read_registers(struct extra_state *state) { state->cr0 = read_cr0(); state->cr2 = read_cr2(); state->cr3 = read_cr3(); state->cr4 = read_cr4(); - read_sregs(regs); - state->fsb = read_fs_base(); state->gsb = read_gs_base(); state->gss = read_gs_shadow(); + + asm ( "mov %%ds, %0" : "=m" (state->ds) ); + asm ( "mov %%es, %0" : "=m" (state->es) ); + asm ( "mov %%fs, %0" : "=m" (state->fs) ); + asm ( "mov %%gs, %0" : "=m" (state->gs) ); } static void get_hvm_registers(struct vcpu *v, struct cpu_user_regs *regs, @@ -68,17 +72,17 @@ static void get_hvm_registers(struct vcpu *v, struct cpu_user_regs *regs, regs->cs = sreg.sel; hvm_get_segment_register(v, x86_seg_ds, &sreg); - regs->ds = sreg.sel; + state->ds = sreg.sel; hvm_get_segment_register(v, x86_seg_es, &sreg); - regs->es = sreg.sel; + state->es = sreg.sel; hvm_get_segment_register(v, x86_seg_fs, &sreg); - regs->fs = sreg.sel; + state->fs = sreg.sel; state->fsb = sreg.base; hvm_get_segment_register(v, x86_seg_gs, &sreg); - regs->gs = sreg.sel; + state->gs = sreg.sel; state->gsb = sreg.base; hvm_get_segment_register(v, x86_seg_ss, &sreg); @@ -124,17 +128,23 @@ static void _show_registers( state->fsb, state->gsb, state->gss); printk("ds: %04x es: %04x fs: %04x gs: %04x " "ss: %04x cs: %04x\n", - regs->ds, regs->es, regs->fs, - regs->gs, regs->ss, regs->cs); + state->ds, state->es, state->fs, + state->gs, regs->ss, regs->cs); } void show_registers(const struct cpu_user_regs *regs) { - struct cpu_user_regs fault_regs = *regs; + struct cpu_user_regs fault_regs; struct extra_state fault_state; enum context context; struct vcpu *v = system_state >= SYS_STATE_smp_boot ? current : NULL; + /* + * Don't read beyond the end of the hardware frame. It is out of bounds + * for WARN()/etc. + */ + memcpy(&fault_regs, regs, offsetof(struct cpu_user_regs, es)); + if ( guest_mode(regs) && is_hvm_vcpu(v) ) { get_hvm_registers(v, &fault_regs, &fault_state); @@ -142,7 +152,7 @@ void show_registers(const struct cpu_user_regs *regs) } else { - read_registers(&fault_regs, &fault_state); + read_registers(&fault_state); if ( guest_mode(regs) ) { @@ -209,6 +219,11 @@ void vcpu_show_registers(struct vcpu *v) state.gsb = gsb; state.gss = gss; + state.ds = v->arch.user_regs.ds; + state.es = v->arch.user_regs.es; + state.fs = v->arch.user_regs.fs; + state.gs = v->arch.user_regs.gs; + context = CTXT_pv_guest; } @@ -291,7 +306,7 @@ void asmlinkage do_double_fault(struct cpu_user_regs *regs) printk("*** DOUBLE FAULT ***\n"); print_xen_info(); - read_registers(regs, &state); + read_registers(&state); printk("CPU: %d\n", cpu); _show_registers(regs, &state, CTXT_hypervisor, NULL); From patchwork Tue Mar 11 21:10:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14012711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DC62C282EC for ; Tue, 11 Mar 2025 21:13:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.909299.1316300 (Exim 4.92) (envelope-from ) id 1ts6uE-0000pv-4S; Tue, 11 Mar 2025 21:12:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 909299.1316300; Tue, 11 Mar 2025 21:12:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uD-0000pD-UJ; Tue, 11 Mar 2025 21:12:53 +0000 Received: by outflank-mailman (input) for mailman id 909299; Tue, 11 Mar 2025 21:12:52 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uC-0008Uq-DK for xen-devel@lists.xenproject.org; Tue, 11 Mar 2025 21:12:52 +0000 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [2a00:1450:4864:20::42b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9793e51b-febd-11ef-9ab9-95dc52dad729; Tue, 11 Mar 2025 22:12:51 +0100 (CET) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-3913d129c1aso194570f8f.0 for ; Tue, 11 Mar 2025 14:12:51 -0700 (PDT) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. 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The discussed "proper fix" has now been implemented, and the #DF path no longer writes out-of-bounds. Restore the proper #DF IST pointer. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné Only 5 years late... --- xen/arch/x86/cpu/common.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index e8d4ca3203be..b934ce7ca487 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -847,13 +847,7 @@ void load_system_tables(void) tss->ist[IST_MCE - 1] = stack_top + (1 + IST_MCE) * PAGE_SIZE; tss->ist[IST_NMI - 1] = stack_top + (1 + IST_NMI) * PAGE_SIZE; tss->ist[IST_DB - 1] = stack_top + (1 + IST_DB) * PAGE_SIZE; - /* - * Gross bodge. The #DF handler uses the vm86 fields of cpu_user_regs - * beyond the hardware frame. Adjust the stack entrypoint so this - * doesn't manifest as an OoB write which hits the guard page. - */ - tss->ist[IST_DF - 1] = stack_top + (1 + IST_DF) * PAGE_SIZE - - (sizeof(struct cpu_user_regs) - offsetof(struct cpu_user_regs, es)); + tss->ist[IST_DF - 1] = stack_top + (1 + IST_DF) * PAGE_SIZE; tss->bitmap = IOBMP_INVALID_OFFSET; /* All other stack pointers poisioned. */ From patchwork Tue Mar 11 21:10:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14012709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83B43C28B2E for ; Tue, 11 Mar 2025 21:13:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.909300.1316314 (Exim 4.92) (envelope-from ) id 1ts6uF-0001HQ-Es; Tue, 11 Mar 2025 21:12:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 909300.1316314; Tue, 11 Mar 2025 21:12:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uF-0001G3-B0; Tue, 11 Mar 2025 21:12:55 +0000 Received: by outflank-mailman (input) for mailman id 909300; Tue, 11 Mar 2025 21:12:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uE-0008V9-Ao for xen-devel@lists.xenproject.org; Tue, 11 Mar 2025 21:12:54 +0000 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [2a00:1450:4864:20::435]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9810a7ff-febd-11ef-9898-31a8f345e629; Tue, 11 Mar 2025 22:12:52 +0100 (CET) Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3912c09bea5so4964100f8f.1 for ; Tue, 11 Mar 2025 14:12:52 -0700 (PDT) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. 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In both arch_{get,set}_info_guest(), expand the memcpy()/XLAT_cpu_user_regs() to copy the fields individually. This will allow us to eventually make them different types. No practical change. The compat cases are identical, while the non-compat cases no longer copy _pad fields. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné Should we really be copying error_code/entry_vector? They're already listed as explicitly private fields, and I don't think anything good can come of providing/consuming them. --- xen/arch/x86/domain.c | 42 ++++++++++++++++++++++++++++++++++++++++-- xen/arch/x86/domctl.c | 42 ++++++++++++++++++++++++++++++++++++++++-- xen/include/xlat.lst | 2 -- 3 files changed, 80 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index a42fa5480593..bc0816c71495 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1196,7 +1196,26 @@ int arch_set_info_guest( if ( !compat ) { - memcpy(&v->arch.user_regs, &c.nat->user_regs, sizeof(c.nat->user_regs)); + v->arch.user_regs.rbx = c.nat->user_regs.rbx; + v->arch.user_regs.rcx = c.nat->user_regs.rcx; + v->arch.user_regs.rdx = c.nat->user_regs.rdx; + v->arch.user_regs.rsi = c.nat->user_regs.rsi; + v->arch.user_regs.rdi = c.nat->user_regs.rdi; + v->arch.user_regs.rbp = c.nat->user_regs.rbp; + v->arch.user_regs.rax = c.nat->user_regs.rax; + v->arch.user_regs.error_code = c.nat->user_regs.error_code; + v->arch.user_regs.entry_vector = c.nat->user_regs.entry_vector; + v->arch.user_regs.rip = c.nat->user_regs.rip; + v->arch.user_regs.cs = c.nat->user_regs.cs; + v->arch.user_regs.saved_upcall_mask = c.nat->user_regs.saved_upcall_mask; + v->arch.user_regs.rflags = c.nat->user_regs.rflags; + v->arch.user_regs.rsp = c.nat->user_regs.rsp; + v->arch.user_regs.ss = c.nat->user_regs.ss; + v->arch.user_regs.es = c.nat->user_regs.es; + v->arch.user_regs.ds = c.nat->user_regs.ds; + v->arch.user_regs.fs = c.nat->user_regs.fs; + v->arch.user_regs.gs = c.nat->user_regs.gs; + if ( is_pv_domain(d) ) memcpy(v->arch.pv.trap_ctxt, c.nat->trap_ctxt, sizeof(c.nat->trap_ctxt)); @@ -1204,7 +1223,26 @@ int arch_set_info_guest( #ifdef CONFIG_COMPAT else { - XLAT_cpu_user_regs(&v->arch.user_regs, &c.cmp->user_regs); + v->arch.user_regs.ebx = c.cmp->user_regs.ebx; + v->arch.user_regs.ecx = c.cmp->user_regs.ecx; + v->arch.user_regs.edx = c.cmp->user_regs.edx; + v->arch.user_regs.esi = c.cmp->user_regs.esi; + v->arch.user_regs.edi = c.cmp->user_regs.edi; + v->arch.user_regs.ebp = c.cmp->user_regs.ebp; + v->arch.user_regs.eax = c.cmp->user_regs.eax; + v->arch.user_regs.error_code = c.cmp->user_regs.error_code; + v->arch.user_regs.entry_vector = c.cmp->user_regs.entry_vector; + v->arch.user_regs.eip = c.cmp->user_regs.eip; + v->arch.user_regs.cs = c.cmp->user_regs.cs; + v->arch.user_regs.saved_upcall_mask = c.cmp->user_regs.saved_upcall_mask; + v->arch.user_regs.eflags = c.cmp->user_regs.eflags; + v->arch.user_regs.esp = c.cmp->user_regs.esp; + v->arch.user_regs.ss = c.cmp->user_regs.ss; + v->arch.user_regs.es = c.cmp->user_regs.es; + v->arch.user_regs.ds = c.cmp->user_regs.ds; + v->arch.user_regs.fs = c.cmp->user_regs.fs; + v->arch.user_regs.gs = c.cmp->user_regs.gs; + if ( is_pv_domain(d) ) { for ( i = 0; i < ARRAY_SIZE(c.cmp->trap_ctxt); ++i ) diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 3044f706de1c..7ab9e9176b58 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1399,7 +1399,26 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) c(flags |= VGCF_online); if ( !compat ) { - memcpy(&c.nat->user_regs, &v->arch.user_regs, sizeof(c.nat->user_regs)); + c.nat->user_regs.rbx = v->arch.user_regs.rbx; + c.nat->user_regs.rcx = v->arch.user_regs.rcx; + c.nat->user_regs.rdx = v->arch.user_regs.rdx; + c.nat->user_regs.rsi = v->arch.user_regs.rsi; + c.nat->user_regs.rdi = v->arch.user_regs.rdi; + c.nat->user_regs.rbp = v->arch.user_regs.rbp; + c.nat->user_regs.rax = v->arch.user_regs.rax; + c.nat->user_regs.error_code = v->arch.user_regs.error_code; + c.nat->user_regs.entry_vector = v->arch.user_regs.entry_vector; + c.nat->user_regs.rip = v->arch.user_regs.rip; + c.nat->user_regs.cs = v->arch.user_regs.cs; + c.nat->user_regs.saved_upcall_mask = v->arch.user_regs.saved_upcall_mask; + c.nat->user_regs.rflags = v->arch.user_regs.rflags; + c.nat->user_regs.rsp = v->arch.user_regs.rsp; + c.nat->user_regs.ss = v->arch.user_regs.ss; + c.nat->user_regs.es = v->arch.user_regs.es; + c.nat->user_regs.ds = v->arch.user_regs.ds; + c.nat->user_regs.fs = v->arch.user_regs.fs; + c.nat->user_regs.gs = v->arch.user_regs.gs; + if ( is_pv_domain(d) ) memcpy(c.nat->trap_ctxt, v->arch.pv.trap_ctxt, sizeof(c.nat->trap_ctxt)); @@ -1407,7 +1426,26 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) #ifdef CONFIG_COMPAT else { - XLAT_cpu_user_regs(&c.cmp->user_regs, &v->arch.user_regs); + c.cmp->user_regs.ebx = v->arch.user_regs.ebx; + c.cmp->user_regs.ecx = v->arch.user_regs.ecx; + c.cmp->user_regs.edx = v->arch.user_regs.edx; + c.cmp->user_regs.esi = v->arch.user_regs.esi; + c.cmp->user_regs.edi = v->arch.user_regs.edi; + c.cmp->user_regs.ebp = v->arch.user_regs.ebp; + c.cmp->user_regs.eax = v->arch.user_regs.eax; + c.cmp->user_regs.error_code = v->arch.user_regs.error_code; + c.cmp->user_regs.entry_vector = v->arch.user_regs.entry_vector; + c.cmp->user_regs.eip = v->arch.user_regs.eip; + c.cmp->user_regs.cs = v->arch.user_regs.cs; + c.cmp->user_regs.saved_upcall_mask = v->arch.user_regs.saved_upcall_mask; + c.cmp->user_regs.eflags = v->arch.user_regs.eflags; + c.cmp->user_regs.esp = v->arch.user_regs.esp; + c.cmp->user_regs.ss = v->arch.user_regs.ss; + c.cmp->user_regs.es = v->arch.user_regs.es; + c.cmp->user_regs.ds = v->arch.user_regs.ds; + c.cmp->user_regs.fs = v->arch.user_regs.fs; + c.cmp->user_regs.gs = v->arch.user_regs.gs; + if ( is_pv_domain(d) ) { for ( i = 0; i < ARRAY_SIZE(c.cmp->trap_ctxt); ++i ) diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst index 3c7b6c6830a9..6d6c6cfab251 100644 --- a/xen/include/xlat.lst +++ b/xen/include/xlat.lst @@ -34,8 +34,6 @@ ? pmu_intel_ctxt arch-x86/pmu.h ? pmu_regs arch-x86/pmu.h -! cpu_user_regs arch-x86/xen-@arch@.h - ? cpu_offline_action arch-x86/xen-mca.h ? mc arch-x86/xen-mca.h ! mc_fetch arch-x86/xen-mca.h From patchwork Tue Mar 11 21:10:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14012707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A8CBC282EC for ; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfba9sm19480872f8f.39.2025.03.11.14.12.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 14:12:52 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 98957bdf-febd-11ef-9898-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741727573; x=1742332373; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HFrngM1TgUNgBBj30oxGvF9xc2D1FyOkZS0ffbcsnNo=; b=ZCmh4i4JgAKTo1LHKdU6uMR9gNlEoE8oBaT53eeKw20Se9LYK3B9FEO412staOOBgT fLaFItscMaVoGKKoZOJktK+2wJwqTF9kQrQUt+OJkZnOP3kSRJ3+PAbRva2yJMM3ADKI cP1BCgT3LpoOnvT0lSKJhU7U2naJPYuplq67Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741727573; x=1742332373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HFrngM1TgUNgBBj30oxGvF9xc2D1FyOkZS0ffbcsnNo=; b=r64FFSn55FZuZjEF+T96U0lBJmnrHi/vdeHsGeGusGIF8KzzL8oD2tpJXU4amZbyqn JuEcW/caAar7ikqdhfzKkojE7c4OGSirWy4WJQFfFZAaUfvFxon3DvonuBXi5/aecoqb hQF0uRHn8fVuyEvbqC7gtjb/ZyT0a5EOLREoe4YzvxZ6b5+YOO5+4JRfp3Uhas5w1R/K 8vK+iZRHPCMv8+JjWMCVPIlP3ssBdYjcD2B/33NqjDCNlxd44LRyWNyFYGUI2z525W5m k/xKviBqn10CVKB6wIDITrUj/3j5hK/JHhBer65HLKGs9kmWdigtBA2jmMUVe/2VYPXU btkg== X-Gm-Message-State: AOJu0YxzWnqalK50v2E28C0C6xyn+Uenc8a3efAb/XtlRmjbZ/s2LB/Z ko0KEXMjUIkWNDaKz0vG1obISWsmlkBu53VGMFKAWHMn0iYO4neq8IRZELdxC6pACLmHwWyfbGI R X-Gm-Gg: ASbGncvrfiL546OWVZxWYJutbdDL8WHSVyMbKyGyZkT0is517Rbzb5zQru94jMMO1eS FOzTeFkdrcA4fGdSMOY+4qt1I9AQry9PSF6+wdPxKqjV61nWGxBnLNhIxq9BU5wmI2vWs7gIbHi RY7ns0za9dTganjHk2QyEYXTAV3+tiqLIsGACF2vwT4xIpoNNs0FJUmdPOzeRd3k59hsJ77k5wm P2PiR6W/2itRdmvBDXH4xYCVWc0pdIncuPsqk2lk/tsl8uOi0rBIqlKATlQXoxcrteWhzCxYF1u Y8LB5vMWK6/WCPlTB/BFqCuMFfn/TwgQfLRVYTTFWxf494Yt8KR2EjecH/Z20AJ9AW7SGMQmPun kUDmA5/r26tGJjOYnmBd7XGuO X-Google-Smtp-Source: AGHT+IHLu90I7Oxb9f9B2V1ljG4U7asaIi+yb+uqAksLnpE42DOph4w9vUxKd6hge8kToyDbSdwnEg== X-Received: by 2002:a05:6000:1885:b0:390:fbdd:994d with SMTP id ffacd0b85a97d-39264694d6bmr6113045f8f.27.1741727572721; Tue, 11 Mar 2025 14:12:52 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 6/8] x86/pv: Store the data segment selectors outside of cpu_user_regs Date: Tue, 11 Mar 2025 21:10:41 +0000 Message-Id: <20250311211043.3629696-7-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250311211043.3629696-1-andrew.cooper3@citrix.com> References: <20250311211043.3629696-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 In order to support FRED, we're going to have to remove the {ds..gs} fields from struct cpu_user_regs. This will impact v->arch.user_regs. These fields are unused for HVM guests, but for PV hold the selector values when the vCPU is scheduled out. Introduce new fields for the selectors in struct pv_vcpu, and update: * {save,load}_segments(), context switching * arch_{set,set}_info_guest(), hypercalls * vcpu_show_registers(), diagnostics * dom0_construct(), PV dom0 to use the new storage. This removes the final user of read_sregs() so drop it too. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/domain.c | 70 +++++++++++++++---------------- xen/arch/x86/domctl.c | 16 +++---- xen/arch/x86/include/asm/domain.h | 2 + xen/arch/x86/include/asm/regs.h | 8 ---- xen/arch/x86/pv/dom0_build.c | 6 ++- xen/arch/x86/x86_64/traps.c | 8 ++-- 6 files changed, 53 insertions(+), 57 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index bc0816c71495..e9c331be6f63 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1211,10 +1211,10 @@ int arch_set_info_guest( v->arch.user_regs.rflags = c.nat->user_regs.rflags; v->arch.user_regs.rsp = c.nat->user_regs.rsp; v->arch.user_regs.ss = c.nat->user_regs.ss; - v->arch.user_regs.es = c.nat->user_regs.es; - v->arch.user_regs.ds = c.nat->user_regs.ds; - v->arch.user_regs.fs = c.nat->user_regs.fs; - v->arch.user_regs.gs = c.nat->user_regs.gs; + v->arch.pv.es = c.nat->user_regs.es; + v->arch.pv.ds = c.nat->user_regs.ds; + v->arch.pv.fs = c.nat->user_regs.fs; + v->arch.pv.gs = c.nat->user_regs.gs; if ( is_pv_domain(d) ) memcpy(v->arch.pv.trap_ctxt, c.nat->trap_ctxt, @@ -1238,10 +1238,10 @@ int arch_set_info_guest( v->arch.user_regs.eflags = c.cmp->user_regs.eflags; v->arch.user_regs.esp = c.cmp->user_regs.esp; v->arch.user_regs.ss = c.cmp->user_regs.ss; - v->arch.user_regs.es = c.cmp->user_regs.es; - v->arch.user_regs.ds = c.cmp->user_regs.ds; - v->arch.user_regs.fs = c.cmp->user_regs.fs; - v->arch.user_regs.gs = c.cmp->user_regs.gs; + v->arch.pv.es = c.nat->user_regs.es; + v->arch.pv.ds = c.nat->user_regs.ds; + v->arch.pv.fs = c.nat->user_regs.fs; + v->arch.pv.gs = c.nat->user_regs.gs; if ( is_pv_domain(d) ) { @@ -1729,7 +1729,6 @@ long do_vcpu_op(int cmd, unsigned int vcpuid, XEN_GUEST_HANDLE_PARAM(void) arg) */ static void load_segments(struct vcpu *n) { - struct cpu_user_regs *uregs = &n->arch.user_regs; unsigned long gsb = 0, gss = 0; bool compat = is_pv_32bit_vcpu(n); bool all_segs_okay = true, fs_gs_done = false; @@ -1762,7 +1761,7 @@ static void load_segments(struct vcpu *n) if ( !(n->arch.flags & TF_kernel_mode) ) SWAP(gsb, gss); - if ( using_svm() && (uregs->fs | uregs->gs) <= 3 ) + if ( using_svm() && (n->arch.pv.fs | n->arch.pv.gs) <= 3 ) fs_gs_done = svm_load_segs(n->arch.pv.ldt_ents, LDT_VIRT_START(n), n->arch.pv.fs_base, gsb, gss); } @@ -1771,12 +1770,12 @@ static void load_segments(struct vcpu *n) { load_LDT(n); - TRY_LOAD_SEG(fs, uregs->fs); - TRY_LOAD_SEG(gs, uregs->gs); + TRY_LOAD_SEG(fs, n->arch.pv.fs); + TRY_LOAD_SEG(gs, n->arch.pv.gs); } - TRY_LOAD_SEG(ds, uregs->ds); - TRY_LOAD_SEG(es, uregs->es); + TRY_LOAD_SEG(ds, n->arch.pv.ds); + TRY_LOAD_SEG(es, n->arch.pv.es); if ( !fs_gs_done && !compat ) { @@ -1829,13 +1828,13 @@ static void load_segments(struct vcpu *n) } if ( ret | - put_guest(rflags, esp - 1) | - put_guest(cs_and_mask, esp - 2) | - put_guest(regs->eip, esp - 3) | - put_guest(uregs->gs, esp - 4) | - put_guest(uregs->fs, esp - 5) | - put_guest(uregs->es, esp - 6) | - put_guest(uregs->ds, esp - 7) ) + put_guest(rflags, esp - 1) | + put_guest(cs_and_mask, esp - 2) | + put_guest(regs->eip, esp - 3) | + put_guest(n->arch.pv.gs, esp - 4) | + put_guest(n->arch.pv.fs, esp - 5) | + put_guest(n->arch.pv.es, esp - 6) | + put_guest(n->arch.pv.ds, esp - 7) ) domain_crash(n->domain, "Error creating compat failsafe callback frame\n"); @@ -1861,17 +1860,17 @@ static void load_segments(struct vcpu *n) cs_and_mask = (unsigned long)regs->cs | ((unsigned long)vcpu_info(n, evtchn_upcall_mask) << 32); - if ( put_guest(regs->ss, rsp - 1) | - put_guest(regs->rsp, rsp - 2) | - put_guest(rflags, rsp - 3) | - put_guest(cs_and_mask, rsp - 4) | - put_guest(regs->rip, rsp - 5) | - put_guest(uregs->gs, rsp - 6) | - put_guest(uregs->fs, rsp - 7) | - put_guest(uregs->es, rsp - 8) | - put_guest(uregs->ds, rsp - 9) | - put_guest(regs->r11, rsp - 10) | - put_guest(regs->rcx, rsp - 11) ) + if ( put_guest(regs->ss, rsp - 1) | + put_guest(regs->rsp, rsp - 2) | + put_guest(rflags, rsp - 3) | + put_guest(cs_and_mask, rsp - 4) | + put_guest(regs->rip, rsp - 5) | + put_guest(n->arch.pv.gs, rsp - 6) | + put_guest(n->arch.pv.fs, rsp - 7) | + put_guest(n->arch.pv.es, rsp - 8) | + put_guest(n->arch.pv.ds, rsp - 9) | + put_guest(regs->r11, rsp - 10) | + put_guest(regs->rcx, rsp - 11) ) domain_crash(n->domain, "Error creating failsafe callback frame\n"); @@ -1900,9 +1899,10 @@ static void load_segments(struct vcpu *n) */ static void save_segments(struct vcpu *v) { - struct cpu_user_regs *regs = &v->arch.user_regs; - - read_sregs(regs); + asm ( "mov %%ds, %0" : "=m" (v->arch.pv.ds) ); + asm ( "mov %%es, %0" : "=m" (v->arch.pv.es) ); + asm ( "mov %%fs, %0" : "=m" (v->arch.pv.fs) ); + asm ( "mov %%gs, %0" : "=m" (v->arch.pv.gs) ); if ( !is_pv_32bit_vcpu(v) ) { diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 7ab9e9176b58..833fcbd4bbb6 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1414,10 +1414,10 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) c.nat->user_regs.rflags = v->arch.user_regs.rflags; c.nat->user_regs.rsp = v->arch.user_regs.rsp; c.nat->user_regs.ss = v->arch.user_regs.ss; - c.nat->user_regs.es = v->arch.user_regs.es; - c.nat->user_regs.ds = v->arch.user_regs.ds; - c.nat->user_regs.fs = v->arch.user_regs.fs; - c.nat->user_regs.gs = v->arch.user_regs.gs; + c.nat->user_regs.es = v->arch.pv.es; + c.nat->user_regs.ds = v->arch.pv.ds; + c.nat->user_regs.fs = v->arch.pv.fs; + c.nat->user_regs.gs = v->arch.pv.gs; if ( is_pv_domain(d) ) memcpy(c.nat->trap_ctxt, v->arch.pv.trap_ctxt, @@ -1441,10 +1441,10 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) c.cmp->user_regs.eflags = v->arch.user_regs.eflags; c.cmp->user_regs.esp = v->arch.user_regs.esp; c.cmp->user_regs.ss = v->arch.user_regs.ss; - c.cmp->user_regs.es = v->arch.user_regs.es; - c.cmp->user_regs.ds = v->arch.user_regs.ds; - c.cmp->user_regs.fs = v->arch.user_regs.fs; - c.cmp->user_regs.gs = v->arch.user_regs.gs; + c.cmp->user_regs.es = v->arch.pv.es; + c.cmp->user_regs.ds = v->arch.pv.ds; + c.cmp->user_regs.fs = v->arch.pv.fs; + c.cmp->user_regs.gs = v->arch.pv.gs; if ( is_pv_domain(d) ) { diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index 5fc1d1e5d01a..7fa409cb3055 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -546,6 +546,8 @@ struct pv_vcpu bool syscall32_disables_events; bool sysenter_disables_events; + uint16_t ds, es, fs, gs; + /* * 64bit segment bases. * diff --git a/xen/arch/x86/include/asm/regs.h b/xen/arch/x86/include/asm/regs.h index 4f2f06b60161..c05b9207c281 100644 --- a/xen/arch/x86/include/asm/regs.h +++ b/xen/arch/x86/include/asm/regs.h @@ -41,12 +41,4 @@ __sel; \ }) -static inline void read_sregs(struct cpu_user_regs *regs) -{ - asm ( "mov %%ds, %0" : "=m" (regs->ds) ); - asm ( "mov %%es, %0" : "=m" (regs->es) ); - asm ( "mov %%fs, %0" : "=m" (regs->fs) ); - asm ( "mov %%gs, %0" : "=m" (regs->gs) ); -} - #endif /* __X86_REGS_H__ */ diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c index 96e28c7b6a77..bcaacc7586c0 100644 --- a/xen/arch/x86/pv/dom0_build.c +++ b/xen/arch/x86/pv/dom0_build.c @@ -1020,8 +1020,10 @@ static int __init dom0_construct(struct boot_info *bi, struct domain *d) * [rAX,rBX,rCX,rDX,rDI,rBP,R8-R15 are zero] */ regs = &v->arch.user_regs; - regs->ds = regs->es = regs->fs = regs->gs = - (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); + v->arch.pv.ds = (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); + v->arch.pv.es = (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); + v->arch.pv.fs = (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); + v->arch.pv.gs = (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); regs->ss = (compat ? FLAT_COMPAT_KERNEL_SS : FLAT_KERNEL_SS); regs->cs = (compat ? FLAT_COMPAT_KERNEL_CS : FLAT_KERNEL_CS); regs->rip = parms.virt_entry; diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index 23622cdb1440..cb06f99021d1 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -219,10 +219,10 @@ void vcpu_show_registers(struct vcpu *v) state.gsb = gsb; state.gss = gss; - state.ds = v->arch.user_regs.ds; - state.es = v->arch.user_regs.es; - state.fs = v->arch.user_regs.fs; - state.gs = v->arch.user_regs.gs; + state.ds = v->arch.pv.ds; + state.es = v->arch.pv.es; + state.fs = v->arch.pv.fs; + state.gs = v->arch.pv.gs; context = CTXT_pv_guest; } From patchwork Tue Mar 11 21:10:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14012706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12E2EC28B2E for ; Tue, 11 Mar 2025 21:13:20 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.909301.1316323 (Exim 4.92) (envelope-from ) id 1ts6uG-0001Xc-PM; Tue, 11 Mar 2025 21:12:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 909301.1316323; Tue, 11 Mar 2025 21:12:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uG-0001XB-Lc; Tue, 11 Mar 2025 21:12:56 +0000 Received: by outflank-mailman (input) for mailman id 909301; Tue, 11 Mar 2025 21:12:55 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ts6uF-0008Uq-Eb for xen-devel@lists.xenproject.org; Tue, 11 Mar 2025 21:12:55 +0000 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [2a00:1450:4864:20::332]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 995413d1-febd-11ef-9ab9-95dc52dad729; Tue, 11 Mar 2025 22:12:54 +0100 (CET) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-43cf628cb14so1463345e9.1 for ; Tue, 11 Mar 2025 14:12:54 -0700 (PDT) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. [92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfba9sm19480872f8f.39.2025.03.11.14.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 14:12:53 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 995413d1-febd-11ef-9ab9-95dc52dad729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741727574; x=1742332374; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NAtTpo8KH5ZdCgDPrWpHEeo3BLVM30dQttgId7v1Tq0=; b=p8OjYOowWQgfPjVC0rfrPG4rSUM1ul8Qwv8SixxBguaUSx9ifZaSvyTQLQ6Jf3jDo0 35mVXhP1oqJVqQQ/lf/jKT6p5IutAs+Crg4uSsChPbRCndlxsLECakcNUZ8c9/IkFmrU 8oZ1QDOnnqhy/1XG9m5D7j8+Yr1Qpc2KSyzOs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741727574; x=1742332374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NAtTpo8KH5ZdCgDPrWpHEeo3BLVM30dQttgId7v1Tq0=; b=e3TFIiS0l6vYdCNSjrXrzUnE1w48jvOMqGbVThYpWPReNQRQbns6VTP0EqMoyTmS+7 IEu72sG7PD4mtpsfDQL2P636lR4WDSQFx+pd6HmuiUjggnAqusKkoj0Bc/QOd8v6CkN5 y/8XTe70ILc4LdntDX4FH/ILj15S/NDs02Nq8yAWtguNPYvFvym8+ApW/oJOAslytgKO 1AhvMdq6rASWvkE8LMVYs+uySJw8rnRSbhucJXreVHj4Tk5yFFPvgsQJrL7LuXBBqOnb pPASFVPIjfdZ2QhN0S2yXQGWx3eWKt44T3o2ya+rlMn+D0TgmhXTDqGgx1bbLhHX86Rw mmTA== X-Gm-Message-State: AOJu0YyvUr8y2cuYgdO3gvAF6pdwq/y9DbaUXZHu20hUUju+NJB3KXvd Tvqmy7FoKzTSkA3xFggZAK3rGy2hvBwCsxB8BnRQr49iHq3Uhu6mzVw8kvpAKMxxZk5Pm1b8Ob4 n X-Gm-Gg: ASbGncsFXvYs9cPCu6kfYa/EvfRqSWROBiT5U+leF7sYqmWyem58e3rWnhHv/twMZra X7HqXGpJnVWrdYtqINEoB25rZDPBjuGnq29hZyU4QjlpgtyDXnodpW1j56FVPRgjy7XaZEm19Rf WAhiryLtQBJbFe57tcO1ECZ1rYtaIijxZJaoCqPkRBKR0mkGuXfPROzFWrYnfT8t0ufMEDfavjL MBmsRVl2tNv+6WPfDbByeMyw2EFVP692a/8PldMnsBxKcDU09VQPKYBBU+rby+7l8c8mI8s7CDc ZOUsDLn1El2plHwgaR2DdtG4pMJEMvkXx3WL+ImFGoQUhIZvV9g0pe5YmrwXndewMZvnqvWNFAK VTTkSt8xFx4NhOsdCWaPNUgyc X-Google-Smtp-Source: AGHT+IHsWfSRfuAMivDIwLvlJJIaz7ykB32KoN0VA83oPOE7JV3fL2q8AIh/7qFxYjs79LGwjeHuaA== X-Received: by 2002:a5d:5f82:0:b0:38d:b12f:60d1 with SMTP id ffacd0b85a97d-3926d5ef561mr5495427f8f.26.1741727574005; Tue, 11 Mar 2025 14:12:54 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 7/8] x86/public: Split the struct cpu_user_regs type Date: Tue, 11 Mar 2025 21:10:42 +0000 Message-Id: <20250311211043.3629696-8-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250311211043.3629696-1-andrew.cooper3@citrix.com> References: <20250311211043.3629696-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 In order to support FRED, we're going to have to remove the {ds..gs} fields from struct cpu_user_regs, meaning that it is going to have to become a different type to the structure embedded in vcpu_guest_context_u. struct cpu_user_regs is a name used in common Xen code (i.e. needs to stay using this name), so renaming the public struct to be guest_user_regs in Xen's view only. Introduce a brand hew cpu-user-regs.h, currently containing a duplicate structure. This removes the need for current.h to include public/xen.h, and highlights a case where the emulator was picking up cpu_user_regs transitively. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné Jan: Is this what you intended? cpu_user_regs_t and the guest handle don't seem to be used anywhere. I'm tempted to exclude them from Xen builds. --- xen/arch/x86/include/asm/cpu-user-regs.h | 69 ++++++++++++++++++++++++ xen/arch/x86/include/asm/current.h | 3 +- xen/arch/x86/x86_emulate/private.h | 2 + xen/include/public/arch-x86/xen-x86_32.h | 8 +++ xen/include/public/arch-x86/xen-x86_64.h | 8 +++ xen/include/public/arch-x86/xen.h | 6 +++ 6 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 xen/arch/x86/include/asm/cpu-user-regs.h diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/include/asm/cpu-user-regs.h new file mode 100644 index 000000000000..845b41a22ef2 --- /dev/null +++ b/xen/arch/x86/include/asm/cpu-user-regs.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef X86_CPU_USER_REGS_H +#define X86_CPU_USER_REGS_H + +#define DECL_REG_LOHI(which) union { \ + uint64_t r ## which ## x; \ + uint32_t e ## which ## x; \ + uint16_t which ## x; \ + struct { \ + uint8_t which ## l; \ + uint8_t which ## h; \ + }; \ +} +#define DECL_REG_LO8(name) union { \ + uint64_t r ## name; \ + uint32_t e ## name; \ + uint16_t name; \ + uint8_t name ## l; \ +} +#define DECL_REG_LO16(name) union { \ + uint64_t r ## name; \ + uint32_t e ## name; \ + uint16_t name; \ +} +#define DECL_REG_HI(num) union { \ + uint64_t r ## num; \ + uint32_t r ## num ## d; \ + uint16_t r ## num ## w; \ + uint8_t r ## num ## b; \ +} + +struct cpu_user_regs +{ + DECL_REG_HI(15); + DECL_REG_HI(14); + DECL_REG_HI(13); + DECL_REG_HI(12); + DECL_REG_LO8(bp); + DECL_REG_LOHI(b); + DECL_REG_HI(11); + DECL_REG_HI(10); + DECL_REG_HI(9); + DECL_REG_HI(8); + DECL_REG_LOHI(a); + DECL_REG_LOHI(c); + DECL_REG_LOHI(d); + DECL_REG_LO8(si); + DECL_REG_LO8(di); + uint32_t error_code; + uint32_t entry_vector; + DECL_REG_LO16(ip); + uint16_t cs, _pad0[1]; + uint8_t saved_upcall_mask; + uint8_t _pad1[3]; + DECL_REG_LO16(flags); /* rflags.IF == !saved_upcall_mask */ + DECL_REG_LO8(sp); + uint16_t ss, _pad2[3]; + uint16_t es, _pad3[3]; + uint16_t ds, _pad4[3]; + uint16_t fs, _pad5[3]; + uint16_t gs, _pad6[3]; +}; + +#undef DECL_REG_HI +#undef DECL_REG_LO16 +#undef DECL_REG_LO8 +#undef DECL_REG_LOHI + +#endif /* X86_CPU_USER_REGS_H */ diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h index bcec328c9875..243d17ef79fd 100644 --- a/xen/arch/x86/include/asm/current.h +++ b/xen/arch/x86/include/asm/current.h @@ -9,7 +9,8 @@ #include #include -#include + +#include /* * Xen's cpu stacks are 8 pages (8-page aligned), arranged as: diff --git a/xen/arch/x86/x86_emulate/private.h b/xen/arch/x86/x86_emulate/private.h index ef4745f56e27..dde4d3e3ccef 100644 --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -10,6 +10,8 @@ # include # include + +# include # include # include # include diff --git a/xen/include/public/arch-x86/xen-x86_32.h b/xen/include/public/arch-x86/xen-x86_32.h index 9e3bf06b121e..cd21438ab12b 100644 --- a/xen/include/public/arch-x86/xen-x86_32.h +++ b/xen/include/public/arch-x86/xen-x86_32.h @@ -114,6 +114,10 @@ #define __DECL_REG_LO16(name) uint32_t e ## name #endif +#ifdef __XEN__ +#define cpu_user_regs guest_user_regs +#endif + struct cpu_user_regs { __DECL_REG_LO8(b); __DECL_REG_LO8(c); @@ -139,6 +143,10 @@ struct cpu_user_regs { typedef struct cpu_user_regs cpu_user_regs_t; DEFINE_XEN_GUEST_HANDLE(cpu_user_regs_t); +#ifdef __XEN__ +#undef cpu_user_regs +#endif + #undef __DECL_REG_LO8 #undef __DECL_REG_LO16 diff --git a/xen/include/public/arch-x86/xen-x86_64.h b/xen/include/public/arch-x86/xen-x86_64.h index 43f6e3d22001..4388e20eaf49 100644 --- a/xen/include/public/arch-x86/xen-x86_64.h +++ b/xen/include/public/arch-x86/xen-x86_64.h @@ -159,6 +159,10 @@ struct iret_context { #define __DECL_REG_HI(num) uint64_t r ## num #endif +#ifdef __XEN__ +#define cpu_user_regs guest_user_regs +#endif + struct cpu_user_regs { __DECL_REG_HI(15); __DECL_REG_HI(14); @@ -192,6 +196,10 @@ struct cpu_user_regs { typedef struct cpu_user_regs cpu_user_regs_t; DEFINE_XEN_GUEST_HANDLE(cpu_user_regs_t); +#ifdef __XEN__ +#undef cpu_user_regs +#endif + #undef __DECL_REG #undef __DECL_REG_LOHI #undef __DECL_REG_LO8 diff --git a/xen/include/public/arch-x86/xen.h b/xen/include/public/arch-x86/xen.h index fc2487986642..3b0fd05432f4 100644 --- a/xen/include/public/arch-x86/xen.h +++ b/xen/include/public/arch-x86/xen.h @@ -173,7 +173,13 @@ struct vcpu_guest_context { #define _VGCF_online 5 #define VGCF_online (1<<_VGCF_online) unsigned long flags; /* VGCF_* flags */ + +#ifdef __XEN__ + struct guest_user_regs user_regs; /* User-level CPU registers */ +#else struct cpu_user_regs user_regs; /* User-level CPU registers */ +#endif + struct trap_info trap_ctxt[256]; /* Virtual IDT */ unsigned long ldt_base, ldt_ents; /* LDT (linear address, # ents) */ unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */ From patchwork Tue Mar 11 21:10:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14012710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B921C282EC for ; Tue, 11 Mar 2025 21:13:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.909304.1316343 (Exim 4.92) (envelope-from ) id 1ts6uI-00020o-R9; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfba9sm19480872f8f.39.2025.03.11.14.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 14:12:54 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 99dc90dc-febd-11ef-9898-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741727575; x=1742332375; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ELTmL9+t2/EDs2TC9abOCsUNCvZ0XnggaJfjdGBA0Ow=; b=sv6x1b5lRPp3R5QZVsb2eTiHoCifdt1oLZv67tFOledHBnLnxCxVrw39GMMD7Gyp+u AopoVyeVZUb08VOF7zmgVz55dG6ekpCgIvR0KPfw+kw4QFDeoesLvZUgg1EEWWk+HnkL ESREkNL5DYJBjlAlYk2FhiLIde+l0jFqOcXcc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741727575; x=1742332375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ELTmL9+t2/EDs2TC9abOCsUNCvZ0XnggaJfjdGBA0Ow=; b=FNpjbWxNBFqfCe+1lm8LFc8MzLYnPpnxCYDkMTG+3zqhA3nDnRcgrVQDFp9bxhxVi4 9X4cExC4/2ZHgX7sZEpfJqkXMfUKAzP/lfTaxwq+C4X4cOL6jsn72RKLwOyKopCntwHU oq90puHn8Q/F9ntvK5GvzhRwR/aBrbLJ3/r//OUJUC/odqWsEyTBeLK9VHc1fSjuvLbw UlrOpq/x/k385rgYKa/WK9QzUIp8Df+Xr7AA+471LcrLZvAKk6O754P8SDlZNl0BW8r9 0bRomnjuL6XUAGMQHQrzgu9Y+RakUUogtzIz9OMNCEiqTixMPrq1Zxydo2LicvuFlZWt dWJA== X-Gm-Message-State: AOJu0Yz1GfcKmUSzzFyXvAE3ARMKtOX6Tpj53CoBqU0s4RD2t85yrmdv DwEFAdRPyeDiZxDb9ZO1aJf451LSPBHkqEgLZK40QHW+o1v2bRj7B3RVvW+9lQF6OAkBJh38l0l S X-Gm-Gg: ASbGncuh6VBUBxpYKnAq7KRxWdyBfqDWCW/HoLJ4XqjQP8mMOlp8nFnNoz8K/gwe3r3 iyyR8WEZDkVZ3yQxe9GfbXD1vXKGQy/ZSkqfgervWr+GtIsc1NASrqUX28EooGfCVw6URvWiJTZ yMQvmfV0kcrTffPS2B3bN2xmMTdUXAPYIElB+5hDs3uwKPEKosAUEiCnsfmCFiYBGzwtZ1W+XtQ /PoUqh7VrUJ19QHvKl77vVwjYqpYo6muV9Q7b4d2iyPUZbwzGlFVwlIJl268af8WTpQwQEGkWGx TGju4R+XhVjPm4mQy3DAmDFRMpOIZi1+YNbRH2H6meEBgqknwRRZxL55bq0o/54MVTkaVmFg438 qXa0Tqv7H4OFG+QoIQXyNnZfd X-Google-Smtp-Source: AGHT+IHrlMMVED2OGhb/bvwgeOVR+uJmOwxEzLT1GTo4/e+macMG8RVTwXUyCSFe7YtaPlSC/PlVSw== X-Received: by 2002:a5d:6d8a:0:b0:391:12a5:3cb3 with SMTP id ffacd0b85a97d-39132d2af8bmr15755406f8f.3.1741727574848; Tue, 11 Mar 2025 14:12:54 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 8/8] x86: Drop the vm86 segments selectors from struct cpu_user_regs Date: Tue, 11 Mar 2025 21:10:43 +0000 Message-Id: <20250311211043.3629696-9-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250311211043.3629696-1-andrew.cooper3@citrix.com> References: <20250311211043.3629696-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 The data segment registers are part of the on-stack IRET frame when interrupting Virtual 8086 mode, but this ceased being relevant for Xen in commit 5d1181a5ea5e ("xen: Remove x86_32 build target.") in 2012. With all other cleanup in place, delete the fields so we can introduce FRED support which uses this space for different data. Everywhere which used the es field as an offset in cpu_user_regs needs adjusting. However, they'll change again for FRED, so no cleanup is performed at this juncture. This also undoes the OoB Read workaround in show_registers(), which can now switch back to being simple structure copy. No functional change, but a lot of rearranging of stack and struct layout under the hood. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/cpu/common.c | 2 +- xen/arch/x86/include/asm/cpu-user-regs.h | 4 ---- xen/arch/x86/include/asm/current.h | 8 ++++---- xen/arch/x86/include/asm/hvm/hvm.h | 4 ---- xen/arch/x86/include/asm/regs.h | 3 +-- xen/arch/x86/traps.c | 2 +- xen/arch/x86/x86_64/asm-offsets.c | 2 +- xen/arch/x86/x86_64/traps.c | 8 +------- 8 files changed, 9 insertions(+), 24 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index b934ce7ca487..654f847e1f8c 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -917,7 +917,7 @@ void load_system_tables(void) * Defer checks until exception support is sufficiently set up. */ BUILD_BUG_ON((sizeof(struct cpu_info) - - offsetof(struct cpu_info, guest_cpu_user_regs.es)) & 0xf); + sizeof(struct cpu_user_regs)) & 0xf); BUG_ON(system_state != SYS_STATE_early_boot && (stack_bottom & 0xf)); } diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/include/asm/cpu-user-regs.h index 845b41a22ef2..c4cc8640c23f 100644 --- a/xen/arch/x86/include/asm/cpu-user-regs.h +++ b/xen/arch/x86/include/asm/cpu-user-regs.h @@ -55,10 +55,6 @@ struct cpu_user_regs DECL_REG_LO16(flags); /* rflags.IF == !saved_upcall_mask */ DECL_REG_LO8(sp); uint16_t ss, _pad2[3]; - uint16_t es, _pad3[3]; - uint16_t ds, _pad4[3]; - uint16_t fs, _pad5[3]; - uint16_t gs, _pad6[3]; }; #undef DECL_REG_HI diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h index 243d17ef79fd..a7c9473428b2 100644 --- a/xen/arch/x86/include/asm/current.h +++ b/xen/arch/x86/include/asm/current.h @@ -106,12 +106,12 @@ static inline struct cpu_info *get_cpu_info(void) #define get_per_cpu_offset() (get_cpu_info()->per_cpu_offset) /* - * Get the bottom-of-stack, as stored in the per-CPU TSS. This actually points - * into the middle of cpu_info.guest_cpu_user_regs, at the section that - * precisely corresponds to a CPU trap frame. + * Get the bottom-of-stack, as stored in the per-CPU TSS. This points at the + * end of cpu_info.guest_cpu_user_regs, at the section that precisely + * corresponds to a CPU trap frame. */ #define get_stack_bottom() \ - ((unsigned long)&get_cpu_info()->guest_cpu_user_regs.es) + ((unsigned long)(&get_cpu_info()->guest_cpu_user_regs + 1)) /* * Get the reasonable stack bounds for stack traces and stack dumps. Stack diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h index 963e8201130a..cde6efd7adc0 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -624,10 +624,6 @@ static inline void hvm_sanitize_regs_fields(struct cpu_user_regs *regs, regs->saved_upcall_mask = 0xbf; regs->cs = 0xbeef; regs->ss = 0xbeef; - regs->ds = 0xbeef; - regs->es = 0xbeef; - regs->fs = 0xbeef; - regs->gs = 0xbeef; #endif } diff --git a/xen/arch/x86/include/asm/regs.h b/xen/arch/x86/include/asm/regs.h index c05b9207c281..dcc45ac5af7f 100644 --- a/xen/arch/x86/include/asm/regs.h +++ b/xen/arch/x86/include/asm/regs.h @@ -20,8 +20,7 @@ (!is_pv_32bit_vcpu(v) ? ((tb)->eip == 0) : (((tb)->cs & ~3) == 0)) /* Number of bytes of on-stack execution state to be context-switched. */ -/* NB. Segment registers and bases are not saved/restored on x86/64 stack. */ -#define CTXT_SWITCH_STACK_BYTES (offsetof(struct cpu_user_regs, es)) +#define CTXT_SWITCH_STACK_BYTES sizeof(struct cpu_user_regs) #define guest_mode(r) \ ({ \ diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 5addb1f903d3..27e68285e504 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -416,7 +416,7 @@ unsigned long get_stack_trace_bottom(unsigned long sp) { case 1 ... 4: return ROUNDUP(sp, PAGE_SIZE) - - offsetof(struct cpu_user_regs, es) - sizeof(unsigned long); + sizeof(struct cpu_user_regs) - sizeof(unsigned long); case 6 ... 7: return ROUNDUP(sp, STACK_SIZE) - diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-offsets.c index 630bdc39451d..2258b4ce1b95 100644 --- a/xen/arch/x86/x86_64/asm-offsets.c +++ b/xen/arch/x86/x86_64/asm-offsets.c @@ -52,7 +52,7 @@ void __dummy__(void) OFFSET(UREGS_eflags, struct cpu_user_regs, rflags); OFFSET(UREGS_rsp, struct cpu_user_regs, rsp); OFFSET(UREGS_ss, struct cpu_user_regs, ss); - OFFSET(UREGS_kernel_sizeof, struct cpu_user_regs, es); + DEFINE(UREGS_kernel_sizeof, sizeof(struct cpu_user_regs)); BLANK(); /* diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index cb06f99021d1..78c5b7a1e300 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -134,17 +134,11 @@ static void _show_registers( void show_registers(const struct cpu_user_regs *regs) { - struct cpu_user_regs fault_regs; + struct cpu_user_regs fault_regs = *regs; struct extra_state fault_state; enum context context; struct vcpu *v = system_state >= SYS_STATE_smp_boot ? current : NULL; - /* - * Don't read beyond the end of the hardware frame. It is out of bounds - * for WARN()/etc. - */ - memcpy(&fault_regs, regs, offsetof(struct cpu_user_regs, es)); - if ( guest_mode(regs) && is_hvm_vcpu(v) ) { get_hvm_registers(v, &fault_regs, &fault_state);