From patchwork Mon Mar 17 02:59:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 14018598 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A71418DB1F; Mon, 17 Mar 2025 02:59:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742180376; cv=none; b=Lv31WnEkQ/m2NS6cHax+AT0flgO5yrJG3thmOiFV7yaZ4rAsJ77lWG2hXv5BlKzczPc6Q+O5oyyfgS4KuPD/2fymUaPuD2j9FVELtpyfHmcMLH0Go2+mkJwfBSJJeGr3g0C1gssgM1zvz1iU/k8iZuChXYrqnyD2etNXbKFrg5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742180376; c=relaxed/simple; bh=rX/ZenZP7G7r5j6emPUNCKaBksCD1nSwxpFZhZ0I5YQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RItSxtlMAFVZJntE1Tjm/MbQRYtH5Cvtk6qKmJfciK97dcoiCBJiMqbmZm5fwE+ib2wLA9vn9MeL3awxdGrHwfsLPfcfC50Fwvc0cHa3c2P1vHffHGE8rJBsNgZ0SafAgFaEDAYB3GIcF67Jcaqb9Va6YEva0apKylvjPw4W1gc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 17 Mar 2025 10:59:22 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 17 Mar 2025 10:59:22 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , CC: Subject: [net-next 1/4] ARM: dts: aspeed-g6:add scu to mac for RGMII delay Date: Mon, 17 Mar 2025 10:59:19 +0800 Message-ID: <20250317025922.1526937-2-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250317025922.1526937-1-jacky_chou@aspeedtech.com> References: <20250317025922.1526937-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The RGMII delay of AST2600 MAC is configured in SCU register, so add scu regmap into mac node. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 8ed715bd53aa..17e979d616dc 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -236,6 +236,7 @@ mac0: ethernet@1e660000 { reg = <0x1e660000 0x180>; interrupts = ; clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; + scu = <&syscon>; status = "disabled"; }; @@ -244,6 +245,7 @@ mac1: ethernet@1e680000 { reg = <0x1e680000 0x180>; interrupts = ; clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; + scu = <&syscon>; status = "disabled"; }; @@ -252,6 +254,7 @@ mac2: ethernet@1e670000 { reg = <0x1e670000 0x180>; interrupts = ; clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; + scu = <&syscon>; status = "disabled"; }; @@ -260,6 +263,7 @@ mac3: ethernet@1e690000 { reg = <0x1e690000 0x180>; interrupts = ; clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; + scu = <&syscon>; status = "disabled"; }; From patchwork Mon Mar 17 02:59:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 14018599 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C78018FDBE; Mon, 17 Mar 2025 02:59:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742180378; cv=none; b=r6FJ/ZcfYU3GqO3F457DTBvDHZDQQh0ywpdAj1F5XIkb+/rIz1YclREDPu3C1el6req/9uIyeMVpb+koQA7/u+9waWOMV9nZRA1N2rVQcfJhMQQtPn+Lo1Zqdj9D1twmSp+0Tf2gEybw3jTUBilPvgRyqPyta+mDqT/ggYcyAZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742180378; c=relaxed/simple; bh=079BKpVziC3jsx7LXamG6iEwiPaLW3laD5D7Qe1sT3E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FJgHHnUOaEs0JY75Q2gCqYD9upCrNvbSdLim6URQcaqga2lZehha4417hGNvOPhMd4was0H5L5FzF0gLNRzCXdyY8HCGXJs4nyGqhMLy8LTro+8clKZIBlVGvlMMa95SMLDZtn7gl/8gOZ6/ts7s8SOYIqdblbJj2YEsXDj8XVQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 17 Mar 2025 10:59:22 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 17 Mar 2025 10:59:22 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , CC: Subject: [net-next 2/4] ARM: dts: ast2600-evb: add default RGMII delay Date: Mon, 17 Mar 2025 10:59:20 +0800 Message-ID: <20250317025922.1526937-3-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250317025922.1526937-1-jacky_chou@aspeedtech.com> References: <20250317025922.1526937-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Use tx-internal-delay-ps and rx-internal-delay-ps to configure the RGMII delay on MAC. And add default value for AST2600 MAC in dts. Refer to faraday,ftgmac100yaml to know how to configure the RGMII delay. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts index de83c0eb1d6e..1db1f2a02d91 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts @@ -126,6 +126,9 @@ &mac0 { phy-mode = "rgmii-rxid"; phy-handle = <ðphy0>; + tx-internal-delay-ps = <16>; + rx-internal-delay-ps = <10>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii1_default>; }; @@ -137,6 +140,9 @@ &mac1 { phy-mode = "rgmii-rxid"; phy-handle = <ðphy1>; + tx-internal-delay-ps = <16>; + rx-internal-delay-ps = <10>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii2_default>; }; @@ -147,6 +153,9 @@ &mac2 { phy-mode = "rgmii"; phy-handle = <ðphy2>; + tx-internal-delay-ps = <8>; + rx-internal-delay-ps = <4>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii3_default>; }; @@ -157,6 +166,9 @@ &mac3 { phy-mode = "rgmii"; phy-handle = <ðphy3>; + tx-internal-delay-ps = <8>; + rx-internal-delay-ps = <4>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii4_default>; }; From patchwork Mon Mar 17 02:59:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 14018600 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB89B19DF4F; Mon, 17 Mar 2025 02:59:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742180380; cv=none; b=XJ0D5RevuUIp63MV2SA9i6ARh+iKcbVA3bjy39zpSmhIFumZOGkIXO3wHVm/x5vh9uF4VQRE1E/jQdXVlo83xhatOKxjXGNKXcDVGX/u7IXACRudvoK6hTQvJu/RZm0YfYbRpnCqM/HJbw28kyNaok8VKex8BQW/8W/9GaLrsuU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742180380; c=relaxed/simple; bh=GD1LW0vXw+i8B82pbsRQhzGQDzuNi7BRqQCRXF/tsfA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WEmXYqVZKq4LBdp9tNmiyjER8bK3bBQ5a/7lkVc62XdXBSt4RUARIh+i37LmUCGroH0jjtIJOVSGtWxmv4FZ0PTr+Usr/nqUAXoBT3ID96OoW/Mu5PkOiFCPqtlQAMNABrRy8RcUDdUQ31//lz1WrAAns75CkByV0M7ZahjW2Fc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 17 Mar 2025 10:59:22 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 17 Mar 2025 10:59:22 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , CC: Subject: [net-next 3/4] dt-bindings: net: ftgmac100: add rgmii delay properties Date: Mon, 17 Mar 2025 10:59:21 +0800 Message-ID: <20250317025922.1526937-4-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250317025922.1526937-1-jacky_chou@aspeedtech.com> References: <20250317025922.1526937-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Add tx-internal-delay-ps and rx-internal-delay-ps to configure the RGMII delay for MAC. According to ethernet-controller.yaml, they use for RGMII TX and RX delay. In Aspeed desgin, the RGMII delay is a number of ps as unit to set delay, do not use one ps as unit. The values are different from each MAC. So, here describes the property values as index to configure corresponding scu register. Signed-off-by: Jacky Chou --- .../bindings/net/faraday,ftgmac100.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml index 55d6a8379025..c5904aa84e05 100644 --- a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml +++ b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml @@ -66,6 +66,20 @@ properties: type: boolean deprecated: true + rx-internal-delay-ps: + description: + Setting this property to a non-zero number sets the RX internal delay + for the MAC. Use this property value as a index not a ps unit to + configure the corresponding delay register field. And the index range is + 0 to 63. + + tx-internal-delay-ps: + description: + Setting this property to a non-zero number sets the TX internal delay + for the MAC. Use this property value as a index not a ps unit to + configure the corresponding delay register field. And the index range is + 0 to 63. + mdio: $ref: /schemas/net/mdio.yaml# @@ -102,4 +116,4 @@ examples: reg = <1>; }; }; - }; + }; \ No newline at end of file From patchwork Mon Mar 17 02:59:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 14018601 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C98B1A2380; Mon, 17 Mar 2025 02:59:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742180382; cv=none; b=uyskXR8Sd/HXXMLgNmpA55TVKN23u4MjOZ0EOWJRQEKofcWMHZc6lC/p+//MK5x5TYct/hsTOMtiJTUKAwMBRc7HktVhJTn3+Iw3sRlEc77/PEHcHl04rBm6kFeDkluS7ns0YTg7vJPXktS+dWF0QZhQ7+pkWDahbCwb7/5G57o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742180382; c=relaxed/simple; bh=XSyYJ75R9Rc3SDBDuB8CZtXABWuY8O5VgKqquNhvM2s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rhUrW4xEO/BkkL1zSiY1St8bqQeQ5TiJLYZ1C71veqW7439JLVWVatowBpu5781d59YZcXXEfIfJRMhT+5oRgsNP8y6me2SNsuZQ8URyBKIP5jaOdDJMLYAEEL9uXXdH3CyoAE7qd6pEHLFAvaJmXhw/AGJ1FLg4sun6SFXosWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 17 Mar 2025 10:59:22 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 17 Mar 2025 10:59:22 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , CC: Subject: [net-next 4/4] net: ftgmac100: add RGMII delay for AST2600 Date: Mon, 17 Mar 2025 10:59:22 +0800 Message-ID: <20250317025922.1526937-5-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250317025922.1526937-1-jacky_chou@aspeedtech.com> References: <20250317025922.1526937-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Use rx-internal-delay-ps and tx-internal-delay-ps properties to configue the RGMII delay into corresponding register of scu. Currently, the ftgmac100 driver only configures on AST2600 and will be by pass the other platforms. The details are in faraday,ftgmac100.yaml. Signed-off-by: Jacky Chou --- drivers/net/ethernet/faraday/ftgmac100.c | 88 ++++++++++++++++++++++++ drivers/net/ethernet/faraday/ftgmac100.h | 12 ++++ 2 files changed, 100 insertions(+) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c index 17ec35e75a65..ea2061488cba 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.c +++ b/drivers/net/ethernet/faraday/ftgmac100.c @@ -27,6 +27,9 @@ #include #include #include +#include +#include +#include #include "ftgmac100.h" @@ -1812,6 +1815,88 @@ static bool ftgmac100_has_child_node(struct device_node *np, const char *name) return ret; } +static void ftgmac100_set_internal_delay(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct net_device *netdev; + struct ftgmac100 *priv; + struct regmap *scu; + u32 rgmii_tx_delay, rgmii_rx_delay; + u32 dly_reg, tx_dly_mask, rx_dly_mask; + int tx, rx; + + netdev = platform_get_drvdata(pdev); + priv = netdev_priv(netdev); + + tx = of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay); + rx = of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay); + + if (of_device_is_compatible(np, "aspeed,ast2600-mac")) { + /* According to mac base address to get mac index */ + switch (priv->res->start) { + case 0x1e660000: + dly_reg = AST2600_MAC12_CLK_DLY; + tx_dly_mask = AST2600_MAC1_TX_DLY; + rx_dly_mask = AST2600_MAC1_RX_DLY; + rgmii_tx_delay = FIELD_PREP(AST2600_MAC1_TX_DLY, rgmii_tx_delay); + rgmii_rx_delay = FIELD_PREP(AST2600_MAC1_RX_DLY, rgmii_rx_delay); + break; + case 0x1e680000: + dly_reg = AST2600_MAC12_CLK_DLY; + tx_dly_mask = AST2600_MAC2_TX_DLY; + rx_dly_mask = AST2600_MAC2_RX_DLY; + rgmii_tx_delay = FIELD_PREP(AST2600_MAC2_TX_DLY, rgmii_tx_delay); + rgmii_rx_delay = FIELD_PREP(AST2600_MAC2_RX_DLY, rgmii_rx_delay); + break; + case 0x1e670000: + dly_reg = AST2600_MAC34_CLK_DLY; + tx_dly_mask = AST2600_MAC3_TX_DLY; + rx_dly_mask = AST2600_MAC3_RX_DLY; + rgmii_tx_delay = FIELD_PREP(AST2600_MAC3_TX_DLY, rgmii_tx_delay); + rgmii_rx_delay = FIELD_PREP(AST2600_MAC3_RX_DLY, rgmii_rx_delay); + break; + case 0x1e690000: + dly_reg = AST2600_MAC34_CLK_DLY; + tx_dly_mask = AST2600_MAC4_TX_DLY; + rx_dly_mask = AST2600_MAC4_RX_DLY; + rgmii_tx_delay = FIELD_PREP(AST2600_MAC4_TX_DLY, rgmii_tx_delay); + rgmii_rx_delay = FIELD_PREP(AST2600_MAC4_RX_DLY, rgmii_rx_delay); + break; + default: + dev_warn(&pdev->dev, "Invalid mac base address"); + return; + } + } else { + return; + } + + scu = syscon_regmap_lookup_by_phandle(np, "scu"); + if (IS_ERR(scu)) { + dev_warn(&pdev->dev, "failed to map scu base"); + return; + } + + if (!tx) { + /* Use tx-internal-delay-ps as index to configure tx delay + * into scu register. + */ + if (rgmii_tx_delay > 64) + dev_warn(&pdev->dev, "Get invalid tx delay value"); + else + regmap_update_bits(scu, dly_reg, tx_dly_mask, rgmii_tx_delay); + } + + if (!rx) { + /* Use rx-internal-delay-ps as index to configure rx delay + * into scu register. + */ + if (rgmii_tx_delay > 64) + dev_warn(&pdev->dev, "Get invalid rx delay value"); + else + regmap_update_bits(scu, dly_reg, rx_dly_mask, rgmii_rx_delay); + } +} + static int ftgmac100_probe(struct platform_device *pdev) { struct resource *res; @@ -1977,6 +2062,9 @@ static int ftgmac100_probe(struct platform_device *pdev) if (of_device_is_compatible(np, "aspeed,ast2600-mac")) iowrite32(FTGMAC100_TM_DEFAULT, priv->base + FTGMAC100_OFFSET_TM); + + /* Configure RGMII delay if there are the corresponding properties */ + ftgmac100_set_internal_delay(pdev); } /* Default ring sizes */ diff --git a/drivers/net/ethernet/faraday/ftgmac100.h b/drivers/net/ethernet/faraday/ftgmac100.h index 4968f6f0bdbc..d464d287502c 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.h +++ b/drivers/net/ethernet/faraday/ftgmac100.h @@ -271,4 +271,16 @@ struct ftgmac100_rxdes { #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) #define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) +/* Aspeed SCU */ +#define AST2600_MAC12_CLK_DLY 0x340 +#define AST2600_MAC1_TX_DLY GENMASK(5, 0) +#define AST2600_MAC1_RX_DLY GENMASK(17, 12) +#define AST2600_MAC2_TX_DLY GENMASK(11, 6) +#define AST2600_MAC2_RX_DLY GENMASK(23, 18) +#define AST2600_MAC34_CLK_DLY 0x350 +#define AST2600_MAC3_TX_DLY AST2600_MAC1_TX_DLY +#define AST2600_MAC3_RX_DLY AST2600_MAC1_RX_DLY +#define AST2600_MAC4_TX_DLY AST2600_MAC2_TX_DLY +#define AST2600_MAC4_RX_DLY AST2600_MAC2_RX_DLY + #endif /* __FTGMAC100_H */